Efficient mobility enhancement engineering on 65 nm fully silicide complementary metal-oxide-semiconductor field-effect-transistors using second contect etch stop layer process

(1)

Eﬃcient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary

Metal–Oxide–Semiconductor Field-Eﬀect-Transistors Using Second Contect

Etch Stop Layer Process

Chieh-Ming LAI, Yean-Kuen FANG, Chien-Ting LIN, and Wen-Kuan YEH1

Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan 70101, Taiwan, R. O. C.

1_{Department of Electrical Engineering, National University of Kaohsiung,}

No. 700, Kaohsiung University Road, Nan-Tzu Dist, Kaohsiung 811, Taiwan, R.O.C.

(Received September 20, 2006; accepted December 12, 2006; published online April 24, 2007)

In this study, we have applied a second high-stress contect etch stop layer (CESL) in nickel fully silicide complementary metal–oxide–semiconductor field-effect-transistors (Ni FUSI CMOSFETs) and investigated performance characteristics, such as driving capacity, leakages, low-frequency noise (LF noise), and capacitance–voltage (C–V) characteristics. In Ni FUSI nMOSFETs, the effect of the second CESL on the improvement of carrier mobility is apparent. However, the second CESL also induces defects and junction leakages, resulting in a high LF noise and a low accumulation capacitance. Since we adopted the tensile-stressed second CESL, which is profitless improving the performance of pMOSFETs (should be compress-stressed) and apparently degrades the devices’ driving capability, leakages, and LF noise of the devices. Furthermore, the FUSI process does not induce apparent damage that increases the gate leakages of both Ni-FUSI nMOSFETs and pMOSFETs.

[DOI:10.1143/JJAP.46.2127]

KEYWORDS: FUSI, CESL, second CESL, strained engineering

1. Introduction

As the device’s geometry is scaled down continually, issues, such as the boron penetration, polygate depletion, and low carrier mobility become more critical and serious. According to the ITRS Road Map (2003),1) _{a metal gate}

electrode has been proposed to replace a conventional polycrystalline silicon (poly-Si) electrode for future com-plementary metal–oxide–semiconductor field-effect-transis-tors (CMOSFETs) devices in order to achieve an equivalent oxide thickness (EOT) < 1 nm in the next five years. Metal gates have many advantages over poly-Si gates, such as the absence of polygate depletion effects and boron penetration, a very low resistance, and suppressed remote charge scattering.2) Recently, a nickel fully silicided (Ni FUSI) gate electrode has become one of the promising metal gate candidates for its high tunable work function, stable silicide/ gate oxide interface, and compatible CMOS processes.3–6)

However, it is a pity that the FUSI gate technology is not applied to improve the device mobility directly; thus, we still require some strain techniques to improve the mobility.

Channel-strained technologies, such as a relaxed SiGe or epitaxial SiGe layer in a source/drain region for improving the mobility, were widely studied previously. However, for CMOS of 90 nm node and beyond,7,8)_{a new strain}

engineer-ing of high stress contact etch stop layer (CESL) is more popular for its compatibility with a conventional CMOS preparing process and requires no additional epitaxial or lithography process. Thus, integrating the CESL and Ni FUSI gate electrode is expected to be the efficient for enhancing the carrier mobility. However, thus far, no investigation about the effects of the CESL on the perform-ance characteristics of Ni FUSI gate devices has been reported. In this study, we prepared three types of devices (Fig. 1) to investigate the effects of the CESL on the performance characteristics of Ni FUSI gate devices, namely, (a) a conventional device with the first CESL, (b)

a Ni FUSI gate device with the first CESL, and (c) a Ni FUSI gate device with the first and second CESLs. In addition, we also measured low-frequency noise (LF noise) to investigate the effects of FUSI and second CESL processes on the integrated gate.

2. Experimental Procedure

Samples were fabricated by a leading edge 90 nm technology9)with regular process sequences and a salicide formation process was used as a tool to demonstrate the performance characteristics of a device with a gate length of 65 nm (polygate thickness, 1200 A˚ ). The ﬁrst high-tensile-stress CESL (with 1.1 GPa high-tensile-stress and 700 A˚ ) was deposited following S/D cobalt silicidation to form a control device [Fig. 1(a)]. After interlayer dielectric (ILD) SiN and oxide deposition, FUSI CMP planarization was performed to remove top poly-SiN to expose polysilicon with a remaining polygate thickness of around 800 A˚ . In a poly gate FUSI process, Ni silicide was chosen for its low thermal budget and better properties.3–6) _{After the rapid thermal process}

(a)

1st CESL (700A)

(c)

2nd_{tensile CESL (700A)} ILD

(b)

Non stress Post SiN layer (700A)

Fig. 1. Schematic views of 65 nm CMOSFETs with various gate electrodes: (a) conventional gate with ﬁrst CESL (control device), (b) Ni FUSI gate, and (c) Ni FUSI gate covered with the second CESL.

_{E-mail address: [email protected]} Japanese Journal of Applied Physics

Vol. 46, No. 4B, 2007, pp. 2127–2130 #2007 The Japan Society of Applied Physics

(2)

(RTP), a Ni FUSI gate electrode was formed. Next, to maintain a proper reliability as in conventional CESL SiN, a non-stressed post-SiN layer (without stress, 700 A˚ ) was deposited to prevent the exposure of the gate electrode to backend charging and/or damaging [Fig. 1(b)]. Addition-ally, in order to inspect the eﬀects of the second high-tensile-stress CESL on Ni FUSI gate devices, in some Ni-FUSI devices, non-stressed post-SiN layer was replaced by a high-tensile-stressed second CESL [second CESL with 1.1 GPa stress and 700 A˚ , Fig. 1(c)].

3. Results and Discussion

3.1 Eﬀects of the second CESL on nMOSFETs

The ID–VD curves for the 65 nm conventional CESL

nMOSFETs (control devices) and Ni FUSI nMOSFETs with and without the second CESL, which were measured at VD¼0 {1:3 V and VGVTH¼1 V, are shown in Fig. 2.

Apparently, the Ni FUSI gate devices with and without second CESL have a higher driving capacity than the control device because of the higher carrier mobility and larger gate oxide capacitance (Cox). Previous studies2,10)indicated that

Coulomb scattering from remote charges in a polygate or from a polygate/oxide interface results in mobility degra-dation. Moreover, the Cox in the conventional polygate

device decreases owning to the polygate depletion eﬀect. Thus, both mobility degradation and decreased Cox lead to

the lowest driving current in the control device. In other words, the Ni FUSI gate device increases IDto about 14 and

18% for the devices without and with second CESL, respectively. Therefore, the carrier mobility in Ni FUSI nMOSFETs should be further increased by utilizing the second CESL. For the same reason, similar improvements in the transconductance (Gm) were found, as shown in the inset

of Fig. 2. Additionally, the second CESL further improves Gm eﬃciently; thus, the Ni FUSI devices with the second

CESL exhibit the highest Gm. From the plot of Gmvs Vg, the

Gm values of the Ni FUSI devices with and without the

second CESL are observed to increase to 13 and 7%, respectively. Figure 3 shows the ID–VG curves and

sub-threshold swing (SS). In a subsub-threshold region, the control device possesses a larger leakage current than the Ni FUSI devices. We attribute the low subthreshold leakages of the

Ni FUSI devices to the high threshold voltage (VTH) caused

by a positive shift in ﬂatband voltage because of the small work function of NiSi.11)The measured VTHvalues of the Ni

FUSI devices with and without the second CESL and the control device are 0.482, 0.516, and 0.36 V, respectively. Since, VTHis extracted from the maximum Gm, a high ID–VG

curve leads to a small VTH; thus, the Ni FUSI devices

without the second CESL exhibit a higher VTH than the

devices with the second CESL. On the other hand, the extracted subthreshold swing values of the Ni FUSI devices with and without the second CESL and the control device are 79, 75, and 86 mv/dec, respectively. The reduced polygate depletion, which improves the gate control, is responsible for the better subthreshold characteristic in the FUSI gate devices. Furthermore, the second CESL in the Ni FUSI devices induced defects in oxide and at the interface of oxide/Si, weakening the oxide integrity and degrading subthreshold characteristics,12)resulting in a worse SS than that without the second CESL. Moreover, in the the IG–VG

curves (inset in Fig. 3), the Ni FUSI devices possess higher gate leakages than the control device, particularly the devices with the second CESL owing to the damage caused by an additional chemical mechanical polishing (CMP) process in the gate oxide of the FUSI gate devices and the second-CESL-induced stress.

In addition to the DC investigations discussed above, the dynamic impacts of the Ni FUSI process and the second CESL were investigated by low-frequency noise (LF noise) measurement, as shown in Fig. 4. Obviously, the Ni FUSI gate devices possess lower input referred noise spectrum densities (Svg) than the control device. Since Svg is mainly

related to the defecs in oxide and at the Si/oxide inter-face,13–16) the lower Svg values of the Ni FUSI devices are

attributed to the following factors. (a) the reduced remote charge scattering2) _{in FUSI gate devices, (b) the low}

interface defect density (small SS, as shown in Fig. 3) produced by the long thermal process time for the FUSI devices, and (c) the high VTH which causes a markedly low

Ioff in the Ni FUSI devices, as shown in the inset in Fig. 4.

On the other hand, the Ni FUSI devices with the second CESL have a slightly higher Svg(measured at VDS¼0:05 V)

than the devices without the second CESL, indicating that

0.0

0.4

0.8

1.2

0

400

800 1200

65 nm nMOS V G- VT= 1V

Ni FUSI + second CESL Ni FUSI control device

I

D ( µ

A/

µ

m

)

V

_D

(V)

0.0 0.5 1.0 0 50 100 150 200 250 65 nm nMOS control device Ni FUSI + second CESL Ni FUSI Gm (S/ µ m ) V_G-V_TH (V)

Fig. 2. ID–VD and Gm vs VGVT (inset) characteristics of 65 nm

nMOSFETs with various gate electrodes.

-0.5

0.0

0.5

1.0

1.5

10

-11

10

-9

10

-7

10

-5

10

-3

65 nm nMOS V

D

= 0.05 V

V

_G

(V)

I

D ( µ

A/

µ

m

) control device SS:86 Ni FUSI + second CESL SS:79 Ni FUSI SS:75 -0.4 0.0 0.4 0.8 1.2 10-11 10-9 10-7 10-5 65 nm nMOS VD= 0.05V, VS= 0V Ni FUSI + second CESL Ni FUSI control device V G (V) IG (A)

Fig. 3. ID–VG, subthreshold swing, and IG–VG (inset) characteristics of

65 nm nMOSFETs with various gate electrodes.

Jpn. J. Appl. Phys., Vol. 46, No. 4B (2007) C.-M. LAIet al.

(3)

the second CESL induces some interface and oxide defects.12) _{Figure 5 shows gate oxide capacitances (C}

ox);

these capacitances indicate that the Ni FUSI gate reduces the polygate depletions to 1.38 and 1.06 A˚ , and increases the Cox in the inversion region of the Ni FUSI devices with

and without the second CESL to about 8.1 and 5.85%, respectively. Again, the stress-induced defects, which pro-vide leakage paths for charges and reduce the capacitance, cause small improvements in the devices with the second CESL. On the other hand, the increase in the ﬂat band voltage of the Ni FUSI devices results in the positive shifts of the C–V curves.

3.2 Impacts of second CESL on pMOSFETs

Similar to the ID–VD curves of nMOSFET’s, those of

pMOSFETs (Fig. 6) show that the Ni FUSI pMOSFETs without the second CESL have a higher driving capability than the control devices for a high carrier mobility2,10)_and

a larg gate oxide capacitance (Cox). However, the stress

induced by the second CESL is tensile, which does not improve the mobility (should be a compressive stress) as shown by previous studies,17,18) _{thus causing the I}

D of the

pMOS devices with the second CESL to be lower than that of the control device. A similar tendency was found in Gm

characteristics, as shown in the inset in Fig. 6. The smallest and largest Gm values were found in the Ni FUSI

pMOSFETs with and without the second CESL. In other words, the impact of the tensile stress induced by the second CESL on the mobility enhancement of the pMOSFETs is negative. Figure 7 shows the ID–VGcurves and SS values of

three diﬀerent pMOSFETs. The VTH values of the Ni FUSI

pMOSFETs with and without the second CESL and the control device are 0:56, 0:63, and 0:42 V, respectively. Because of the ﬂatband negative shift, the Ni FUSI devices possess large jVTHj values, and low subthreshold leakages.

On the other hand, the extracted subthreshold swing values of the Ni FUSI devices with and without the second CESL and the control device are 86, 94, and 97 mv/dec, respec-tively. The better subthreshold characteristic of the FUSI gate devices is attributed to the reduced polygate depletion, which improves the gate control. However, compared with the nMOSFET’s, the improvements in the Ni FUSI pMOSFETs with the second CESL are not obvious for the detrimental second CESL. The inset in Fig. 6 shows the IG–

10

100 1k

10k

10

-13

10

-12

10

-11 Ni FUSI Ni FUSI + second CESL control device 65 nm nMOS V_G-V_T=0.3 V

Frequency (Hz)

S VG ( V 2 / Hz ) 0.0 0.2 0.4 0.6 0.8 1.0 10-4 10-3 ID ( µ A/ µ m ) control device Ni FUSI + second CESL Ni FUSI

VD (V)

65 nm nMOS

VG=VB=VS= 0V

Fig. 4. Low frequency noise and Ioffcharacteristics of 65 nm nMOSFETs

with various gate electrodes.

-1.0

-0.5

0.0

0.5

1.0

4

6

8

10

12

14

Tox = 16A control device Ni FUSI + second CESL Ni FUSI 65 nm nMOS, W= 10µm, f=100 Hz

Gate capacitance (fF)

V

_G

(V)

Fig. 5. Gate capacitances (Cox) in inversion regions of 65 nm nMOSFETs

0.0 -0.4

-0.8

-1.2

-1.6

0

100

200

300

400

500

control device

Ni FUSI + second CESL Ni FUSI 65 nm pMOS |V_G- V_T|= 1V

I

D ( µ

A/

µ

m

)

V

_D

(V)

0.4 0.0 -0.4 -0.8 -1.2 0 50 control device Ni FUSI + second CESL Ni FUSI 65 nm pMOS Gm ( S/ µ m ) V_G-V_T (Volts)

Fig. 6. ID–VD and Gm vs VGVT (inset) characteristics of 65 nm

pMOSFETs with various gate electrodes.

0.5

0.0 -0.5

-1.0

10

-12

10

-10

10

-8

10

-6

10

-4 65 nm pMOS V D = -0.05V control device SS: 97 Ni FUSI + second CESL SS: 94 Ni FUSI SS: 86

I

D

(

µ

A/

µ

m)

V

G

(V)

0.0 -0.4 -0.8 -1.2 10-13 10-11 10-9 10-7 10-5 V G (V) IG (A) _{Ni FUSI} + second CESL Ni FUSI control device 65 nm pMOS VD= 0.05 V VS= 0 V

Fig. 7. ID–VG, subthreshold swing, and IG–VG (inset) characteristics of

65 nm pMOSFETs with various gate electrodes.

(4)

VGcurves of the pMOSFETs. All the Ni FUSI devices have

higher gate leakages than the control device with reasons similar to that of the nMOSFETs. The LF noise character-istics of the pMOSFETs were shown in Fig. 8. It is apparent that the Ni FUSI gate devices possess a low Svg.

Never-theless, owing to their smaller leakage currents, the noise diﬀerences in the pMOSFETs are smaller than in the nMOSFETs. Moreover, based on the SS, gate leakages (inset in Fig. 7), and the oﬀ-state leakages (Ioff, inset in Fig. 8), we

ﬁnd that the eﬀect factors of the LF noise in the pMOSFETs are similar to those in the nMOSFETs as mentioned above. On the other hand, the same reasons for the nMOSFETs lead the pMOSFETs with the second CESL to have a higher Svgthan those without the second CESL. Figure 9 shows the

C–V curves of three diﬀerent pMOSFETs. The reduced polygate depletions are 2 and 1.6 A˚ for the Ni FUSI devices with and without the second CESL, respectively. Compared with the nMOSFETs, the improvements are small for the polygate predoped. Moreover, the increased Cox values in

the inversion regions of the devices with and without the second CESL are about 12 and 10%, respectively, which are larger than those of the nMOSFETs are. On the other hand,

the Ni FUSI pMOSFETs have a negative C–V curve shift due to the increase in ﬂatband voltage (jVFBj).

4. Conclusions

In this study, the driving capacity, leakages, low-frequen-cy noise (LF noise), and C–V characteristics have been investigated on 65 nm Ni FUSI CMOSFETs with and without the second high-tensile-stressed CESL. From the results of our investigations, we found that even the second CESL also induces defects, degrading junction leakages to result in a high LF noise and a small accumulation capacitance. The effect of the second CESL for the further improvement in carrier mobility on the Ni FUSI pMOSFETs is significant; thus, the second CESL makes the Ni FUSI nMOSFETs further enhance the carrier mobility. However, for pMOSFETs, the second CESL is profitless in the improvement of performance owing to an inappropriate stress (it should be compressive not tensile). The inappro-priate tensile stress causes a larger degradation than the improvements in devices driving capability, leakages, and LF noise. Furthermore, we also found that the FUSI process does not cause apparent gate oxide damage; thus, no apparent increase in the gate leakages of both Ni-FUSI n-and pMOSFETs.

Acknowledgement

The work is supported by the UMC Device Engineering Division and National Science Council of Taiwan under contract NSC 95-2221-E-006-419 and 95-2221-E-390-028.

1) The International Technology Roadmap for Semiconductors, 2003. 2) N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman: IEEE Trans.

Electron Devices 47 (2000) 440.

3) J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong: IEEE Electron Device Lett. 24 (2003) 631.

4) P. Xuan and J. Bokor: IEEE Electron Device Lett. 24 (2003) 634. 5) J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott,

Cyril. Cabral. Jr, M. Ieong, and W. Haensch: IEDM Tech. Dig., 2003, p. 315.

6) C. H. Huang, D. S. Yu, A. Chin, C. H. Wu, W. J. Chen, C. Zhu, M. F. Li, B. J. Cho, and D.-L. Kwong: IEDM Tech. Dig., 2003, p. 319. 7) S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi,

R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto: IEDM Tech. Dig., 2004, p. 213. 8) S. E. Thompson: IEEE Trans. Electron Devices 51 (2004) 1790. 9) Y. C. Liu: IEDM Tech. Dig., 2005, p. 836.

10) A. Chin, W. J. Chen, T. Chang, R. H. Kao, B. C. Lin, C. Tsai, and J. C.-M. Huang: IEEE Electron Device Lett. 18 (1997) 417. 11) K. Hosaka, T. Kurahashi, K. Kawamura, T. Aoyama, Y. Mishima, K.

Suzuki, and S. Sato: Symp. VLSI Technology Dig., 2005, p. 66. 12) C. M. Lai, Y. K. Fang, and W. K. Yeh:Jpn. J. Appl. Phys. 45 (2006)

3053.

13) C. T. Sah and F. H. Hielscher:Phys. Rev. Lett. 17 (1966) 956. 14) M. J. Kirton and M. J. Uren: Adv. Phys. 38 (1989) 367.

15) D. M. Fleetwood and J. H. Scoﬁeld:Phys. Rev. Lett. 64 (1990) 579. 16) K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng: IEEE Trans. Electron

Devices 37 (1990) 654.

17) T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoﬀmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr: IEDM Tech. Dig., 2003, p. 978. 18) S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoﬀman, J. Klaus, M. Zhiyong, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy: IEEE Electron Device Lett. 25 (2004) 191.

10

100 1k

10k

10

-15

10

-14

10

-13

10

-12

10

-11 Ni FUSI control device Ni FUSI + second CESL

Frequency (Hz)

S

VG (

V

2

/ Hz

) 65 nm pMOS |V_G-V_T| =0.3 V 0.0 -0.4 -0.8 10-8 10-6 10-4 65 nm pMOS V G= VB=VS=0 V control device Ni FUSI + second CESL Ni FUSI V D (V) ID (µ A/ µ m )

Fig. 8. Low frequency noise and Ioffcharacteristics of 65 nm pMOSFETs