IFTU-81
A 1
lOMHz
84dB CMOS.Programmable Gain
Amplifier
with
RSSI
Chun-Pang Wu and Hen-Wai Tsao
Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National
Taiwan University, Taipei, Taiwan, 10617,
ROC
,
:
[email protected]
Abstract
-
This paper describes a CMOS programmable gain amplifier that maintains a 3dB bandwidth greater than llOMHz and can provide 84dB gain control range in 1dB steps. The PGA can also be operated in a low power mode with 3dB bandwidth greater than 71MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a 20.7dB logarithmic accuracy over 80dB dynamic range. It achieves a sensitivity'of -83dBm. The amplifier consumes 13mA from a single 3V supply in high power mode. The chip area including pads occupies 1 . 5 ~1.5mm2.
I. INIRODUCT~ON
Although recently zero-IF and low-IF architecture have been widely used recently in wireless telephone handsets to reduce the extemal component count, super-heterodyne architecture as shown in Fig.1 continues to he widely used due to its overall better performance. Signal processing such as amplifying or filtering are usually realized at the IF frequency in a super-heterodyne system. The circuits will consume less power if the signal processing is performed at IF frequency rather than at RF frequency.
Also, offset and flicker noise can be ignored if most of the system gain is realized at IF frequency rather than at baseband.
In wireless communication systems, the received signal exhibits a wide dynamic range after passing through unpredictable propagation channels,
so
a PGA is typically employed in the signal chain to handle these unpredictable received signals. In the design of a PGA with non-uniformgain
distribution such as proposedin
reference[I],
it is difficult to accompany the circuit with a RSSI function, so the measurement of the received signal strength needs to be performed, for example, at baseband. The tracking speed for the automatic gain control loop will he lowered.In the design of a PGA with uniform gain distribution as proposed in reference [2], the RSSI circuit can he easily added to the PGA circuit, hut unfortunately, the RSSI characteristics will change when the gain of the PGA is
adjusted, so a mapping from the RSSI output to true signal level is required.
The voltage gain of the proposed PGA in this paper can he programmed from 0dB to 84dB in 1dB steps, which corresponds to a programmable range from -6dB to 78dB in power gain with an input impedance 50R and
an
Fig.1 Block diagram of a typical super-heterodyne system output impedance 200R. With this PGA we also design a received signal strength indicator (RSSI) circuit in order to monitor the signal strength at IF frequency and use it as
a
reference of how to adjust the gain of the system. The RSSI curve will not change when we v;uy the gain of thePGA. The PGA circuit we propose can be used in either
the received path or the transmit path as shown in Fig.1.
In section 2 we will describe the circuit architecture of the proposed PGA with RSSI. The circuit design of the fixed gain amplifier and the fme gain step amplifier is expounded in section 3 and 4, respectively. Section 5 describes the RSSI circuit and some other considerations. The experimental results are shown in section 6. Finally, a simple conclusion is drawn in section 7.
1
-.
m
-.
I
E. T H E CIRCYIT ARCHITECTLRE ~
In our design as shown in Fig.2, we also accompany the
PGA with a received signal strength indicator circuit, and
furthermore, the RSSI curve will not change when we adjust the gain of the whole PGA. The PGA circuit is composed of six fmed gain stages, and each gain stage has 12dB gain. With these six fmed gain stager, we can adjust our gain in 12dB gain step over 72dB range by selecting the input of the PGA or one of the outputs of the six fmed gain stages as shown in Fig.2. We can further increase the resolution of the PGA by passing the selected output signal through a PGA with fine 'gain steps, for instance IdB in our design, to cover I2dB range. So the overall gain of the PGA is programmable from OdB to 84dB in
1dB steps.
A125
Fig2 Block diagram of the proposed PGA
lII.
FIXED GAIN AMPLETER DESIGNDue to process variations, the gain of the fixed gain amplifiers may vary from 6dB to 15dB, and this will significantly affect the accuracy of the gain setting of the PGA.
To
accommodate the gain variation caused by such process variations, we design a gain control bias circuit to generate the bias current for our fixed gain amplifiers, as' shown in Fig.3. The circuit compares the gain of the fixed
gain amplifier with the gain we set, which is equal to (R1+2Rz)/RI, and generates the correct bias current to bias the fixed gain amplifiers.
For the fvred gain amplifier we designed, power can he saved by lowering the bandwidth of the amplifier circuit as shown in Fig.3. The load of the fixed gain amplifiers is composed of a resistor in parallel with a voltage controlled resistor (VCR). The gain of the Fixed gain amplifier can be obtained as,
t Av
z
g,,-, 2Zm R&...
when RRLc (14
w h e n R m -=&
...
(1b) CR...
when Rm
>uRycR
(IC)where
K=(1/2)finCox(W/L)
andh
is the channel length modulation coefficient, In order to fmd out the maximumFig.3 Fixed gain stage and gain control bias circuit
gain of the fixed gain amplifier, we can take the differentiation of (Ib) with respect to Iail and it will be shown that the maximum gain occurs when the resistance of the VCR is equal to the resistance of the resistor. This means the maximum gain is achieved when the tail current is 2/( h xR,). When the resistance R, of the resistor is much lower than the resistance Rvcn of the VCR, the load resistance is dominated by Rm. So the gain of the fvred gain amplifiers can be enlarged by increasing the tail current as shown in (la). And the 3dB bandwidth of the amplifier is determined by the pole 1/(2 ii x R R E s x C ~ ~ ~ ~ , ) formed by the load resistance, i.e. Rm, and the capacitance C,,,, at the output node. When Rvcn dominates the resistance of load, i.e. RvcR is much smaller than R w , the gain of the fixed gain amplifier can be enlarged by decreasing the tail current of the amplifier as shown in (IC). And under the circumstance that RvcR is much smaller than RRES, the 3dB bandwidth of the fvred gain amplifier is approximately 1/(2 ii x Rvm x J.,C., Since Rvcn is smaller than RES which is a fixed value, we can expect that the 3dB bandwidth is larger when the Rvm dominates the load resistance and meanwhile the power consumption is'also higher. As long as the IF frequency does not exceed the bandwidth of the PGA in low power mode, power can be Saved by operating the circuit in the low power mode.
IV.
FINE
GAIN STEP AMPLIFIER DESIGN In order to achieve fme gain step adjustment, one fme gain step PGA with 1dB steps over 12dB range is arranged at the end of the signal chain. The circuit of this PGA is shown in Fig.4. The gain step is determined by the ratio of the gain control transistor M3 to M4 and M5 to M6. The gain of the PGA can be expressed as the following equation:T T
:
memaicomponems;
I 1 8-_______._I!
-2 I M B PGA I _ _ * h p- - - -
.
-
- - -
- .-
- - -
-
-
Fig.4 Fine gain step PGA amplifierThe ratio of K3 to
&
chosen for the voltage gain setting of the fine gain amplifier from OdB to 6dB with respect to the minimum gain is listed in Table I. For example, the gain set by choosing K3:&=18:5 is 1dB larger than the gain set by choosing K3:&=18:6. For voltage gain from 7dB to 12dB, we simply apply another 6dB PGA inTABLE I
SUMMARY OF VOLTAGE GAIN SETTINGS
186 182
1 8 1 1 8 4
3dB
1 8 3parallel with the former 6dB PGA. These are shown in Fig.4. The change of the total width of gain control transistors M3 and M4 (M5 and M6) should be as small as possible so that the variation of the voltage at point X (point Y ) won't significantly influence the g, of the input transistors M1 and
M2.
If the variation of the voltage at point X (point Y ) is too large, the gain step error will also increase due to. the significant influence on the g, of the input transistors MI and M2. The differential output points are connected to the power supply through two extemal inductors that can improve the linearity of the PGA. These two inductors together with the capacitor between the differential output nodes also provide bandpass filtering and impedance matching functions.v . RSSI CIRCUIT AND OTHER DESIGN CONSIDERATIONS
~ 2 0 , , ,
.
,.
,.
,.
-0.4Gain-Comral Cwe
20 40 60 10 im
Fig.5 IF amplifier power gain and gain error
The RSSI circuit is the same as'tbat proposed in reference
[3],
and it can function well in spite of the process variations. The coarse gain step adjust circuit must be designed carefully to eliminate the reverse signal coupling from the output of the last stage of the fmed gain amplifier chain, otherwise the circuit may oscillate. Double guard rings are used to prevent suhswate coupling. The first fixed gain stage must also be carefully designed because the offset cancellation circuit will deduce the gain of the fxst stage. We have designed the first fmed gain stage with a little higher gain to compensate theloss.
VI. EXPERIMENTAL RESULTS
The IF amplifier we proposed has been fabricated in a
0.35
1 tu 1P4M CMOS process. The capacitors used for frequency compensation in our operational amplifier for the bias circuit are realized using MOS capacitors. The gain programming logic circuit and RSSI circuit are also integrated with this IF amplifier. The test chip is directly bonded to a PCB surrounded with the required extemal components. The programmable power gain range is from -7.78dB to 79.79dB in normal operation (at 11OMHz) mode and -7.79dB to 80.03dB ig low power operation (at71MHz) mode as shown in Fig.5. It can be found that the peaks of gain step error occur every 12 dB because of the 12dB gain of the fixed gain amplifiers.'The gain step error is kept within M0.4dB when the test chip is operated in either mode. The input impedance is 50R and the output impedance is 200R. In Fig.6 it is shown that the measured RSSI accuracy is M.7dB with the input signal varied from -83dBm to -3dBm. The accuracy of the multimeter used for measuring the RSSI circuit is IOmV, which corresponds to about 0.6dB. The measured oCP is
Fig.6 RSSI Output and RSSI Error
-10s .loo 63 .$n 65- .M -7s .m
iApanSconii L ~ M I ( ~ E v )
Fig.? IF Amplifier OCP and IP3
-4dBV and the oIP3 is 10.6dBV which are shown in Fig.7. The IC consumes 13mA from 3V when operated in
normal mode and 5mA from 3V when operated in IOW
power mode. The chip micrograph is shown in Fig.8. The chip area including pads occupies 1.5 A.5mm2. Table 11 summarizes the key measured performances.
VI.
CONCLUSIONS
In this paper we realized a IlOMHz 84dB programmable gain amplifier usingstandard CMOS technology. Despite of the process variations, the performance can be maintained excellent by using the gain controlled bias circuit. The programmable gain amplifier can be operated when the minimal input signal is -83dBm. High gain step accuracy (9.4dB) with IdB resolution is be saved under low power mode when the frequency of the input signal is
lower than 74MHz.
Fig.8 Chip micrograph
TABLE I1
SUMMARY OF CHIP PERFORMANCE
0.03dEXlow oowerl
7.79dB(low power)
ain step error "put impedance 0fl 10.4 to 0.3dB _____ utput impedance 0062 "OdYVoltaee b.Of13V
1
13InA(high power) onsumption ACKNO~~EDGEMENTThe authors would like to thank National Chip Implementation Center and MediaTek Incorporation, Taiwan, for chip implementation and support of this work,
REFERENCES
[l] Francesco Piazza. et al., "A 2mN3V 71MHz IF Amplifier
in 0.4 p m CMOS Programmable over 80dB Range." ISSCC Digest of Technical Papers, pp.78-79, Feb., 1997. (21 "RF2903 Integrated Spread Spectrum Receiver," Data
Sheet, RF Micro Device, 1999.
[3] Katsuji Kimura. "A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs." IEEE J. Solid-State Circuits. vol. 28. pp. 78-83, Jan., 1993.
