Time-based frequency band selection
method for phase-locked loops
T.-H. Lin and Y.-J. Lai
High-performance phase-locked loops (PLLs) often require voltage-controlled oscillators (VCOs) employing both discrete and continuous tuning mechanisms to satisfy a wide frequency range and a low VCO tuning gain simultaneously. An auxiliary circuit is required to facilitate the selection among a group of discrete bands. An agile technique to search for an optimum VCO frequency band is proposed. The search is based on measuring the period difference between a reference and the VCO-divided signals. The VCO band selection circuit is implemented with a 10 GHz PLL in a 0.18 mm CMOS process and consumes only an extra 3 mA. The band selection time is less than 4 ms.
Introduction: A PLL typically requires a wide tuning range to cover the desired frequency band and tolerate the process-voltage-temperature (PVT) variations. However, as supply voltage decreases and PLL
operating frequency increases, VCO tuning gain (KVCO, MHz=V)
increases, thus degrading PLL noise and spur performance. A way to
keep KVCOlow is to adopt both discrete and continuous tuning in the
VCO, i.e. use multiple overlapped discrete frequency bands to cover
the desired frequency range[1]. This topology requires a VCO band
selection circuit to find the optimum band that covers the desired frequencies. Time spent on the band search adds to PLL settling time, resulting in an increased overhead in communication systems. To address this issue, we propose a fast VCO band selection method.
FREF a b PFD/CP LF Vdd/2 VCO logic counters FVCO/N ∏N FREF PFD/CP LF Vctrl VCO ∏N logic Vref1 Vref2
Fig. 1 Conventional VCO band selection techniques a Open-loop approach
b Closed-loop approach
Conventional VCO band selection techniques: Existing VCO band selection techniques fall into two categories: open-loop and
closed-loop methods. Fig. 1a shows a typical open-loop technique [2].
During operation, the PLL is opened at the loop filter (LF) and Vctrl
is connected to a reference voltage (usually Vdd=2). The band select
circuit consists of counters that count the FREFand FVCO=N signal
cycles until one of the counters overflows. This indicates which signal is faster=slower, and proper band adjustment can be made. This process repeats until the search criteria are met. To avoid possible errors due to initial phase uncertainties between two signals, the counts must be long enough. Therefore, the band selection time cannot be made small. In the closed-loop approach shown in Fig. 1b, the PLL tries to lock the VCO to a desired frequency.
When the loop is settled, Vctrl is measured against the predefined
voltage range (between Vref1 and Vref2). If Vctrlis outside this range,
another VCO frequency band will be selected (by proper capacitor
array setting). Vctrlis then checked again. Such operation repeats until
Vctrlfinally falls into this desired range[1]. Since the PLL loop must
settle before valid voltage comparison can be made, the band selection process can be slow.
Concept of proposed VCO band selection method: The proposed scheme is also an opened-loop method. Rather than comparing frequencies by counters, this approach compares two signals through measuring their period difference. This is accomplished by observing
the relative phase positions of the two rising edges and falling edges.
The operation principle is shown inFig. 2. The signals from divider and
reference paths (FVCO=N, FREF) are first divided by 2, such that
the divider output pulse widths equal the signal periods. Initially, the
voltage across the capacitor C1is reset to Vref. Next, consider the two
cases illustrated in the bottom ofFig. 2. When FVCO=2N > FREF=2, the
phase difference of the two rising edges is smaller than that of the two
falling edges. This results in a net effect of charging the capacitor C1
and raises the charge pump (CP) output voltage (VC). The comparator
output will then be an indicator of which signal is faster=slower and this information is used to adjust the VCO frequency band.
FVCO/N FREF ∏2 ∏2 logic control charge pump up down Vref VC C1 + -FVCO/2N> REF/2F FREF/2 FVCO/2N down up VC Vref FREF/2 FVCO/2N down up VC Vref FVCO/2 < REF/2N F
Fig. 2 Conceptual illustration of proposed VCO band selection method
FVCO/N ∏N LF CP PFD FREF band select circuit Vdd/2 VCO Vctrl 3 FREF (40 MHz) ∏2 ∏2 ∏2 FVCO/N ∏2 (~20 MHz)
generate eight phases
enable controllogic phase selector logic counter3 to VCO frequency bands charge pump 1 charge pump 2 Vref VC compar ator
Fig. 3 Block diagram of 10 GHz PLL with proposed VCO band selection circuit
Architecture of VCO band selection: Fig. 3shows the proposed band
selection architecture is shown in Fig. 3. This method requires a
proper phase relationship between FVCO=2N and FREF=2 (where
FVCO=2N leads FREF=2). A phase selector circuit is developed to
produce a reference signal with a proper phase. To increase the phase
resolution, eight phases are generated from a 40 MHz FREFsignal.
The reference signal out of the phase selector has a phase lagging that
of FVCO=2N by 45–90. A proper phase relationship increases the
comparison accuracy, and prevents the following CPs from operating near the dead-zone region.
1.1 900 m 700 m V 500 m Vref VC
charge pump waveforms
8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 V /digi_out /1334/vo+ 2.0 1.0 0 -1.0 V
control code for VCO capacitor array
operation started
operation completed
VCO calibration-ready indicator
0.8 sm 1.6 sm 2.4 sm 3.2 sm
Fig. 4 Operation of VCO band selection
The method of generating Vref can greatly affect the comparison accuracy. Owing to the nature of the switching operation of the CP
(alternating the up=down currents), the voltage VC, has a non-ideal
switching component superimposed on top of the desired waveforms. To cancel out this effect, the reference voltage generation also incor-porates a CP. This essentially forms a pseudo-differential topology, and other non-idealities, such as power line noise coupling or substrate noise pickup, can be largely cancelled as well.
ref 0 dBm samp log 10 dB/ Atten 10 dB mkr1 10.0000 GHz 13.7 dBm -VAvg 100 W1 S2 S3 FC AA centre 10 GHz Res BW 300 KHz VBW 300 KHz span 50 MHz sweep 4 ms (401 pts) a marker 10.000000000 GHz 13.7 dBm
-band selection loop filter VCO
b PFD/CP divider
Fig. 5 PLL output spectrum at 10 GHz and chip photo a PLL output spectrum
b Chip photo
In principle, each comparison can be completed in one FVCO=2N
period, thus the band selection process is fast. In the actual implemen-tation, each comparison cycle is repeated twice to enhance the circuit accuracy and robustness.
PLL implementations and results: The 10 GHz integer-N PLL block
diagram is also shown inFig. 3. When powering on, the PLL first
enters the VCO band selection mode, during which, the loop is
opened, and Vctrlis set to Vdd=2. Once the operation is completed,
the PLL then closes the loop and locks to the desired frequency. The
band selection operation is illustrated inFig. 4. The initial frequency
band setting is 111 (decimal code 7, corresponds to the lowest VCO
frequency band). As seen from the Figure, when VCis lower than Vref
(i.e. FVCO=N is slower than FREF), the band selection circuit acts to
decrease the code by 1, thus raising the VCO frequency. This process
repeats until FVCO=N is just faster than FREF. At this point, a
calibration ready signal is asserted to enable the PLL closed-loop locking. The worst case band selection operation (stepping from 111 to 000 sequentially) can still be completed in less than 4 ms. The band selection time can be further reduced with a binary search scheme.
This 10 GHz PLL with the proposed band selection circuit is fabricated in the TSMC 0.18 mm CMOS process. All circuit blocks are integrated on chip. In this work, VCO tuning range is divided into eight bands. The chip is measured with a 1.8 V supply and consumes 44 mW. The band select circuit dissipates only an extra 3 mA. The measured frequency range is 8.67–10.12 GHz, corresponding to 14.5%.
The PLL output spectrum at 10 GHz is shown inFig. 5a. The reference
spurs are lower than 48 dBc. The VCO phase noise at 1 MHz away
from the 10 GHz carrier is 102 dBc=Hz. The chip occupies an area
1400 by 964 mm. The die photo is shown inFig. 5b.
Conclusions: An agile VCO frequency band selection technique and its application to a 10 GHz CMOS PLL have been reported. The proposed method is based on measuring the relative signal periods. It completes the band selection much faster than other methods where either long count of signal cycles or waiting for PLL settling is required. This agile time-based technique enables fast-settling PLLs. Acknowledgments: The authors thank the Chip Implementation Center (CIC), Taiwan, for chip fabrication. This work is supported by the National Science Council, Taiwan, ROC, contract number: NSC93-2215-E-002-031.
#IEE 2005 19 July 2005
Electronics Letters online no: 20052451 doi: 10.1049/el:20052451
T.-H. Lin and Y.-J. Lai (Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan, Republic of China) E-mail: thlin@cc.ee.ntu.edu.tw
References
1 Lin, T.-H., and Kaiser, W.J.: ‘A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop’, IEEE J. Solid-State Circuits, 2001, 36, pp. 424–431
2 Wilson, W.B., et al.: ‘A CMOS self-calibrating frequency synthesizer’, IEEE J. Solid-State Circuits, 2000, 35, pp. 1437–1444
