A Statistical Model for the Headed and Tail
Distributions of Random Telegraph Signal
Magnitudes in Nanoscale MOSFETs
Ming-Jer Chen, Senior Member, IEEE, Kong-Chiang Tu, Huan-Hsiung Wang,
Chuan-Li Chen, Shiou-Yi Lai, and You-Sheng Liu
Abstract— Trapping-detrapping of a single electron via an
indi-vidual trap in metal–oxide–semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitudeId/Idin the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: (Id/Id) = (Iloc/Id)2, where Iloc is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a 35× 35-nm2channel to provideId/Id
for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the Iloc/Idformula. Extension to threshold voltage shift counterparts, from sub-threshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.
Index Terms— Fluctuations, metal–oxide–semiconductor field-effect transistors (MOSFETs), nano, noise, percolation, random telegraph signals (RTSs), technology computer-aided design (TCAD), trap.
I. INTRODUCTION
I
N 1984, Ralls et al. [1] of Bell Laboratories first observed random telegraph signals (RTSs) in metal–oxide– semiconductor field-effect transistors (MOSFETs) and had attributed such phenomena to the alternate capture and emis-sion of a single electron at a certain individual gate dielec-tric trap. Since then, RTS of MOSFETs has attracted soManuscript received December 18, 2013; accepted May 2, 2014. Date of publication May 29, 2014; date of current version June 17, 2014. This work was supported by the National Science Council of Taiwan under Contract NSC 100-2221-E-009-017-MY3. The review of this paper was arranged by Editor Z. Celik-Butler.
M.-J. Chen, K.-C. Tu, H.-H. Wang, C.-L. Chen, and Y.-S. Liu are with the Department of Electronics Engineering, Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: chenmj@faculty.nctu.edu.tw; kctu.ee96g@g2.nctu.edu.tw; treebeard.ee96@ g2.nctu.edu.tw; recreation2266.ep97@g2.nctu.edu.tw; idoflymark@gmail. com).
S.-Y. Lai is with the Ministry of the Interior, Taipei 100, Taiwan (e-mail: lineage78225@hotmail.com).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2323259
Fig. 1. (a) Schematics of a MOSFET structure showing the electron trapping-detrapping process via a trap in gate dielectric and corresponding two-level RTS in the source and drain current. (b) 3-D TCAD created statistical distributions (from 200 samples) [21] of RTS relative magnitude in the subthreshold current at low drain voltage: a headed distribution (solid line) in a percolation-free channel and a tail distribution (dotted line) in a percolative channel. The two arrows indicate the separation of the headed distribution into the tail one via the strategically located trap and the remaining via the nonstrategically located trap [18]. Note that there is an intersection between two curves.
many researchers [2]–[22] for its unique capability, relative to expensive nanometer-precision probe equipment, to examine atomic-sized traps, blocked regions, and even the underlying channel. More recently, the study in the field has substantially turned to RTS relative magnitude or equivalently the extra threshold voltage shift [23]–[26]. The reason is that state-of-the-art MOSFETs have been aggressively scaled down to the extent the RTS critically impacts, primarily through its relative magnitude as shown in Fig. 1 for a two-level RTS in the source/drain current under fixed drain and gate voltages.
There has been a simplest but widely quoted model for the source/drain current RTS magnitude [2], [17]
Id Id =
L2t
W L (1)
where Lt is the effective size of the blocked region around
the trapped electron, and W and L are the channel width and length, respectively. Relative magnitude Id/Id corresponds
to extra threshold voltage shift under constant source/drain current. Such relative current magnitudes or threshold volt-age shifts have been experimentally demonstrated to have large values or significant variations, particularly for static RAM [27] and flash memory [28]. Thus, the ability to quantify
Id/Id through (1) is essential and crucial. In doing so,
0018-9383 © 2014 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted,
or 3-D analytical models [23], each with its own percolation paths. Specifically, simulations by Asenov et al. [21], on an individual 50× 50 nm2MOSFET in the subthreshold region at low drain voltage, pointed to the existence of the two different distributions of Id/Id, as shown in Fig. 1(b): a headed and
a tail distribution. The former is due to the uncertainty in the trap position, in case of no percolation, whereas the presence of the percolation gives rise to the latter having an extended range to higher Id/Id. As illustrated in the figure (see more
detailed explanations later), once the strategically located traps are involved [18], part of the headed distribution will fall down and become the tail one.
The second way goes to (1) again, especially its statistical version. According to [18], the following relationship can be derived from (1): Id Id = Iloc Id 2 (2) where Iloc represents the local current around the trap. The
ratio of the local current to the total current, Iloc/Id, was
experimentally found to follow a normal distribution, denoted as n0(Iloc/Id) [18]. Consequently, the distribution function
of Id/Id, h(Id/Id), can be obtained by performing the
function transformation on (2) [18] h I d Id = n0 Iloc Id I d Id −1/2 2. (3) The application of (3) had successfully reproduced the exper-imental tail distribution of Id/Id from an ensemble of
187 samples of 500 × 500 nm2 MOSFETs, all operated in the subthreshold region [18]. Corresponding mean mloc and
standard deviation σloc of the normal variable Iloc/Id reflects
the underlying individual percolation path due to the use of the same manufacturing process [18]. In principle, different sets of
mlocandσloccorrespond to different manufacturing processes
and hence different percolation paths, and vice versa (the validity of this statement will be examined in the subsequent sections). However, several issues concerning the use of (3) arise, due to the uncertainties in mloc and σloc. First, it is
unclear whether mloc orσloc is unlimited. Second, the values
of mlocandσlocare unique or not, if they are extracted from a
given percolative channel. Third, mlocandσlocshould change
or not, if the operating conditions change. Finally, guidelines to adequately determine mloc and σloc were lacking to date.
Only with these issues clarified and resolved can the practical application of (3) be possible.
At this point, one should keep in mind that there exist fun-damental limitations associated with the statistical experiment
is likely to limit the visible range of the created distribution. These drawbacks may all be overcome if one turns to the use of (3).
In this paper, we show how to make (3) practically useful. First, we focus on a 35 × 35-nm2 MOSFET and limit the operating conditions to the subthreshold regime at low drain voltage (0.05 V). To achieve the goal efficiently, we make use of a commercially available 3-D TCAD simulation tool and execute it only for several trap positions in case of no percolation. This leads to the statistical version of (1) in closed form, which can reproduce headed distributions well. Straightforwardly, it enables the establishment of the key criteria and hence the guidelines to ensure the adequate use of (3) in percolation conditions. Resulting tail distributions are validated. Aforementioned issues associated with mlocandσloc
are also made clear. Extension to RTS-induced threshold volt-age shift, in a wide range of gate voltvolt-ages from subthreshold to inversion, is done as well.
II. PERCOLATIONFREECHANNEL:
MODEL ANDVALIDATION
3-D TCAD Sentaurus [30], in its default conditions (i.e., the conventional scattering mechanisms due to ionized impurity atoms, phonons, and surface roughness; and the density gra-dient model for the quantum confinement), was employed. Simulation structure is a bulk n-channel W /L = 35/35-nm MOSFET structure (with no shallow trench isolation (STI); the effect of including the STI as in [31] and [32] will be addressed later) with the equivalent gate oxide thickness of 2 nm and p-type substrate doping concentration of 2× 1018 cm−3 (continuous doping, with no halo implants). Simulated subthreshold I –V characteristic is shown in Fig. 2(a). Corre-sponding threshold voltage and subthreshold swing (SS) are labeled. A negatively charged trap was placed at the SiO2/Si
interface to simulate the altered drain current. TCAD was carried out, with different positions of such trap along the transport direction but fixed at the midchannel (those fixed at the edge part will be discussed later) in the width direction. SimulatedId/Id at Vg= 0 is shown in Fig. 2(b) versus the
distance d of the trap from the midchannel in the transport direction. Corresponding Lt as extracted by (1) is added to the
figure. Evidently, the maximumId/Id and Lt correspond to
the midchannel trap and will decrease with increasing distance from midchannel; and owing to the symmetry of the structure in the channel length direction, which is valid only for small enough drain voltage, it can be inferred that the same distance will have the same Id/Id, regardless of the trap located
Fig. 2. (a) Simulated subthreshold I –V characteristics with (black line) and without (red line) percolation. Corresponding SS and threshold voltage are labeled. (b) SimulatedId/Idand corresponding Lt(empty symbols for traps
between midchannel and source; solid symbols for traps between midchannel and drain) versus the distance d from the midchannel. Fitting line via (4) yields Lt 0= 19.7 nm, a = 0.10, and b = 4.11 nm.
near source or drain. Furthermore, we suggest that Id/Id
is appropriately a weak function of the trap position in the width direction (the reasons will be given later, along with the STI issue). Similar statements were also reported in case of
W /L= 50/50 nm (with no STI) [21].
There are many empirical formulas one can use to fit Lt
in Fig. 2(b). Here, we adopted the following one, without any particular reason:
Lt = Lt 0
1+ a(exp(d/b) − 1). (4)
Data fitting yields Lt 0= 19.7 nm, a = 0.10, and b = 4.11 nm.
The fitting quality is good, meaning that only a few trap posi-tions, but with enough distance between posiposi-tions, are needed in the simulation. This greatly reduces the computational load in the 3-D TCAD simulation. Note that Lt 0 stands for Lt in
case of midchannel trap (d = 0). Then, it is a straightforward task to derive a closed-form statistical model forId/Id. The
derivation process is shown in Fig. 3. First, we can reasonably assume that: 1) the probability of finding a region between midchannel and source is 1/2, equal to that of the remaining between midchannel and drain and 2) the probability of finding
Fig. 3. Derivation process for the statistical model of the RTS source/drain current magnitude in the percolation free case.
Fig. 4. Calculated (green solid line) and simulated (yellow line with triangle) Id/Id headed distributions in this paper for the percolation free
case. Together plotted are simulated tail distributions due to fixed charges in this paper (Vd = 0.05 V) and due to random discrete dopants from the
citation (Vd = 0.01 V) [25]. Corresponding sample size (i.e., number of the
trap positions) is given. In this paper, Vg= 0 and Vd= 0.05 V.
a trap at a certain d is constant across the channel. Thus, the distribution function of the trap distance d (0 ≤ d ≤ L/2) in each of these two regions can read as
f(d) = 1
L. (5)
Next, by substituting (4) into (1) and applying the function transformation to (5), the distribution function ofId/Id can
result g I d Id = 2bf (d) 1+1− a a exp −d b I d Id . (6)
The upper and lower limits of Id/Id correspond to d = 0
and L/2, respectively, both of which can be readily calculated. The area under the distribution curve created by (6) between lower and upper limits is equal to unity.
Calculated distribution function of Id/Id appears to pile
up near the upper limit of Id/Id, typical of the headed
distribution, as shown in Fig. 4. To testify to the validity of the model and its assumptions, we add to the figure a TCAD created distribution curve in this paper, with a large sample size of 693 (i.e., 693 TCAD simulation structures with only one trap randomly positioned across the whole channel). Fairly good agreements between the two are evident, achieved
near source and drain, away from the midchannel, where the electron concentration is much larger than that around midchannel. This means that the strong inversion dominates in these local regions. In other words, the subthreshold region of operation strictly applies only to around the midchannel. Such localized strong inversion near source and drain junctions holds even in the percolation case, as earlier mentioned in [21]. In a sense, the percolation effect in such local strong-inversion regions should be greatly reduced, due to enhanced electron screening. Two extra sources of corroborative evidence exist. First, in [33], subthreshold current mismatch significantly decreases as the electron density increases via a substrate forward bias. Second, 3-D TCAD simulation results [24] sug-gested that the closer to source or drain the trap is situated, the lower the corresponding RTS-induced threshold voltage shift. Thus, the first key criterion emerges: theId/Iddistribution
curve near the lower limit does not change too much between the two cases of with and without percolation. In other words, the lowerId/Iddistribution in the presence of the percolation
is considerably close to that of the headed one. This also means that the lower limit of Iloc/Id can reasonably be set by the
lower limit of Id/Id with d = L/2. In a sense, the normal
distribution function of Iloc/Id in (3) must be modified as the
limiting one n Iloc Id = n0 Iloc Id Iloc/Id max Iloc/Id min n0 Iloc Id dIloc Id (7)
where n0(Iloc/Id) is the standard (unlimited) normal
distribu-tion funcdistribu-tion with the mean mloc and standard deviationσloc,
(Iloc/Id)minis the squared root of the lower limit ofId/Idin
the headed distribution, and (Iloc/Id)max is set at 1 to reflect
the worst case conditions (i.e., RTS high level being Id and
low level zero).
The second is related to the remaining region around the midchannel. In this region, there are, to a first-order approximation, two types of individual traps responsible for RTS: one of the strategically located trap and one of the nonstrategic trap [18]. The former is likely to produce a value of Id/Id larger than that of the upper limit of the
headed distribution and hence constitute the tail distribution at higher Id/Id. As for the latter, its role is simply to raise
the resulting distribution curve near lower limit to above that of no percolation. Thus, part of the headed distribution near the upper limit is repopulated and separated into two different components in percolation case: 1) higher Id/Id part and
Fig. 5. (a) Simulated conduction-band energy on 35× 35-nm2 channel in the presence of fixed charges (black squares) and (b) correspondingId/Id
distributions (created from 693 trap positions). The number of fixed charges is 16 and hence the average density is 1.3× 1012 cm−2. Vg = 0 and
Vd= 0.05 V.
2) lower Id/Id part [Fig. 1(b)]. Because the area under
the distribution curve is unity, the distribution curve in the presence of the percolation must intersect with that of no percolation. Thus, the required intersection between the two curves may serve as the second criterion.
To support those criteria, we added a percolation path to the TCAD simulation structure in terms of the negatively fixed charges, following the approach in [18]. The number of fixed charges in this paper is 16 and hence the average density of fixed charges is 1.3 × 1012 cm−2. Simulated
I –V and potential distribution over channel are shown in
Figs. 2(a) and 5(a), respectively. Different positions of the trap (693 positions) correspond to different simulatedId/Id
values, thus producing a map ofId/Id as together shown in
Fig. 5(b). These trap-position-dependentId/Id distributions
are quite smooth, due to the very short distance from position to position. CorrespondingId/Id distribution curve is added
to Fig. 4.
Evidently, our TCAD simulated Id/Id distribution curve
due to fixed charges intersects with that of no such fixed charges, with the two following features newly created: 1) part of its distribution near the lowerId/Id limit is slightly higher
than no percolation and 2) a tail distribution appears at higher
Id/Idthan the upper limit of headed distribution. Our
simula-tion results resemble those of 50/50 nm by Asenov et al. [21] [Fig. 1(b)], despite different percolation origins between the two. However, to make the comparison fair, we further quoted one of their simulated ones under the same channel dimension [25], as shown in Fig. 4. Once again, the intersection with the headed curve remains. Note that our TCAD simulated
Id/Id has a wider tail distribution to a maximum value
of around 60%, higher than that (40%) of the citation [25]. Such difference may be attributed to the two factors: 1) more strategic traps in this paper and 2) larger sample size in this paper (see the labels in Fig. 4).
Therefore, these key criteria considerably act as guidelines through (7) in the use of (3). To illustrate this, we show in
Fig. 6. CalculatedId/Idheaded and tail distribution curves. Lt 0= 19.7 nm,
a= 0.10, and b = 4.11 nm. (a) mloc= 0.01 and (b) mloc= 0.2, with σloc
as a parameter. TCAD created distributions from this paper and the literature (Vd = 0.01 V) [25] are shown for comparison. In this paper, Vg = 0 and
Vd= 0.05 V.
Fig. 6 the calculated results, for two different values of mloc
with σloc as a parameter. It can be seen that the distribution
curve rotates clockwise as mloc decreases, thus increasing the
probability of intersecting with the headed one. This is the case for decreasing σloc. Such rotational change is simply
to make the area under the resulting curve remain of unity. Thus, for all σloc illustrated, the condition of mloc = 0.01
satisfies the criteria; however, as mloc is increased to 0.2,
onlyσlocof less than 0.35 can have the expected intersection.
Extra works were done, leading to a critical σloc versus mloc
curve below which the curve intersection occurs, as shown in Fig. 7. Obviously, mlocandσlocare not unlimited. Specifically,
simulated tail distribution due to fixed charges in this paper can be reproduced with σloc of 0.35 for mloc= 0.01 and σloc
of 0.25 to 0.35 for mloc = 0.2. This indicates that: 1) the
extracted mloc and σloc from a percolation channel are not
unique and 2) the tail distribution of the percolation channel can be reproduced from a few critical mlocandσloc. Next, for
the case of random discrete dopants [25], the optimumσlocat
mloc= 0.2 is 0.15 [Fig. 6(b)], which is less than fixed charges
ones. Thus, different percolation origins and/or paths can have different combinations of mloc and σloc. Further fitting to
Fig. 7. Plot of a criticalσlocversus mloccurve as drawn from the works, as
in Fig. 6. Only for sets ofσlocand mloclying below the curve, the calculated
tail distribution can have intersections with the headed distribution. Extracted
σloc and mloc from the tail distributions for three gate voltages [25] appear,
as expected, in the allowed region.
Fig. 8. Symbols: extracted Ltversus the trap distance at three gate voltages.
Fitting lines using (4) are shown. Corresponding model parameters are: 1) Lt 0 = 19.7 nm, a = 0.10, and b = 4.11 nm for Vg = 0; 2) Lt 0 =
16.7 nm, a= 0.02, and b = 2.57 nm for Vg= 0.4 V; and 3) Lt 0= 4.7 nm,
a= 0.07, and b = 4.50 nm for Vg= 0.8 V.
other tail distributions [25] was done concerning the effect of gate voltage. We found that extracted mloc and σloc have
significantly low values, if the gate voltage is large enough, as shown in Fig. 7.
IV. EXTENSION ANDDISCUSSION
We further extend the work to RTS-induced threshold volt-age shift, at three gate voltvolt-ages: Vg= 0, 0.4, and 0.8 V. Since
the threshold voltage is 0.37 or 0.52 V [Fig. 2(a)], these three gate voltages separately represent the subthreshold, transition, and inversion region of operation. CorrespondingId/Id
mag-nitudes in the percolation free channel had been simulated by 3-D TCAD, leading to Lt in Fig. 8 as a function of the trap
distance. The figure clearly reveals that the maximum Lt stems
from midchannel traps (d = 0), valid for all gate voltages illustrated. Increasing gate voltage produces a decrease in Lt,
as expected due to increased electron screening. This strongly corroborates the applicability of (4) and hence the statisti-cal model (6) in the transition and above-threshold region.
Vth= −
SS
ln 10ln 1−
Id
Id . (8)
Using the function transformation, one can reach the distrib-ution function for the threshold voltage shift
l(Vth) = g Id Id ln 10 SS exp −Vth SS ln 10 . (9)
The other is the transconductance method [34] for the inver-sion case
Vth= (Vg− Vth)Id
Id . (10)
Since the gate overdrive (Vg−Vth) is constant, the transformed
Vthdistribution is theId/Iddistribution times this constant.
ResultingVthdistributions are given in Fig. 9, all featuring
headed ones. We found that Vth distributions from both
transformation methods are almost the same at Vg= 0.4 V, the
transition region between subthreshold and inversion. In Fig. 9, we add the simulated Vth distribution curves due to
ran-dom discrete dopants as quoted from the same source [25]. Again, the intersection with the headed curve appears in case of RTS-induced threshold voltage shift, in a wide range of gate voltages. Next, we combine the Iloc/Id statistical
model [(3) with (7) incorporated] with the Id/Id to Vth
transformation formulas, to reproduceVth tail distributions.
In the beginning, we fixed mloc and σloc at the optimum set
(mloc= 0.2 and σloc = 0.15), as mentioned in the preceding
section for the same random discrete dopants. CalculatedVth
distributions are shown to be comparable with those simulated with the random discrete dopants in channel [25], but only valid at Vg = 0 and 0.4 V. Serious discrepancies take place,
as Vg increases to 0.8 V. We found that both mloc and σloc
must be reduced in this inversion regime. With the new values
of mloc = 0.05 and σloc = 0.05, reasonable reproduction is
achieved. Such change in mloc and σloc supports those of
arguments by Asenov et al. [21] from their simulation task that underlying percolation paths will electrically change, when the operating conditions change. Extra evidence exists. In [22], experimentally extracted percolation coefficients undergo significant change from subthreshold to inversion.
More recently, Asenov’s group published their works on the impact of including STI in the simulation structure [31], [32]. Relatively, such STI substructure was lacking in this paper; but essentially, this can be compensated by adding a delta width, according to [35] and [36]. In this sense, extra TCAD simulation is needed to accommodate the increased effective width and hence the corresponding headed distribution can be expected in the percolation free channel. Ironically, we should focus on the width effect, especially the edge part in this paper.
Fig. 9. CalculatedVth(green solid lines) headed and (nonsolid lines) tail
distribution curves at (a) Vg= 0, (b) Vg= 0.4 V, and (c) Vg= 0.8 V.
Sim-ulated (red solid lines) tail distributions due to random discrete dopants [25] are shown, along with calculated ones from several values of mlocandσloc.
Clearly, mloc and σloc both must be reduced while entering into inversion
regime, indicating that the underlying percolation paths electrically change, as well known in the field. Vd= 0.05 V in this paper.
Fig. 10 shows the simulated potential andId/Id distribution
over channel in the absence of the percolation. It can be seen that potential is uniform from edge to edge in the width
Fig. 10. Simulated potential and Id/Id distribution over channel
corre-sponding to the headed distribution in Fig. 4.
direction, whereas Id/Id values near both edges are much
smaller than the remaining region around the midchannel. Such region of smallerId/Id is very limited, thus
contribut-ing insignificantly to the TCAD simulated headed distribution in this paper. More importantly, such edge effect may further be weakened if the delta width is incorporated.
Furthermore, we want to stress that the model derivation procedure can handle the large drain voltage conditions. First, corresponding trap distance dependencies [21], [26] differ significantly from those of low drain voltage as in this paper. Even such situations are likely to occur for device with halo implant or nonuniform doping in the channel, which were not particularly included in this paper. Thus, the empirical formula used in this paper for Lt, (4), might fail and is better replaced
with other more suitable ones. Nevertheless, the presented model derivation and function transformation essentially holds and key criteria and guidelines can further be reached as well. Finally, we summarize the merits of the proposed statistical model as follows.
1) It needs only a few trap positions in the 3-D TCAD percolation-free simulation (or an analytical 3-D I –V model without using any 3-D TCAD tools), without doing too much in this numerically demanding process. 2) It can efficiently create headedId/Id andVth
distri-butions and thereby criteria and guidelines for the tail distributions.
3) It can effectively overcome the limitations of the statistical experiment or 3-D simulation in the field, such as the limited sample size, the numerical error, the measurement precision, the unrefined mesh, and even the extraordinarily huge CPU time.
V. CONCLUSION
The closed-form statistical model has been devised and has reproduced headed distributions of two-level RTS magnitudes in the subthreshold current at low drain voltage. Key criteria have been drawn and guidelines have therefore been created to enable the adequate use of the literature Iloc/Id formula
in percolation case. Resulting tail distributions have shown to be in agreement with those obtained from 3-D TCAD simulations. Extension to threshold voltage shift counterparts
has satisfactorily been done. Effect of varying gate voltage from subthreshold to inversion on the underlying percolation path, through the two key parameters (mean and standard deviation) of Iloc/Id, has been explicitly examined. Other
issues such as width dependence, large drain voltage, and nonuniform doping have been addressed. Merits of the model proposal have been summarized.
REFERENCES
[1] K. S. Ralls et al., “Discrete resistance switching in submicrometer silicon inversion layers: Individual interface traps and low-frequency (1/ f ?) noise,” Phys. Rev. Lett., vol. 52, no. 3, pp. 228–231, Jan. 1984. [2] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: A new
perspective on individual defects, interface states and low-frequency (1/ƒ) noise,” Adv. Phys., vol. 38, no. 4, pp. 367–468, Jul. 1989. [3] M. J. Chen and M. P. Lu, “Electrically probing atomic-sized oxide
traps,” in Encyclopedia of Nanoscience and Nanotechnology, vol. 13, H. S. Nalwa, Ed. Valencia, CA, USA: American Scientific Publishers, 2011, pp. 243–261.
[4] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “Random telegraph noise of deep-submicrometer MOSFETs,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 90–92, Feb. 1990.
[5] M. Schulz, “Coulomb energy of traps in semiconductor space-charge regions,” J. Appl. Phys., vol. 74, no. 4, pp. 2649–2657, Aug. 1993. [6] H. H. Mueller, D. Wörle, and M. Schulz, “Evaluation of the
Coulomb energy for single-electron interface trapping in sub-μm metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 75, no. 6, pp. 2970–2979, Mar. 1994.
[7] A. Palma, A. Godoy, J. A. Jiménez-Tejada, J. E. Carceller, and J. A. López-Villanueva, “Quantum two-dimensional calculation of time constants of random telegraph signals in metal–oxide–semiconductor structures,” Phys. Rev. B, vol. 56, no. 15, pp. 9565–9574, Oct. 1997. [8] Z. Celik-Butler and F. Wang, “Effects of quantization on
random telegraph signals observed in deep-submicron MOSFETs,”
Microelectron. Rel., vol. 40, no. 11, pp. 1823–1831, 2000.
[9] M. Xiao, I. Martin, and H. W. Jiang, “Probing the spin state of a single electron trap by random telegraph signal,” Phys. Rev. Lett., vol. 91, no. 7, p. 078301, Aug. 2003.
[10] M.-P. Lu and M.-J. Chen, “Oxide-trap-enhanced Coulomb energy in a metal-oxide-semiconductor system,” Phys. Rev. B, vol. 72, no. 23, p. 235417, Dec. 2005.
[11] J.-W. Lee, B. H. Lee, H. Shin, and J.-H. Lee, “Investigation of random telegraph noise in gate-induced drain leakage and gate edge direct tunneling currents of high-κ MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 913–918, Apr. 2010.
[12] H.-J. Cho et al., “Investigation of gate etch damage at metal/high-κ gate dielectric stack through random telegraph noise in gate edge direct tunneling current,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 569–571, Apr. 2011.
[13] B. Oh et al., “Characterization of an oxide trap leading to random telegraph noise in gate-induced drain leakage current of DRAM cell transistors,” IEEE Trans. Electron Devices, vol. 58, no. 6, pp. 1741–1747, Jun. 2011.
[14] W. Goes, F. Schanovsky, T. Grasser, H. Reisinger, and B. Kaczer, “Advanced modeling of oxide defects for random telegraph noise,” in
Proc. 21st ICNF, Jun. 2011, pp. 204–207.
[15] I.-O. Yoon, S. Choi, S. Rhee, H. Kim, S. Park, and Y. J. Park, “Correction of the RTN model considering 3D effect of single trapped charge,” in
Proc. SISPAD, Sep. 2012, pp. 412–415.
[16] S.-W. Yoo, Y. Son, and H. Shin, “Capture cross section of traps causing random telegraph noise in gate-induced drain leakage current,” IEEE
Trans. Electron Devices, vol. 60, no. 3, pp. 1268–1271, Mar. 2013.
[17] E. Simoen, B. Dierickx, C. L. Claeys, and G. J. Declerck, “Explaining the amplitude of RTS noise in submicrometer MOSFETs,” IEEE Trans.
Electron Devices, vol. 39, no. 2, pp. 422–429, Feb. 1992.
[18] H. H. Mueller and M. Schulz, “Random telegraph signal: An atomic probe of the local current in field-effect transistors,” J. Appl. Phys., vol. 83, no. 3, pp. 1734–1741, Feb. 1998.
[19] A. Avellan, W. Krautschneider, and S. Schwantes, “Observation and modeling of random telegraph signals in the gate and drain currents of tunneling metal–oxide–semiconductor field-effect transistors,” Appl.
“Comprehensive analysis of random telegraph noise instability and its scaling in deca–nanometer flash memories,” IEEE Trans. Electron
Devices, vol. 56, no. 8, pp. 1746–1752, Aug. 2009.
[25] M. F. Bukhori, S. Roy, and A. Asenov, “Simulation of statistical aspects of charge trapping and related degradation in bulk MOSFETs in the presence of random discrete dopants,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 795–803, Apr. 2010.
[26] N. Ashraf and D. Vasileska, “Static analysis of random telegraph noise in a 45-nm channel length conventional MOSFET device: Threshold voltage and on-current fluctuations,” IEEE Trans. Nanotechnol., vol. 10, no. 6, pp. 1394–1400, Nov. 2011.
[27] M. Agnostinelli et al., “Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node,” in IEEE IEDM Tech. Dig., Dec. 2005, pp. 655–658.
[28] H. Kurata et al., “The impact of random telegraph signals on the scaling of multilevel flash memories,” in Symp. VLSI Circuits, Dig. Tech. Papers, 2006, pp. 112–113.
[29] R. W. Keyes, “The effect of randomness in the distribution of impurity atoms on FET thresholds,” Appl. Phys., vol. 8, no. 3, pp. 251–259, 1975. [30] TCAD Sentaurus, version G-2012.06, Synopsys, Mountain View, CA,
USA, 2012.
[31] X. Wang, S. Roy, A. R. Brown, and A. Asenov, “Impact of STI on statistical variability and reliability of decananometer MOSFETs,” IEEE
Electron Device Lett., vol. 32, no. 4, pp. 479–481, Apr. 2011.
[32] S. M. Amoroso, A. Ghetti, A. R. Brown, A. Mauri, C. M. Compagnoni, and A. Asenov, “Impact of cell shape on random telegraph noise in decananometer flash memories,” IEEE Trans. Electron Devices, vol. 59, no. 10, pp. 2774–2779, Oct. 2012.
[33] M.-J. Chen, J.-S. Ho, and T.-H. Huang, “Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling,”
IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 259–262, Feb. 1996.
[34] J. Franco et al., “BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic,” Microelectron. Rel., vol. 52, nos. 9–10, pp. 1932–1935, Jul. 2012.
[35] C.-Y. Hsieh, Y.-T. Lin, and M.-J. Chen, “Distinguishing between STI stress and delta width in gate direct tunneling current of narrow n-MOSFETs,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 529–531, May 2009.
[36] C.-Y. Hsu et al., “Enhanced hole mobility in non-(001) oriented sidewall corner of Si pMOSFETs formed on (001) substrate,” in Proc. IEEE SNW, Jun. 2010, pp. 67–68.
Ming-Jer Chen (S’78–M’79–SM’98) received the
Ph.D. degree from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1985.
He has been a Professor with the Department of Electronics Engineering, NCTU, since 1985. He has supervised 20 Ph.D. and more than 100 M.S. stu-dents, all in the area of device physics.
Dr. Chen is a member of the Phi Tau Phi.
Huan-Hsiung Wang received the B.S. degree in
electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, in 2011, where he is currently pursuing the M.S. degree with the Department of Electronics Engineering, Institute of Electronics.
Chuan-Li Chen received the B.S. degree in
electro-physics from the National Chiao Tung University, Hsinchu, Taiwan, in 2012, where he is currently pursuing the M.S. degree with the Department of Electronics Engineering, Institute of Electronics.
Shiou-Yi Lai received the M.S. degree in
electron-ics engineering from the Department of Electronelectron-ics Engineering, Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2013.
He is currently with the Ministry of the Interior, Taipei, Taiwan.
You-Sheng Liu is currently pursuing the B.S. degree
with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan.