A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation

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ence, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, postamplifier, and digital demodulator on a single chip, the total power consumption is 20.4 mW. The measured phase noise from a recovered carrier at 2.432 GHz is about 111 dBc/Hz at 1 MHz offset. The chip size is 1.75 1.55 mm2.

Index Terms—Body area network (BAN), carrier recovery, de-modulator, QPSK, reference-less, wireless receiver.

I. INTRODUCTION

W

IRELESS sensor networks (WSN) and bio-inspired electronics have drawn tremendous research efforts [1]–[9] recently. For sensor node integrated circuits design, small form factor, low power, and system cost are of special interests to promote pervasive and ubiquitous adaptations. Conventionally, RF receiver front-end includes a LO (local os-cillator) generator that utilizes crystal or other resonator based reference for carrier frequency synthesis. The crystal oscillator itself in general dissipates extra power and is too bulky for single chip integration. Meanwhile, due to unavoidable crystal frequency mismatches between the transmitter and receiver side, a carrier recovery loop is required at the digital base band to compensate frequency offset for data demodulation.

Recently, several techniques were proposed to generate on chip reference frequency in integrated circuit technologies to re-place crystal [10]–[16]. Most of their accuracy falls in the range of a few percent while consuming milliwatt power. For the fre-quency accuracy to be closer to that of a temperature-compen-sated crystal oscillator (TCXO), it may require additional costly trimming process [10].

This paper proposes a low cost, small form factor, single chip reference-less wireless receiver which recovers the LO fre-quency directly from the received RF signal [17]. Based on the

Manuscript received December 06, 2010; revised March 23, 2011; accepted July 18, 2011. Date of publication October 03, 2011; date of current version Feb-ruary 24, 2012. This work was supported in part by the Mediatek Inc., the An-soft Corporation, ITRI/STC, and the National Science Council (NSC), Taiwan, under Grant 97-2220-E-009-009-. This paper was recommended by Associate Editor H. Luong.

The authors are with the Department of Electronics Engineering and the In-stitute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: wzchen@mail.nctu.edu.tw).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2011.2165417

Fig. 1. (a) Proposed receiver architecture. (b) Frequency acquisition mode. (c) Phase tracking and data demodulation mode.

concept of wireless remote frequency synchronization to the transmitter side, it eliminates extra reference generator at the re-ceiver side, and also facilitates wireless clock distribution. Since the LO carrier at the receiver side is tracking the frequency at the transmitter side directly during data receiving, the issue of carrier frequency offset between the transmitter and receiver in conventional wireless transceivers is eliminated. Meanwhile, it

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506 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 3, MARCH 2012

Fig. 2. (a) Frequency discriminator. (b) Timing diagram of edge counter.

accomplishes data demodulation along with carrier and timing recovery without resort to an extra baseband ADC.

This paper is organized as follows. Section II describes the proposed receiver architecture and operation principle. The system behavior and stability is discussed in Section III. Section IV introduces the detailed circuit schematic of each block. Experimental results are shown in Section V, and Section VI concludes this paper.

II. ARCHITECTURE

To demonstrate the proposed concept, an experimental pro-totype for QPSK wireless receiver at 2.4 GHz is implemented. Fig. 1(a) shows the receiver architecture. It integrates LNA, mixer, channel selection filter, postamplifier, data demodulator, frequency discriminator, and LO carrier recovery loop (CRL) on a single chip. As a single channel experimental prototype, the interference is rejected by both external band selection filter and on chip channel selection filter. The LNA and mixer respec-tively provide 16.6 dB and 6.7 dB gain. The postamplifier in-corporating channel selection filter are composed of six stages, which enlarge the output to digital swing.

The CRL composes of a VCO, prescaler, divider and multi-phase generator, multi-phase selector (MUX), and a gating multi-phase fre-quency detector (GPFD). Incorporating with the data demod-ulator, it recovers carrier frequency and clock from the QPSK modulation signal for frequency down conversion and data de-modulation.

A. Frequency Acquisition

Let the cascade divide ratio of the prescaler and feedback di-vider be denotes the VCO frequency, and repre-sents the IF frequency. At the onset for data receiving, a constant phase preamble from the transmitter is received, and the voltage controlled oscillator (VCO) is preset to its highest fre-quency which is larger than . The CRL is operated in the frequency acquisition mode, as illustrated in Fig. 1(b). Mean-while, the phase selector (MUX) passes a fixed divider output phase (one of ) to the GPFD. The down converted

Fig. 3. (a) QPSK signal constellation. (b) Demodulator. (c) Timing diagram.

signal , where , is then compared to by the GPFD. If decreases so that

is reduced more than for . Contrarily, if increases so that is increased more than . By the negative feedback mechanism, when the loop is settled

(1) Thus, the local frequency is determined by and the RF input frequency, where

(2) The frequency locking detector is realized by a frequency dis-criminator. Fig. 2 illustrates detailed circuit schematic, which is based on the concept of edge counting [18]. As is described in (1), when the loop approaches locked, the IF frequency would be equal to the divider output In order to improve the resolution for frequency detection, is scaled down by to generate a control signal . The high and low level of alternatively performs as gating pulse of , whose counting edges are stored in two latches. In this design, if the contents of latches fall within , the confident counter will be toggled. When the contents in latches hit the target con-secutively, implying that approaches locked state, and the status of frequency locked is then resolved by the confident counter.

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Fig. 4. (a) Receiver behavior model. (b) Equivalent model. (c) Noise model.

To successfully demodulate M-ary phase modulation signal, the IF signal should fall into one of the M phase zones during data demodulation. It means that the frequency difference be-tween and should be within a locking window before the CRL steps into phase demodulation. For an M-ary PSK modu-lation signal, let be the symbol rate, it can be shown that the lower bound of can be derived as

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B. Phase Tracking and Data Demodulation

When the loop approaches locked, the receiver will acknowl-edge transmitter for data receiving. The mode control signal (Mod_CTL) will then switch the CRL to phase tracking mode, as illustrated in Fig. 1(c). Afterwards, the CRL will keep track the carrier frequency as well as demodulate the QPSK signal si-multaneously.

Fig. 3 illustrates the scheme for QPSK demodulator and timing diagram for the gating PFD. At the postamplifier output, switches its phase among ( 180 , and 270 ) period-ically at symbol rate , as is shown in Fig. 3(a). For QPSK demodulation, the divider output generates 8 phases to capture . Here ( divides

Fig. 5. The simulated settling behavior. TABLE I DESIGNEDPARAMETERS

the signal constellation into four zones, and the IF signal is directly demodulated by detecting the operating zones (I, II, III, IV) that falls into. This is accomplished by sampling using followed by edge detector and decoder. The I/Q digital output is then demodulated after confident counter, as shown in Fig. 3(b)

In each phase zone, the targeted phase for frequency tracking and phase synchronization is respectively. The demodulator then switches its corresponding targeted phase according to the demodulated I/Q data through the MUX to the GPFD. Thus, the CRL can continuously track the RF signal to maintain the stability of VCO output frequency during data receiving. To avoid mis-disturbing the carrier frequency during phase switching in QPSK signaling, a timing controller in the demodulator will generate gating pulse (GP) to enable the GPFD, as also shown in Fig. 3(c). In each symbol time , let the clock cycles for data demodulation (zone detection) be , the setup time for next data period phase transition be , and the ratio between IF frequency ( and symbol rate be , i.e.,

(4) During these intervals , the GPFD is disabled by GP. The active period (GDC) for the GPFD becomes

(4)

Fig. 6. Low-noise amplifier based on: (a) source and (b) common-gate topology.

Fig. 7. Differential gm-boosted CGLNA.

The loop bandwidth for the CRL during phase tracking and data demodulation mode is designed by taking GDC into ac-count. On the other hand, the tracking bandwidth against noise disturbance for data demodulation reflects in . Both suggest that a higher improves its robustness for demodulation and carrier tracking performance, but also demands a wider band-width of IF amplifier and demodulator.

III. BEHAVIORMODEL

The stability of the wireless carrier recovery loop is investi-gated using a PLL-like linear model. Fig. 4(a) shows the system block diagram. Let the gain of PFD and charge pump be , VCO gain be , and the transfer function of loop filter and postamplifier be and respectively.

The phase transfer function from the received RF signal to the VCO output can be derived as

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Fig. 8. Frequency down-converted mixer.

Fig. 9. Postamplifier architecture.

where . In this design, the bandwidth of postamplifier is much higher than the IF frequency such that the phase shift caused by is negligible. Thus, the system transfer function can be simplified as

(7) If ( in this case), the system transfer function can be approximated as

(8) Thus, the signal transfer function is the same as that of a typ-ical PLL with feedback factor equal to 1, as is shown in Fig. 4(b). The loop gain can be designed to maintain its stability ac-cordingly. Fig. 4(c) illustrates the noise model of the receiver front end, where – denotes the excess noise caused by the receiver front-end, and NF is the corresponding noise figure. We have

– –

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Fig. 10. Gain cell of postamplifier.

Fig. 11. Full wave rectifier for RSSI.

Thus, the VCO phase noise will be elevated by the noise figure of the receiver front-end after phase locked. The designed parameters are summarized in Table I, and the simulated settling behavior is shown in Fig. 5.

The GPFD is compared at IF frequency and is peri-odically enabled and disabled by the gating pulses (GP) for an active period of GDC, which is generated from the I/Q demod-ulator at a symbol rate . Assuming that the voltage ripple caused by the nonidealities of PFD, charge pump and periodi-cally gating is represented as

(10) where presents the ripple amplitude and is the gating pulse. If the VCO gain is represented as , and its output frequency is , the VCO output can be represented as

(11) where GDC should be greater than zero to maintain the close loop system. Equation (11) reveals that the reference spurs will spread at multiples of at double side of the center

Fig. 12. The circuit schematic of VCO.

Fig. 13. The circuit schematic of charge pump and loop filter.

frequency. On the other hand, the higher data rate results in a lower reference spurs. The maximum spurs will occur at which dominates the SFDR of output spectrum. Therefore, the SFDR can be approximated as

(12) It can be seen that the SFDR is improved by a factor of since the GPFD only activates for a short period. The SFDR will be the same as that of a conventional PLL if GDC equals to 1. In this design, is the 1 MHz symbol rate,

is the 16 MHz IF signal, and GDC is around 0.25. IV. BUILDINGBLOCKS

A. Low Noise Amplifier

Conventionally, low noise amplifiers in RF receiver are based on common-source [19] or common-gate [20] architectures, as are shown in Fig. 6. A common-source LNA (CSLNA) in gen-eral has better noise performance compared to its common-gate counterpart (CGLNA). However, it requires two on-chip induc-tors for narrow band input matching [21]. Contrarily, CGLNA only needs a single inductor for input matching, as shown in

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Fig. 14. The architecture of: (a) feedback divider, (b) timing diagram of di-vided-by-19 divider, and (c) NAND gate embedded TSPC filp-flop.

Fig. 6(b). It can provide broadband matching depending on the quality factor of the resonator .

The noise figure of a common gate LNA can be derived as

(13) where and are bias-dependent parameters. To further im-prove its noise performance, differential gm-boosted CGLNA topology is adopted in this design [20]–[22]. Fig. 7 shows the detailed circuit schematic. Its noise figure can be derived as

–

(14)

Fig. 15. Chip microphotograph.

where by differential excitation. By choosing , the noise figure can be derived as

– (15)

(15) shows that the noise figure performance can be improved compared to (13) thanks to differential boosted technique. On the other hand, its power consumption for input matching can be reduced.

B. Frequency Down-Converted Mixer

A double-balanced Gilbert mixer with active load is adopted for frequency down conversion. Fig. 8 shows the circuit schematic. In a typical Gilbert mixer, the low frequency and high frequency noise contribution can be derived as [23]

(16) (17) where and respectively shows the amplitude and slope of the LO signal, is the dc current, is the LO period, de-notes low frequency input-referred noise of LO, is Boltzman’s constant, is absolute temperature and is the channel noise factor. (16) and (17) reveal that both the high and low frequency noise contributed by switching pairs are proportional to . Let represents the overdrive voltage of M and M , the conver-sion gain can be approximated as

(18) To relax the severe trade-off between the conversion gain and noise figure, current bleeding technique is adopted in this design [24]. By injecting currents and into the transconductance stage, it can decrease the dc current flowing through the com-mutating stage and lower the noise contribution from switching pair while sustaining the conversion gain.

The simulated conversion gain of LNA and mixer are about 16.6 dB and 6.7 dB, and noise figure are about 3.5 dB and 13.3

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Fig. 16. Measured recover spectrum of the local oscillator.

Fig. 17. Measured frequency locking time.

Fig. 18. Measured phase noise performance.

dB respectively. The corresponding single sideband noise figure of front-end circuits is about 7.3 dB.

C. Postamplifier

The received RF signal is amplified to digital output swing by a postamplifier. Fig. 9 shows the circuit schematic. It pro-vides received signal strength indicator (RSSI) to adjust the conversion gain in the receiver front-end. The postamplifier is composed of an offset-cancellation amplifier (A ) followed by five identical gain cells (A ) and an offset cancellation network (R -R , C -C , A ).

To achieve low power design goals, all the amplifiers are based on Cherry-Hooper topology [25] to have a better power

Fig. 19. Eye diagram for demodulated signal.

efficiency in terms of gain-bandwidth performance. Fig. 10 shows the detailed circuit schematic of a gain cell. Here M -M performs as a transconductance stage, while M -M and performs as a transimpedance stage.

The common mode feedback loop of the transconductance stage is realized by PMOS operating in linear region (M , M ) to save chip area. The core amplifier of the TIA is an inverter-based architecture for gain enhancement and low power opera-tion by reusing dc biased current. The transfer funcopera-tion of each gain stage can be derived as

(19) where

For a maximally-flat Butterworth response , the dB bandwidth of the gain stage can be approximated as

(20) The plateau gain of the postamplifier is about 70 dB and the high frequency dB bandwidth is 80 MHz, which is five times more than the IF bandwidth to alleviate group delay variations. The RSSI is composed of a RC low-pass filter (R and C ) and four stage full wave rectifiers (FWR), which are connected to the output of gain cells. Fig. 11 shows the detailed circuit schematic of the full wave rectifier. The input voltage is con-verted to current form by the differential pair (M -M ), and then

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TABLE II PERFORMANCEBENCHMARK

rectified through current mirrors (M -M ) and (M -M ). The dynamic range of RSSI is about 40 dB.

D. Carrier Recovery Loop

The CRL consists of a VCO, prescaler, divider, multiphase generator, phase selector (MUX), and a gating phase frequency detector (GPFD). Incorporating with the data demodulator, it recovers carrier frequency and clock from the QPSK modulation signal for frequency down conversion and data demodulation.

Fig. 12 illustrates the LC tank QVCO. Based on complemen-tary architecture, it improves phase noise performance thanks to a more symmetric output waveform [26]. Also, it benefits from two fold negative conductance for power saving. Here both C and C are accumulation mode MOS varactors for fine fre-quency tuning. In addition, SC and SC are added in parallel for coarse tuning to cope with PVT variations.

Fig. 13 shows the schematic of charge pump and loop filter. To alleviate reference spurs induced by current mismatch of up and down currents ( and ) due to channel length modu-lation, a regulated current feedback loop consisted of A , and is employed. Here and are replicas of and , and the pumping currents can track each other by adjusting the gate voltage of the current source [27].

The divider chain in the feedback path of the CRL is com-posed of a high speed divided-by-19 divider followed by a vided-by-8 divider, as shown in Fig. 14. The divided-by-19 di-vider is composed of a 4/5 prescaler, a divide-by-4 didi-vider and a control logic. Fig. 14(b) shows the timing diagram. To reduce power dissipation as well as propagation delay, TSPC flip-flops with embedded NAND gates are incorporated in the dividers, as

shown in Fig. 14(c). The synchronous divided-by-8 divider also performs as a multiphase generator. Fig. 14(a) shows the circuit schematic. The 8 phases output signals are then utilized to cap-ture QPSK symbols, and one of them is passed to the GPFD for phase tracking.

V. EXPERIMENTALRESULTS

The single-chip crystal-less wireless receiver has been fab-ricated in a 0.18 m CMOS process, and powered by a 1.8 V supply. A single channel experimental prototype is imple-mented to demonstrate the concept. The power dissipation for the RF/analog front-end

is about 9.6 mW, while the data de-modulator and CRL consumes about 10.8 mW. Fig. 15 shows the chip photograph. The chip size is 1.75 1.55 mm , and is mounted on a printed circuit board for measurement.

The rejection of out band interferers mainly relies on ex-ternal band selection filter. By using TA0532A SAW filter, the out band interferers are suppressed 40 dB. Besides, a 6th order low pass filter is implemented incorporating postamplifier for channel selection in this design. To emulate the RF signal at the transmitter side, a 1 Mbps QPSK modulated signal is gen-erated by Tekronix AWG7000B arbitrary waveform generator, and then up converted to 2.416 GHz through R&S SMIQ03 signal generator. For , the in band signal to in-terference ratio must be higher than 15 dB to maintain phase locked. With dBm input signal at the receiver side the mea-sured recovered spectrum is shown in Fig. 16. It can be seen that the closest spurs are at 1 MHz offset corresponding to the data rate. The sensitivity can be further improved by reducing signal

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less sensor applications. Compared to the prior art, the pro-posed receiver accomplishes frequency down conversion as well as OQPSK demodulation without extra ADCs, on chip refer-ence, and additional carrier recovery loops in the base band. It achieves much higher data rate (1 Mbps) in contrast to the prior art.

VI. CONCLUSION

This paper proposes a novel single chip wireless QPSK re-ceiver without resort to extra resonator based reference. In con-trast to conventional architectures, the receiver recovers the RF carrier frequency directly from the incident radio signal for fre-quency down conversion. Meanwhile, it accomplishes phase and frequency tracking as well as QPSK demodulation simulta-neously. Thus, no additional baseband ADCs or timing recovery loop are required in this receiver. It greatly improves the system integration level.

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Wei-Zen Chen received the B.S., M.S., and Ph.D.

degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1992, 1994, and 1999, respectively.

He was with ITRI/ERSO in 1999 involved in the development of CMOS RF ICs for cellular and wireless LAN applications. From 1999 to 2002, he was an Assistant Professor with the Department of Electrical Engineering, National Central Univer-sity, Chung-Li, Taiwan. Since 2002, he joined the Department of Electronics Engineering, National Chiao-Tung University, where he is currently a full Professor. He serves as the IEEE Solid-State Circuit Society Taipei Chapter chairman starting from 2008, the deputy executive director of National SoC Program (NSoC) from 2009 to 2011, and is currently the principal investigator of National Program of Intelligent Electronics (NPIE) in Taiwan. His research focuses on mixed-signal integrated circuit for wireless and wireline communication systems, with special emphasis on Serdes, high speed interface, optical communication, wireless PAN, LAN, and body area network applications.

Dr. Chen is a member of Phi-Tau-Phi honorary scholar society, technical pro-gram committee member of the IEEE Custom Integrated Circuits Conference (CICC) and Asian Solid-State Circuit Conference (A-SSCC).

Tai-You Lu received the B.S. degrees in electrical

engineering from National Cheng-Kung University, Taiwan, in 2003. He is currently working toward the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan. His research is focused on radio frequency integrated circuits for wireless communications. He is a member of Phi Tau Phi honorary scholar society.

Wei-Wen Ou was born in Taipei, Taiwan, in 1980.

He received the B.S. degree in electronic engineering from National Yunlin University of Science & Tech-nology, Yunlin, Taiwan. He is currently working the M.S. degree at National Chiao-Tung University, Hsinchu, Taiwan. His research interests include both analog and digital approaches of phase-locked loops, and high-speed CMOS data-communication circuits for multiple gigabit applications.

Shun-Tien Chou was born in Chiayi, Taiwan, in

1985. He received the B.S. degree in electronic and engineering from National Central University, Chung-Li, Taiwan, in 2007, and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 2010.

Currently, he is an Engineer with the R&D Divi-sion, Mstar, Inc., Hsinchu. His current research in-terests in analog circuit design for PLL and optical front-end.

Song-Yu Yang was born in Chiayi, Taiwan, in 1983.

He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2005 and 2008, respectively.

He is currently with MediaTek Inc., Hsinchu. His research interests focus on integrated circuit designs for high speed communication systems.