Polar transmitter for wireless communication system

Proceedings of 2005 International Symposium on Intelligent Signal Processingand CommunicationSystems

POLAR TRANSMITTER FOR

WIRELESS COMMUNICATION SYSTEM

Chung-Chun Chen, Hung-Yang Ko, Yi-Chiuan Wang, Hen-Wai Tsao, Kai-Yuan Jheng, and An-Yeu (Andy) Wu

Graduate Institute of ElectronicsEngineering,National TaiwanUniversity, Taipei 10617, Taiwan,ROC ABSTRACT

Polar modulation techniques offer the capability of multimode wireless system and the potential for the high

efficiencyPowerAmplifier (PA). Any input baseband complex

signal is decomposed into magnitude and phase signal, and goes through envelope modulator and phase modulator respectively. The modulated envelope and phase message signals arecombined and amplified by switched-mode PA. In this paper,wewill focusontherectangular-to-polar converter, envelope modulator and phase modulator of polar transmitter for EDGE (2.5G) system. The analog part includes open-loop envelope modulator. The digital part includes rectangular-to-polar converter and digital phase modulator. We employ the Coordinate Rotation Digital Computer (CORDIC) and Direct Digital Frequency Synthesizer (DDFS) techniques in this part. A prototype chip has been designed and fabricated in UMC 0.18umCMOS process withIP6M technology.

1. INTRODUCTION

Polar modulation offers the capability of achieving high

linearity and high efficiency simultaneously in a wireless

transmitter. Improved

efficiency

is achieved by using a highly efficient and non-linear PA to work at itspeak efficiency. Linear transmission is achievedby modulatingthe envelopeof thesignal throughthevoltage supplyof the PA.

Polar transmission utilizes envelope and phase component to represent the digital symbols instead of the conventional I/Q

format [1]. The basebandsignal V(t) issplit into thephase signal

a

(t)

and the

envelope signal A(t).

V(t)

=

x(t)

+j *

y(t).

A(t)

=

+x(t

+y

W

Ot)=tan" y(t) (2)

L~x(t))

It is clear that from Eq. (2) we can have a phase-only signal through phase modulator andmultiplied with its envelope atthe PA to restore the original complex signal V(t). This polar modulation process is like the Envelope Elimination and

Restoration (EER) [2] architecture. The Eq.(2) is done by a limiter andanenvelope detector. But the circuits will suffer from

thenon-linearity and distortion of the analog devices and would

causemismatch problem throughthetwopaths. Inthis paperwe proposed a DSP engine which includes rectangular-to-polar

converteranddigitalPhase Modulator(PM).Thedesigndoesnot have the distortionproblem caused by the analogcomponentsand

the phasemodulation process can be precisely controlledby the digital phasemodulator. The basebandphase signalis modulated

through digital phase modulator at the specific frequency range. The phase modulated signal is represented as

SIF

pM(t).

SIF_PM

(t)

=

cos(wct

+

q5(t)).

(3)

The PA stage ofamplitude modulator(AM)operates inprinciple

as amultiplierin ourdesignmodel. Thisgivesthe outputsignalin thespecific frequencyband as follows:

SIF(t)

=A(t) SsF-PM(t),

(4)

=x(t)

cos(wct)

+j*y(t)

sin(wct).

Forconvenience of the simulation model [2], thegainof the PA is set to one. Thus the Eq.(4)isequaltothesignalofEDGE,which

isup-converted atIntermediated Frequency (IF) band. The

non-linearityof PA and analysis of up-converter to Radio Frequency

(RF)stage arebeyondthe scope of this paper.

2. POLAR TRANSMITTER ARCHITECTURE

,,,,,,....,,...I

Delay 'nvelope Signal Adjust

DhaseSignal DSPEngine 5-10.4lMH hlixer, BPFI BPF2 Power Ampiifier SynthesizerIPLL

(1)

Fig. 1.Architecture ofpolartransmitter.

The architecture of thepolartransmitter is shown inFig. 1.The

rectangular-to-polar converter extracts the phase and envelope

information of asymbol inthedigital domain. Then theenvelope

signal is modulated by envelope modulator and fedthrough the

voltage supplyof the PA. Thephase information is modulatedby

digital phase modulator to create a constant envelope andphase

modulated signal. The phase modulated precision and channel selection can be well controlled in the digital part first. In this paper we use the concept from [3] to realize the digital phase

modulatordesign. The digitalfine-tune frequenciesaregenerated by the DDFS. The DDFS interpolates the carrier frequencies

between the coarse frequencies generated bythe integer-N PLL. The clock rate of the DDFS can be derived as in[3]. Inourdesign,

the clockrateof DDFS will be operated at26 MHz. The digital

finetuning frequenciesaregenerated bythe DDFS andlocatingat 5 MHz-10.4 MHz. Each interpolated frequency (channel) is stored in

thefine-tune

FrequencyControl Word(FCW)table.

0-7803-9266-3/05/$20.00

©2005

IEEE.

December13-16,2005

Hong Kong

=

A(t)

-

Re

ejo(t)

.ejw,t

I

-3. RECTANGULAR-TO-POLAR

CONVERTER

For acoordinate axis converter, we adopt the CORDICalgorithm

inourdesign since thealgorithm is verysimpleand low hardware cost. Inorder to further reduce the complexity, wealsoapplythe

techniquein[4] to ourrectangular-to-polarconverter. Forthe first iteration we move the inputvectorinto '-thand 4-thquadrantwith

simply sign inversing and dataexchanging. Second wereplaceYi

by

yi12-'

as comparedwith conventional CORDICalgorithm. This modification can save once iteration and one barrier shifter in the rectangular-to-polar converter. This can save more area in our

design.The iterations(fori=2-n)areshown inEq. (5).

xj+1=x +

d,

2-2(i-2) Yi, Yi+1=2.[y

-dx

Zi+1 =

zi

+

di

pi.

pi

= 1 tan-l

(2--2)

1

The approximated polynomial is generated according to the LS

algorithm. Inthispaperwe comparethe SpuriousFreeDynamic

Range (SFDR) performance with the other approximation

algorithm such as Taylor and Chebyshev [9]. The comparison

method is set the input phase from 0 to z/2. The phase word-length is 15-bit and amplitude output is 15-bit. From the simulation result in Fig. 4, we can see that the LS-based

polynomial can achieve better performance than other

approximationalgorithmwith lesspolynomialorder. Less order of

polynomialmeansthat low hardwarecomplexitycanbe achieved.

(5)

K= 1

1 +22(-2)

\li

The desiredphase is zi+l and the desiredenvelopevalue is

xi+]

multiplied by a constant scaling factor K. Due to the iterative

feature of CORDIC algorithm, the clock rate of this module is

n*fclk,

and n is iteration number. It is hard for the module to operate at suchhighclockrate. Acompromise isto useunfolded

techniqueand the architecture is shown inFig.2. Input stage Rotationstage-i Rotationstage-2

L---- --- L

Fig.2.Architecture ofrectangular-to-polarconverter.

4. DIGITAL PHASE MODULATOR

The DDFS architecture is shown inFig. 3. The DDFS has three

basic blocks: FCW

table, phase

accumulator and

phase-to-amplitude converter. The FCW table stores the desired fine-tune

frequencycontrol words and can be derived fromEq.(6).

f,

= FCW

fc/k

I

FCW

<

2L-1

(6)

Fig. 3. Architecture of DDFS

ComparisionbetweenLMS, Taylor,andChebyshev

+LS

Cheby. -n-Taylor

-I 2L 3 4 D D 8 9 V10

ApproximationOrder

Fig.4. SFDRcomparisonbetweenLS,TaylorandChebyshev.

Inorder to reduce thepolynomial order we further divide the

approximated region into eight segments. In each segment, the

approximatedpolynomialp(X) canberepresentedasinEq.

(7).

p(X)

=c 2x2+Cl X+C n1 n -1 k

ZRi2+±[cl]]*[X]n

+ E

Ck

2

n2/2

A1VAC([rom 1] + Q1

[X]n

*4 +[rom

2]n_

)

Q=

-2cl,2j+1

+

Cl,2j

+

Cl,2j-1

, c

1=0,

1 and

cl11

=

0,

I In

denote the truncation with n-bit.

(7)

(8)

In our design we focus on the phase-to-amplitude converter

design which is based on Least Squared

(LS) algorithm

[5] and

Merged-Multiply

Accumulator (MAC) technique [6]. The input phaseis truncatedby3-bitaccordingtothe

rT/4

symmetryand the

amplitude of the sine functioncanbe express

by

the

polynomial.

Where ci represents the

coefficient,

and X is the

phase

offset of each dividedregion. InEq. (7) we store the first term and third terminthelook-uptable. TheoperationsinEq.

(7-8)

nowbecome oneboothmultiplicationandtwo constantadditions. Thesecanbe

mergedinto a modified-MAC (Fig. 5). Xis inputtedtothe booth

decoder circuit and the partial productterm is

generated

in each

-614

-a0

cl

LL

row of MAC. The partial product terms are summed through Carry-Save-Adder (CSA) tree. As compared with the direct implementation of2thorderpolynomial, the CSA tree can prevent the carry ripple problem in the early stages, and the carry ripple only occurs at the final stage. Due to the EDGE spectral requirement we target the desired SFDR over 8OdBc. From Matlab simulation, we set thetruncated accumulated phase word-length to W=15 bits and amplitude word-length to P=14 bits. These hardware parameters canachieve SFDR=86dBc. The word-length of the phase of the EDGE signal will also introduce phase noise and spurs in the output spectrum and will be discussed in section 6. The proposed DDFS circuit is simulated by the

NANOSIMAtool and compares with state of the art in Table 1. The

proposed DDFS can achieve high SFDR performance. The power

efficiencyis alsosuperiortothe other designs.

n2-bitMultiplier

n3-bitMultiplicand OC 11 Co0

>Booth Encoder & Decoder P1

2~~~~~~~~~P

0' r 1tp3 P4

Partial Production P5

Summation &Mergedtwo _ P6

constantoperation 0 P7

I> , P8_P9

C1C C C8(kCCC C P

Sum &Carry Words Pi I

. _ _ __ _ on qp,*\ a 72 a uR5 R4 R RRifROtX P11

Final Adder

I> Result P23 P22P21 P20P19 P18 P17 P16 P15 P14 P13 P12

Fig.

5.Architecture of Modified-MAC. Table 1.Comparisonwith the existing DDFS designs.

CMOs Power

DDFS tech SFDR Latency efficiency

tech.

~~~(mW/MHllz)

Ours 0.18 86 5 0.15 Ref [7] 0.18 84 - 0.22 Ref [8] 0.25 90.3 13 0.66 Ref [9]

0.35

82.5 9 0.26 (Taylor) Ref[9] 0.35 73 7 0.35 (Chebyshev)[1] 05 80 2 Ref[10] 0.35 80 2 0.44 5.

ENVELOPE MODULATOR

Because open-loop architecture canprovidemorebandwidth and less cost than close-loop architecture, we use an open loop approachtodesignthe architecture ofenvelopemodulator(Fig. 6).

Thepre-distorteris needed in the openloop architecture.Besides,

the bandwidth and consideration of cost, the circuitintegration is another big issue. The inductance of the switched-mode power

supply is toolarge to set on chip. The integration problem may

cause many design problems and cost issues. Another design

issues we faced is that the speed of the switching of the power transistor. Based on aboveinvestigation, wedecided to adoptthe power supply named linearregulator shown inFig. 7[11][12] at the cost oflargerpower dissipation. The linear regulator could

provide faster switching rate and no inductance is needed. Before the linear regulator, a DAC is needed to convert the digital signal toanalog signal.

Sampled EDGEEnvelope

signal/ PedsotrR Linear

Pre-distoterD/A O Filter Regulator

12-Bits 12-Bit

EDGEPhase > SM ROutput signal modulated signal

Fig. 6. Open loop architecture of envelope modulator

12 bits 100 R =250k 6<

Digital l it-R O.3r- 60(2

Envelope DAC -I v 'B

Input Cfit500 Q

BlnF =2 To the Power Supply

B dB=2MHz of SMPA

J Gain=50Ri

Filter of R100 R2a 20027

Fig.7.Architecture of linearregulatorwith RC filter and DAC

Weselected BCP69[13], [14]asthe power transistor calledQ1.

BCP69 can supply with high current up to IA and be linear

voltage regulator in application. According to data sheet of

Analog Device, we selected AD8036 as the comparator called OPI inthepreliminary design. AD8036is an operation amplifier

with lowdistortion,wide bandwidthvoltagefeedbackclamp.

6. SIMULATION RESULT

For Mobile Station (MS), the requirements of EVM-rms and

EVM-peak arebelow 9% and 30%. For Base-Tranceiver Station

(BTS) EVM-rms and EVM-peak are below 7% and 22%. The

SFDRperformanceof thedigital frequency synthesizeris suitable for the up-link and down-link spectral requirement. The phase

signal word-length also contributes spurs and phase noise and

affects the EVM and the signal spectrum. In this paper we simulate the finiteword-length

(J)

effect of thephase signalwith the EVM measurement and spectral mask requirement. The

performancesummaryis in Table 2.

Table2. Simulation result and EVM measurement. J-bits EVM-rms EVM-peak Spectral requirement

9-bits 0.028% 0.094% No(Spursat-66dBc) 10-bits 0.014% 0.046% No(Spurs at -74dBc)

11-bits

0.007% 0.018% No (Spurs at -79dBc)

12-bits 0.003% 0.011% Yes(Spurs at -81dBc)

Fromthe Table 2, we can see that the errorsproduced bythe

phase quantization areverysmall for the word-length higherthan 9-bits. But the spectrum of the

SIFJpM(t)

signalis notexactlybelow

the spectralmask. Especiallyfor BTS-mask, the requirement of

the mask is more stringent than MS-mask. It is conservative to choose J=12-bit in our design. The simulation is based on the architecture of thepolartransmitter in the ADS environment. The

-simulation results show the performance of the polar transmitter system for EDGE in the condition of PA nonlinear model. Because of thenonlinearity,weadoptedthepre-distortionmethod

to linearize the PA.Fig.8 shows the simulationblock of nonlinear model withpredistorter.The finalsignal spectrumis shown inFig.

9 and canmeet the spectral requirementfor BTS-mask and

MS-mask.

Sampled EDGEenvelope

Fig ./ ultio oltaer inear

aM-to-AM |Nninear model| Sampled

EDGEphase RFOutput signal

sg |DcFonvenrtderP |>

Fig.

8. Simulation block of

polar

transmitter with nonlinear model and with

predistorter

ED

-D

Fig. 9. The final spect

7. IMPLEMEN

The proposed DSP engine is

CMOSprocesswith lP6Mtech

10.Thesummaryof the circuiti

8. CONCLUSION

In this paper, we propose a DSP engine for the polar transmitter. The engine is realized by the CORDIC and DDFS techniques. In the digital phase modulator we adopt the LS algorithm. We also apply MAC technique in our DDFS architecture to reduce the hardware complexity and decreasethe carryripple problem of the direct polynomial implementation. We adopt the architecture of linear regulator in the envelope

modulator design. The open loop architecture is suitable for mobile handset and wideband modulation scheme. The chip implementation with UMC 0.18 um CMOS process with ]P6M technology is also presented in thispaper.

ACKNOWLEDGEMENT

This work was supported by MediaTek Inc., under NTU-MTK wireless research project.

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"HE

.'.||l

[12]Wendell

B. Sander,

Stephan

V. Schell, Brian L. Sander, Polar

modulator for multi-mode cellphones, Tropian Inc., 20813 Stevens

proposedDSPengine. Creek Blvd. Cupertino, CA95014 USA.

[13]http://www.semiconductors.philips.com/acrobat/datasheets/BCP69_5.

Fig. 10. layoutof the

Table 3.Implementsurnmarvof theDSP

engine.

pdf

[14]http://www. semiconductors.philips.com/models/spicespar/data/BCP6

9.html

-616

-Technology UMC 0. 18um1P6MCMOS

Voltage 1.8V

Corelayoutarea 0.5lx0.51mm2

Chip layoutarea 1.114xl.114

mm2

SystemclockFrequency 26MHz

Power

consumption@26MHz

3.92mW

---r,7II ...

...