計畫類別： 個別型計畫
計畫編號： NSC94-2215-E-009-058-
執行期間： 94 年 08 月 01 日至 95 年 07 月 31 日
執行單位： 國立交通大學電子工程學系及電子研究所
計畫主持人： 胡樹
計畫參與人員： Robert (Shu-I) Hu
報告類型： 精簡報告
處理方式： 本計畫可公開查詢
中 華 民 國 95 年 9 月 18 日
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 3, MARCH 2006 1277
Wide-Band Matched LNA Design Using Transistor’s
Intrinsic Gate–Drain Capacitor
Robert Hu
Abstract—This paper presents the development of a wide-band
amplifier with matched input impedance and low noise tem-perature over 10–20 GHz. Here, the novel wide-band feedback mechanism provided by the transistor’s intrinsic gate–drain capacitor will be analyzed in detail with both the derived input reflection coefficient and noise temperature of the resulting circuit confirmed by their simulated counterparts. It is thus clear why by fine tuning its output loading impedance and source inductance, a transistor’s input reflection coefficient and noise temperature can be greatly improved over broad bandwidth. To demonstrate the feasibility of this novel approach, a wide-band low-noise amplifier (LNA) is designed and characterized. A bandwidth broadening mechanism using double feedback is also proposed for the future design of matched ultra-wide-band LNA.
Index Terms—Input matching, low-noise amplifier (LNA), noise
parameters, noise temperature, wide-band.
I. INTRODUCTION
W
IDE-BAND low-noise amplifiers (LNAs) have been a critical component in communication industry [1]–[3] and different scientific fields such as the very noise-sensitive radio-astronomy instrumentation where the typical LNA circuit has single-ended transistors in cascade [4]–[6]; LNAs with com-plicated input tuning circuits, which result in the inevitable in-coming signal loss are, therefore, not suitable for astronomical receivers. With this type of cascade, LNAs keep reaching even higher frequency and wider bandwidth, but what is less explored is an accurate and satisfactory account, beyond the scope of sim-ulation or specsim-ulation, of how the matched input impedance can be achieved over wide bandwidth [7]–[13].On the Smith chart in the intended frequency range, a typ-ical input reflection coefficient contour of the wide-band LNA is a loop surrounding the zero point where a small en-closed area is preferred; while that of the narrow-band LNA is a trajectory passing through the zero point at one specific fre-quency point (Fig. 1). As has been well studied, in the narrow-band design where the impact of the intrinsic feedback, i.e., the Miller effect, can be suppressed using cascode circuit configu-ration, it is the combination of external source and gate induc-tors with the transistor itself that brings in the desired matched input impedance [14]–[16]. By replacing these inductors with
Manuscript received November 11, 2005. This work was supported in part by the National Aeronautics and Space Administration under Grant NAG5-9493 and by the National Science Council, R.O.C., under Contract NSC 94-2215-E-009-058.
The author is with the Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, R.O.C. (e-mail: shuihushuihu@ yahoo.com).
Digital Object Identifier 10.1109/TMTT.2006.869703
Fig. 1. Typical input reflection-coefficient contours on the Smith chart of both the wide- and narrow-band LNAs.
Fig. 2. Transistor circuits with matched input impedance over wide bandwidth where the dotted box contains the transistor model. (a) An output loadingC is sufficient for rendering wide-band matchedS when a simplified transistor model is employed. (b) AdditionalR andL need to be added when a more sophisticated transistor model is used.
some more complicated matching circuits, such as a high-order bandpass ladder filter, wider bandwidth can indeed be achieved [17]–[19]. However, the more complicated this passive impedance matching circuit is, the higher the resulting ampli-fier’s noise temperature will be, as the accumulated input signal loss can no longer be neglected, especially if the substrate is a lossy one like silicon.
Contrary to the straightforwardness of the conventional narrow-band and its extended wide-band circuit configurations, some mathematical manoeuvring are needed in analyzing this novel wide-band input matching mechanism. A useful first step is with a simplified transistor model where only the transconductance , the gate–source capacitor , and the gate–drain capacitor are involved, as shown in Fig. 2(a). The output loading circuit is assumed to be a capacitor , which is legitimate since the transistor, especially the first-stage one, in the LNA does not need to have its output loading impedance equal to 50 . Since is much larger than ,
Fig. 3. Simulated input reflection coefficients and noise temperatures of the transistor and its wide-band circuit. (a) Curve 1 corresponds to S of the single transistor with 50- output loading impedance; curve 2 is the S of the intended wide-band transistor circuit with externalR ; C ; and L . (b)T of the single transistor and its wide-band counterpart, both with 50-generator impedance.
this circuit’s input admittance can be calculated as
(1) which is a capacitor in parallel with a resistor. An external source inductor can then be added to remove the imaginary part of , thus rendering a frequency-independent matched input impedance [20].
However, the above reasoning cannot reflect the real LNA design work since it neglects the role played by the intrinsic drain resistor , which has a finite value in the case of high electron-mobility transistor (HEMT) [21]–[23]. In fact, the tran-sistor used in designing this paper’s 10–20-GHz LNA has 68-drain resistance. With finite-value , simulation reveals that it is not simply a pure output capacitor, but an output loading circuit plus a source inductor , like that in Fig. 2(b), that brings in a matched input impedance for the transistor cir-cuit over wide bandwidth. Here, subscript denotes feedback to stress these three components’ respective impact on the input reflection coefficient.
In Fig. 3, the simulated and matched of both the tran-sistor and its corresponding wide-band circuit are displayed. Curve 1 is from the transistor itself that has fF,
fF, mS, and , and the drain
temperature is set to 2300 K. Curve 2 is for the wide-band circuit that has an external source inductor pH con-nected to the transistor, and the transistor now has an output loading circuit with and fF. Simulation also reveals that , once added, suppresses the combined effect of and , and thus results in an almost constant noise tem-perature over wide bandwidth. Also, it is mainly and that bring upon the intended small input reflection coefficient at low frequency; as frequency increases, it is predominantly and that help in the lowering of . Since no external re-sistor appears at its input, this matched wide-band circuit tends to be low noise. Useful though the simulation is, no insight as to why it works that way can be extracted from this empirical approach.
Fig. 4. Proposed wide-band circuit can be decomposed into a resistive-loading circuit at high frequency and a capacitive-loading circuit at low frequency. (a) The resistive-loading circuit with R as its output loading. (b) The capacitive-loading circuit withC as its output loading. The external source inductorL is retained in both circuits.
Relevant equations will be developed below to explain the simulated results and how the wide-band mechanism works, followed by the implementation of a wide-band LNA. A band-width broadening mechanism suitable for ultra-wide-band LNA design is then proposed. Since any gain variation of the input transistor can always be compensated in the following stages of the LNA, and the impact of the transistor’s gain degradation on the overall noise temperature is only secondary when com-pared with the transistor’s directly contributed noise, gain per-formance will not be addressed in this paper.
II. INPUTMATCHINGANALYSIS
To facilitate the input-matching analysis, the wide-band cir-cuit configuration needs to be decomposed into two sub-circir-cuits like that of Fig. 4: one is with resistive output loading , which accounts for the high-frequency response of the original circuit; the other one is with capacitive output loading , which is used to explain the original circuit’s low-frequency be-havior. The external source inductor exists in both cases.
If both and can be neglected, input impedance of the resistive-loading circuit will be
(2) where it is assumed that the impedance of is much larger than that of , which is usually the case in designing an am-plifier circuit. This expression can be best understood as that: the induced current flowing through inductor will generate a voltage that is in phase with the input current and, therefore, contributes a value of to the input resistance. Conceptually this interpretation is correct, but nu-merically it is inaccurate because of the omission of and . The impact of is that it will increase the effective input capacitance and, thus, reduces the amount of generated by ; while the finite-value will degrade the transcon-ductance and, hence, lowers the induced current flowing through . A better approximation for the input impedance is
HU: WIDE-BAND MATCHED LNA DESIGN USING TRANSISTOR’S INTRINSIC GATE–DRAIN CAPACITOR 1279
Fig. 5. Input reflection coefficient of the resistive-loading transistor circuit. (a) On the Smith chart, curves 1 and 2 correspond to the circuit withL = 200 and38 pH, respectively. The solid curves are the simulated results; the dashed curves are the calculated ones using (3). (b) The sameS expressed in decibels versus gigahertz.
with the degradation factor defined as
(4) In deriving (3), it is assumed
(5) and the leakage current flowing through is much smaller than the induced drain current. Of course, the matching fre-quency for , i.e., , is very high if not infinite. For the transistor under discussion, the required for matching only the real part of the input impedance will be a mere 38 pH using (2), and 200 pH if (3) is adopted. As expected, simu-lated results justify the choice of the latter one. Fig. 5 shows the input reflection coefficient from 0.1 to 20 GHz of the resis-tive-loading transistor circuit: the solid curves are the simulated
results where curve 1 has and pH and
curve 2 has and pH; the dashed curves
are the calculated counterparts using (3). The high-frequency discrepancy between the solid and dashed curves is due to the assumption, i.e., (5), used in deriving the close-form expression for input impedance. If an external inductor is inserted to the input of the transistor circuit, a matched input impedance can be obtained at some finite-value frequency point; in this paper’s proposed wide-band circuit, however, this input inductor has been taken away.
To facilitate the analysis of the capacitive-loading circuit, the induced current source needs to be converted into the induced voltage source , as in Fig. 6(a). Here, is the ad-mittance looking into the branch and is the impedance looking into the branch. If the induced current is much larger than the current flowing through either or , the loop current can be approximated as
(6)
Fig. 6. Variations of the capacitive-loading circuit used to facilitate the derivation ofZ . (a) To find out the circuit’s input impedance, values of Y and Z , which are indicated by the arrows, need to be derived first. (b) The equivalent circuit from the input impedance’s point-of-view where R ; C ; L come from Y , while R ; C ; L are from Z .
Thus, the admittance looking into the branch is
(7) with
(8) Likewise, the impedance into the branch is
(9) with
(10) With knowledge of and , input impedance of the capaci-tive-loading circuit can be easily found out as follows:
(11) From the input point-of-view, the capacitive-loading circuit can be rearranged such as that of Fig. 6(b). The critical components are those on the branch, while the other two shunt branches offer some modifications, as can be verified through simulation. In Fig. 7, the solid curve is the simulated result with
Fig. 7. Calculated and simulated input reflection coefficient for the capacitive-loading circuit. (a) On the Smith chart, dashed curve 1 is the calculated result using (11), solid curve 1 is its simulated counterpart, and dashed curve 2 is the calculated one usingR ; L ; C of (8) only. (b) The same results expressed in decibels versus gigahertz.
Fig. 8. Simulated input reflection coefficient of the transistor circuit with different values ofR . (a) On the Smith chart, curves 1–5 correspond to R = 0; 20; 40; 60, and 80 , respectively, while C andL are held constant at 475 fF and 200 pH. (b) The same simulated results in decibels versus gigahertz.
fF and pH, dashed curve 1 is the cal-culated counterpart using (11), dashed curve 2 is the calcal-culated result using only , and while all the other circuit com-ponents are neglected. The matching frequency can thus be ap-proximated as [24]
(12) With the discussed component values, the calculated frequency using (12) is 4.79 GHz and is very close to the simulated one. The 3-dB bandwidth can also be calculated accordingly.
Since the resistive-loading circuit is matched at high fre-quency while the capacitive-loading circuit is matched at comparatively low frequency, the composite -loaded circuit is deemed to be matched over a wide bandwidth: it degenerates into the -loaded circuit at low frequency, thus matched, and becomes the -loaded circuit at high fre-quency and matched again. Now the wide-band input matching mechanism can be soundly explained. With a series
used as the transistor’s output loading circuit while an inductor is connecting its source to ground, Fig. 8 shows the simu-lated input reflection coefficient of this transistor circuit. Here,
curves 1–5 have and , respectively,
Fig. 9. Simulated input reflection coefficient of the wide-band transistor circuit with different values ofL . (a) On the Smith chart, curves 1–5 correspond to L = 0; 100; 200; 300, and 400 fF, respectively, while C andR are held constant at 475 fF and 40. (b) The same simulated results in decibels versus gigahertz.
and all five curves are with fF and pH.
Clearly, curve 3 presents the most desired wide-band charac-teristic. As for curve 2, its hook-shaped on the Smith chart resembles the circled input reflection coefficient contour of a typical wide-band LNA.
Fig. 9 concerns the impact on of the source inductor :
curves 1–5 are with pH,
respec-tively, and all have fF and . Though it
is curve 3 that is most coveted, other values of retain, to a certain degree, the wide-band characteristic, as tends to be running flat at high frequency. This suggests that what is most critical to a wide-band transistor circuit is the value of its output loading impedance.
III. NOISETEMPERATUREANALYSIS
For a transistor with and at temperature
, its noise temperature can be expressed in terms of the generator impedance or the generator
admit-tance as
(13) Thus, the increase with frequency of the noise temperature comes mainly from and, to a lesser extent, from . By using an input inductor to mitigate the capacitive effect, noise temperature of a narrow-band transistor circuit can be greatly reduced at one frequency point.
To derive the noise-temperature expression for the wide-band circuit, its output loading needs to be replaced by a short circuit. Since the input noise temperature of a two-port cir-cuit is a function of its generator impedance, but not its output loading impedance, this short-circuit arrangement is legitimate with the additional advantage of simplifying the derivation pro-cedure. To avoid the mathematical entanglement while retain the underlying physics, capacitor will be omitted here.
First, the relationship between the output current and noise current , which is generated by at temperature , has to be constructed, as indicated in Fig. 10(a). Since
HU: WIDE-BAND MATCHED LNA DESIGN USING TRANSISTOR’S INTRINSIC GATE–DRAIN CAPACITOR 1281
Fig. 10. Schematics used for noise-temperature derivation. (a) Schematic used to derive the output short-circuitI from theR -accompanying noise currentI . (b) Schematic used to obtain the equivalent generator noise voltage V from I .
the voltage on , which is the gate voltage minus the source voltage, is (14) with (15) Thus, (16) Now this has to be transformed to its equivalent input noise voltage , which is generated by at temperature , as shown in Fig. 10(b). Since
(17) then
(18) Following the thermodynamic definition, the noise voltage and noise current per unit bandwidth will be [25]
(19) where is the Boltzmann’s constant. Thus,
(20)
Fig. 11. Simulated and calculated noise temperatures of the wide-band transistor circuit with 50- generator impedance. (a) The solid curves are the simulatedT with curves 1–5 corresponding to circuit with external source inductorL = 0; 50; 100; 150, and 200 fF, respectively; the overlapping dashed curves are the calculated counterparts using (20). (b) The solid curves are the same simulatedT ; the dashed curves are the calculated results using (22), which is itself a rough approximation.
with
(21) When the generator impedance is 50 , i.e., , a rough yet informative approximation is retaining the first three items of while setting to one; therefore,
(22) It is now clear that the inclusion of the source inductor , even of small value, brings in the inductive , thus leveling the noise-temperature curve. Fig. 11(a) shows the simulated and calculated noise temperatures with 50- generator impedance: solid curves 1–5 correspond to the simulated results with
, and pH, respectively; the dashed curves are their calculated counterparts using (20). Validity of the rough approximation is confirmed in Fig. 11(b) where the solid curves are again the simulated results; the dashed curves are the cal-culated ones using (22). The reason why a large at high frequency tends to pull down to 0 K is because, in this ex-treme case, the lower end of the drain resistor becomes floating; thus, noise current can no longer reach the output loading circuit and be counted as effective noise.
IV. WIDE-BANDLNA DESIGN ANDCHARACTERIZATION
As a demonstration of the newly proposed input-matching method, a wide-band LNA using Raytheon’s metamorphic HEMT fabrication process is designed and measured. The constituting transistor is displayed in Fig. 12(a) and has its gate split into four fingers, each 0.1- m wide and 50- m long. Its -parameters, as measured on-wafer at room temperature, are shown in Fig. 12(b) where the solid curves have bias condition
of V and mA and the dashed curves have
Fig. 12. Raytheon transistor and itsS-parameters measured on-wafer. (a) In this photograph, the wide air-bridges are connecting the source to the ground on top and bottom. (b) In the measuredS-parameters, the solid curves correspond toV = 1:0 V and I = 12 mA; the dashed curves are with V = 0:6 V and I = 12 mA.
Fig. 13. Impact of the gate bias resistor on the circuit’s noise temperature. (a) A thin-film resistor (TFR) can be used for the transistor’s gate bias. (b) Noise temperature of the transistor circuit with different gate bias schemes employed.
are less than 1 A. Once extracted [26], parameters corre-sponding to the solid curves are used in this paper’s discussion of wide-band input matching.
One concern in designing the wide-band LNA is about the implementation of the gate bias circuit, especially that of the first-stage transistor since it will directly affect the circuit’s noise performance. For a narrow-band LNA operating at the millimeter-wave frequency range, a grounded quarter-wave transmission line can be used since it behaves like an open circuit for the incoming signal [27]. However, the required quarter-wave line is too large to be implemented into the intended 10–20-GHz circuit chip; one viable option is using a large resistor, which is intrinsically wide-band and can be low loss. For a gate bias resistor , the increased noise
tem-perature due to its thermal noise is ,
where is the ambient temperature. With 50- generator impedance, a 600- gate bias resistor contributes at least 24 K, to say nothing of the incoming signal loss.
Since in the real circuit a lumped resistor has to be realized as a thin-film resistor, as in Fig. 13(a), its parasitic shunt capac-itance will inevitably deteriorate the LNA’s noise performance. Fig. 13(b) compares the noise impact of different gate bias schemes: curve 1 is without any gate bias and is omitted; curve 2 now has included, but still has no gate bias circuit; curve 3 has , and an ideal lumped 600- resistor is used for gate bias; curve 4 adds an additional 40-fF parasitic capacitor in parallel with this 600- lumped resistor; curve 5 replaces
Fig. 14. Layout of the 10–20-GHz matched LNA. This three-stage circuit, with transistors numbered 1–3, has dimension of 20002 750 2 100 m and is fabricated by Raytheon.
Fig. 15. Schematic of the 10–20-GHz matched LNA. The resistance is in ohms and the capacitance is in femtofarads. Here,S andS are the input reflection coefficients into circuits indicated by their respective arrows. The air bridge indicated can be removed using a needle probe, thus allows the gate of the first-stage transistor to be separately biased.
the lumped resistor and its parasitic capacitor with a 600-thin-film resistor that is 5- m wide and 500- m long with 6- /square sheet resistivity; curve 6 takes a different approach by using an ideal 2000- m bond wire for gate bias. With the goal of minimizing the bias circuit’s noise impact, the off-chip scheme offers the best result. If out-of-band low-frequency is also desired to be small, this long bond wire’s other end can be connected to a 50- resistor without increasing much in-band noise.
The 10–20-GHz LNA is a three-stage amplifier with common drain and gate biases, and is fabricated by Raytheon. It has di-mensions of 2000 750 100 m , as in Fig. 14, where color shading have been inverted to highlight the constituting com-ponents. Fig. 15 shows the schematic of this LNA where the capacitance is in femtofarads and the resistance is in ohms. The indicated air bridge on the gate of the first stage can be removed using a needle probe, thus allows the first-stage transistor to be biased off-chip. and are the input reflection co-efficients looking into the indicated direction. Compared with the 100- /square thin-film resistivity provided by TRW (now NGST), the 6- /square resistivity in this Raytheon fabrication process, though suitable for applications preferring a small tem-perature coefficient, tends to arouse more noise.
The drain bias circuit of the first-stage transistor is composed of a rectangular spiral inductor and a 30- resistor; drain bias cir-cuits of the second and third stages have their respective induc-tors realized using narrow transmission lines. This approach not
HU: WIDE-BAND MATCHED LNA DESIGN USING TRANSISTOR’S INTRINSIC GATE–DRAIN CAPACITOR 1283
Fig. 16. Measured and simulatedS and S of the LNA on-wafer at room temperature. The two darkened solid curves are the measured results; the other curves, as solid, dashed, and dotted, are the simulated ones. Another set of simulatedS , where the input bond wire is taken into account, has also been included in this figure.
only tapers the gain curve, but also renders an output impedance less reactive. The inclusion of the 30- resistor on each drain branch, though slightly increasing the circuit’s power dissipa-tion and noise temperature, ensures a negative (in decibels) at very low frequency and, therefore, unconditional stability. The 30- drain resistors on the second and third stages are further split into 10- and 20- ones, which, when combined with large bypass capacitors, form low-pass filters and shore up the signal isolation along the common drain bus.
The first-stage transistor has it source connected to ground, i.e., the 100 100 m via pad, by way of a 110- m-long trans-mission line, which can be viewed as the aforementioned inductor. The source of the second (and also the third) tran-sistor is directly connected to its two adjacent ground pads so the via’s inductive effect can be reduced and, thus, boosts the circuit’s gain response at high frequency. To have a matched output impedance, an 18- resistor is added. Since the LNA already has a large , this resistor-caused gain loss can be tol-erated and its noise contribution is also small.
The simulated and measured results of this circuit on-wafer at room temperature are presented in Fig. 16. Here, the darkened solid curves are the results measured on-wafer with V,
mA, V, and A, and the
testing power of the vector network analyzer is dBm; the other curves are the simulated results where three transistor models, extracted from different wafers and under different bias conditions, are employed. Since during packaging bond wire 200–300- m long has to be included at the input (and also output), its impact on has to be taken into account. Fig. 17(a) shows the simulated of the LNA from 0.1 to 30 GHz without the input bond wire. Once input bond wire is added, as in Fig. 17(b), this LNA becomes perfectly wide-band matched.
As discussed in Section III, appropriate output loading impedance for the LNA’s first-stage transistor is crucial in achieving matched input impedance over wide bandwidth. Fig. 18(a) thus shows the simulated 10–20-GHz output loading
Fig. 17. SimulatedS of the LNA from 0.1 to 30 GHz. (a) There is no input bond wire in front of the circuit. (b) When input bond wire is included, the simulatedS contour will rotate clockwise.
Fig. 18. Simulated output loading reflection coefficient for the first-stage transistor from 10 to 20 GHz. (a) Total output loading reflection coefficient. (b) Two constituting reflection coefficientsS andS , which are defined in the LNA’s schematic.
reflection coefficient for the first-stage transistor and, again, three different transistor models are employed. Being on the lower half of the Smith chart, they resemble that of an cir-cuit. A further decomposition is presented in Fig. 18(b), where is the input reflection coefficient looking specifically into the second-stage transistor and resembles of a one-port circuit; is the input reflection coefficient looking into the drain bias branch and is similar to of an circuit.
After carrying out the -parameter measurement, this cir-cuit is ready to be characterized in terms of noise. As known, noise temperature of a two-port circuit can be expressed as a function of its noise parameters: minimum noise temperature
, noise ratio , and optimum reflection coefficient , which is a complex number, i.e.,
(23)
where is 290 K and is the generator
re-flection coefficient. The reason why noise ratio rather than the conventional noise resistance has been adopted is because is invariant to lossless transformation [28]. The relationship
be-tween and is
(24) where is the optimum generator admittance. For a physical two-port circuit, there is one more constraint, i.e., the value of must be larger than one, which implies the correla-tion coefficient between the two noise waves out of ports 1 and 2 cannot be larger than one [29], [30].
Fig. 19. Schematic of the transistor circuit and its simulated noise temperature with 50- generator impedance. (a) In the schematic, R is assumed to be at ambient temperature, whileR is at temperature T . (b) In the simulated T , solid curves 1–6 correspond to the transistor circuit with no L and the correlation coefficient between R -induced noise voltage and R -induced noise current is 0, 0.2, 0.4, 0.6, 0.8, and 1.0, respectively. The six dashed curves are for the transistor circuit with 200-pHL and the noise correlation coefficient is changing from 0 to 1 again.
Fig. 20. Measured and simulated noise characteristics of the LNA on-wafer at room temperature. (a) The solid curves are the measured4T N; T and T ; the accompanying dashed curves are their simulated counterparts with noise correlation coefficient changing from 0 to 1. (b) The measured and simulated 0 .
When a small gate resistor is included for better transistor modeling [31], [32], noise temperature of the transistor circuit, like that of Fig. 19(a), will now be a function of the correla-tion coefficient between the noise voltage from at tempera-ture and the noise current from at temperature . The simulated results are presented in Fig. 19(b) where the solid curves are without any , while dashed curves have a 200-pH source inductor added to the transistor. Curves 1–6 corspond to correlation value of 0, 0.2, 0.4, 0.6, 0.8, and 1.0, re-spectively. Here, is set to 1 and is assumed to be 2300 K. Due to the difficulty in carrying out noise-parameter measurement accurately down to the transistor level [33], dif-ferent (rather than one specific) values of the correlation coeffi-cient are used in the LNA’s noise simulation.
Fig. 20 shows both the measured and simulated noise charac-teristics of the LNA on-wafer at room temperature with set to 2300 K. The solid curves are the measured results with LNA biased at 36 mA and 1.1 V, and the dashed curves are the simulated counterparts with the noise correlation coefficient changing from 0 to 1, with step size equal to 0.2. It is the LNA’s small and large at 3 GHz that set the low-frequency limit in the noise measurement; the 18-GHz high-frequency measure-ment limit is imposed by the available frequency range of the
Fig. 21. Packaged LNA with the integrated circuit inside. The input and output 50- transmission lines are on the Duroid 3010 substrate. In addition to the two capacitors for drain and gate biases, a third capacitor is added at the input of the circuit for dc-blocking purpose.
Fig. 22. S-parameters and noise temperature of the packaged LNA at room temperature. (a) MeasuredS-parameters of this packaged LNA. S is below 020 dB and not displayed here. (b) Measured noise temperature with 50-generator impedance.
noise source itself. The LNA’s noise parameters, as measured on-wafer using a wide-band frequency-variation method [34], has its in-band ratio equal to 1.7, which is a rea-sonable number. The high-frequency discrepancy between the simulated and measured curves can be accounted for in terms of the slightly smaller in the simulation at high frequency. Revised modeling of the constituting components should result in more agreeing curves, thus minimizes the noise temper-ature difference. Simulated , nevertheless, shows little de-pendency on the noise correlation coefficient and is close to the measured one.
The packaged LNA is shown in Fig. 21. Both the input and output 50- microstrip lines are on a 10-mil Duroid 3010 sub-strate, which has a large dielectric constant and is easy to handle, but tends to be lossy at high frequency. The circuit is attached using silver epoxy to the gold-plated copper chassis, which is designed to have isolation better than 40 dB at 20 GHz when the amplifier circuit is not biased. Since the on-chip input capacitor has been short circuited accidentally, an external chip capacitor for dc blocking has to be added. Due to the unleveled top sur-faces of this chip capacitor and the amplifier circuit, a longer 1-mil input bond wire has to be used, and that causes the LNA’s to be matched at the slightly lower 10 and 15 GHz. A more agreeable should be obtained by using a connector-type dc-blocking capacitor at the input. Fig. 22 shows the measured -parameters and noise temperature of this packaged LNA. The
HU: WIDE-BAND MATCHED LNA DESIGN USING TRANSISTOR’S INTRINSIC GATE–DRAIN CAPACITOR 1285
Fig. 23. 100-m transistor and its corresponding double-feedback circuit configuration for ultra-wide-band application. (a) Photograph of this 100-m transistor, which has its gate split into two fingers. (b) In the double-feedback circuit configuration, an external C is added to increase the equivalent gate–drain capacitance, thus allowing a smaller transistor (such as this 100-m one) to be used.
flat 9-dB curve toward 20 GHz exhibits the typical wide-band characteristic. This LNA can be cooled down in cryostat to have ultra-low noise temperature suitable for radio-astronomy and atmospheric applications [35]–[37].
V. BANDWIDTH BROADENING FOR POTENTIAL
ULTRA-WIDE-BANDLNA DESIGN
Thus far in this paper, we have analyzed and demonstrated the feasibility of designing a matched 10–20-GHz LNA using the novel wide-band approach. Compared with the 20-GHz high end where further design iterations ensure an even smaller input reflection coefficient, much of the design challenge lies in achieving a good at 10 GHz, which is indeed the limiting factor in determining the circuit’s relative bandwidth. One may wonder whether this 10-GHz frequency point can be halved to have an ultra-wide-band 5–20-GHz LNA. Granted, the most straightforward way is using a larger transistor, probably twice the original size. Based on the wide-band theory contrived, the second approach is keeping the transistor unchanged while adding an external capacitor in parallel with the intrinsic capacitor , thus boosting the intended feedback response at low frequency. Naturally, the third approach is having a small 100- m transistor in combination with a large . Fig. 23(a) shows the 100- m transistor, which has a layout that resembles the 200- m transistor, but has the number of fingers halved from 4 to 2. It is, therefore, reasonable to assume that its intrinsic parameters can be linearly scaled from that of the 200- m one. Fig. 23(b) shows the ultra-wide-band circuit configuration with double feedback formed by and .
The simulated and of these ultra-wide-band circuits, with K, are presented in Fig. 24 where curve 1 is with a 100- m transistor and a large ; curve 2 is with a 200- m transistor and a small , and curve 3 is with a 400- m transistor and has no . Though roughly in par with curve 2, it is the double power dissipation that runs against curve 3. The reason why curve 1 has a much larger noise tempera-ture at low frequency is because is inversely proportional to [see (13)] and, thus, is inversely proportional to the size of the transistor. Parameters used in the simulation are tabu-lated in Table I where row 1 is for the 100- m transistor circuit, row 2 is for the 200- m one, and row 3 is for the 400- m one.
Fig. 24. Simulated input reflection coefficients and noise temperatures of three ultra-wide-band transistor circuits, as specified in Table I. (a)S in decibels versus gigahertz. (b) The correspondingT with 50- generator impedance.
TABLE I
THREEDIFFERENTULTRA-WIDE-BANDTRANSISTORCIRCUITS
Here the resistance is in ohms, capacitance is in femtofarads, and inductance is in picohenrys. Of course, if we want to design an LNA with even wider bandwidth, a slightly larger transistor with some moderate value of has to be contemplated given that the transistor’s parameters are difficult to manipulate sepa-rately through process techniques.
VI. CONCLUSION
In this paper, a novel feedback approach for wide-band LNA design has been suggested and analyzed in detail. Agreements between the mathematical expressions and their simulated counterparts have confirmed this approach’s validity. A 10–20-GHz wide-band LNA was then designed and charac-terized. This is the first time an accurate and thorough account of how wide-band LNA works has been carried out has been presented. The methodology proposed here will be useful for the future design of ultra-wide-band LNAs.
ACKNOWLEDGMENT
The author thanks S. Weinreb, J. Zmuidzinas, D. Miller, M. Edgar, J. Kooi, and N. Wadefalk, all with the California Institute of Technology, Pasadena, J. Ward and G. Chattopad-hyay, both with the Jet Propulsion Laboratory (JPL), Pasadena, CA, S. I. Tsai, L. Yang and T. H. Sang, all with the National Chiao Tung University (NCTU), Hsin-Chu, Taiwan, R.O.C., F. K. Y. Lo, with the National Radio Astronomy Observatory (NRAO), Charlottesville, VA, and the anonymous reviewers of this TRANSACTIONSfor suggestions and encouragement.
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Robert (Shu-I) Hu received the B.S.E.E. degree
from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1990, and Ph.D. degree from The Univer-sity of Michigan at Ann Arbor, in 2003.
From 1996 to 1999, he was with Academia Sinica, Taipei, Taiwan, R.O.C., where he was in-volved with millimeter-wave receivers. During 1999 and 2003, he was with the California Institute of Technology, Pasadena, where he was involved with millimeter-wave wide-band receiver. He is currently with the Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, R.O.C. His research interests include microwave and millimeter-wave electronics.
