Low-capacitance and fast turn-on SCR for RF ESD protection

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(1)IEICE TRANS. ELECTRON.,. VOL.E91-C,. NO.8 AUGUST 2008 1321. PAPER. Special Section on Microelectronic Test Structures (ICMTS2007). Low-Capacitance. and. Chun-Yu. LIN†,. Fast. Nonmember,. Turn-on. SCR. Ming-Dou. KER†a),. SUMMARY With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the reduced parasitic capacitance and capacitance variation, the degradation on UWB RF circuit performance can be minimized. Besides, the fast turn-on design on the low-capacitance SCR without increasing the I/O loading capacitance is investigated and applied to an UWB RF power amplifier (PA). The PA co-designed with SCR in the waffle layout structure has been fabricated. Before ESD stress, the RF performances of the ESDprotected PA are as well as that of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still keeps the performances well. key words: electrostatic discharge (ESD), low capacitance (low-C),power amplifier (PA), radio-frequency (RF), silicon-controlled rectifier (SCR), waffle layout 1.. Introduction. It has been a trend to integrate the whole radio-frequency (RF) circuits into a single chip [1], [2]. CMOS technology is the leading role to integrate RF circuits. With the scaling-down feature size and lower cost, nanoscale CMOS technology has become suitable to implement RF circuits. However, the thin gate oxide in advanced CMOS processes seriously degrades the reliability of IC products. The major reliability issue for IC products is the damage caused by electrostatic discharge (ESD). Against ESD damages, onchip ESD protection circuit must be included in IC products [3], [4]. A general concept of on-chip ESD protection for RF ICs is illustrated in Fig. 1 [5], [6]. The ESD protection devices at I/O pad and the power-rail ESD clamp circuit must be provided in RF ICs to accomplish the whole-chip ESD protection. The parasitic capacitance (CESD)of ESD protection device inevitably contributes capacitive loading to the I/O port, which will disturb the high frequency signals, induce RC delay in the signal path, and cause other degradation on the RF circuit performances [7], [8]. For a 5-GHz low-noise amplifier (LNA) in an RF receiver, a typical specification on the total input loading capacitance is in the order of 100fF, including the ESD protection device and the bond Manuscript received December 21, 2007. Manuscript revised February 29, 2008. The authors are with the Nanoelectronics. and Gigascale Sys-. tems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan. a) E-mail: [email protected] DOI: 10.1093/ietele/e91-c.8.1321 Copyright (c). 2008 The Institute. of Electronics,. for RF ESD. Member,. Fig. 1. and. A general. concept. Protection. Guo-Xuan. MENG†,. of on-chip. Nonmember. ESD protection. in RF ICs.. pad [5]. Therefore, the parasitic capacitance of ESD protection device must be minimized. The device with minimized ratio of parasitic capacitance to ESD robustness is desired.. Silicon-controlled rectifier (SCR) device had been reported as an useful RF ESD protection element [9], [10]. The SCR device has a much higher ESD robustness within a smaller device size than other ESD protection devices, such as diode, MOS, BJT, or field-oxide device, because of the low holding voltage (Vhold,about 1.5V in general bulk CMOS process) and the low joule heating (power= IESD×Vhold)of. the. SCR. device. during. ESD. stresses. [11].. With the smaller device size, using SCR as ESD protection device introduces less parasitic capacitance. To further reduce the parasitic capacitance, the layout structure of SCR device must be considered. SCR devices with wade layout structure that have the minimized ratio of parasitic capacitance to ESD robustness have been successfully verified in silicon chips [12]. With the minimized parasitic capacitance, the variation of the parasitic capacitance within ultrawide band (UWB, 3.1-10.6GHz) frequencies can also be minimized. SCR device with the minimized ratios of parasitic capacitance to ESD robustness and capacitance variation to ESD robustness is more suitable for the UWB RF applications. In this paper, the parasitic. capacitance. within UWB fre-. quencies and ESD robustness of the SCR devices with stripe and waffle layout structures have been investigated in a 0.18μm. CMOS. process.. To. improve. the. turn-on. efficiency. of. SCR devices, the fast turn-on design has also been studied. For the application of the low-capacitance and fast turnon SCR, a fully integrated UWB RF power amplifier (PA) co-designed with SCR ESD protection circuit is shown in Sect. 6.. Information. and Communication. Engineers.

(2) IEICE TRANS. ELECTRON.,. VOL.E91-C,. NO.8 AUGUST 2008. 1322. 2.. SCR-Based. 2.1. Devices. for ESD. not be increased. Besides, the modified lateral SCR can be applied with the substrate-triggered technique to improve its turn-on efficiency [15]. When trigger diffusion serves as the trigger port, an extra trigger circuit can be designed to sup-. Protection. Lateral SCR [13]. The lateral SCR device was used as the effective ESD protection device in CMOS ICs. The equivalent circuit of the lateral SCR is shown in Fig. 2(a). The lateral SCR device consists of a PNP BJT, an NPN BJT, and an N-well/P-well junction to form a 2-terminal/4-layer PNPN structure. The turn-on voltage of the lateral SCR device is dominated by the avalanche-breakdown voltage of the N-well/P-well junction,. which. could. be. as high. as. 15V. in. a 0.18-μm. CMOS. process and greater than the gate oxide breakdown voltage of MOSFET realized with thin oxide in the core circuits.. 2.2. Modified Lateral SCR [14]. In order to reduce the turn-on voltage of SCR device, the P+ or N+ trigger diffusion is added across the N-well/P-well junction in the modified lateral SCR to reduce the junctionbreakdown voltage. The equivalent circuit of the modified lateral SCR is shown in Fig. 2 (b). Because the parasitic capacitance of the lateral SCR device is mainly caused by the N-well/P-well junction, the parasitic capacitance of the modified lateral SCR device is increased due to the extra P+/N-well or N+/P-well junction contributed by the added trigger diffusion across the N-well/P-well junction. The turn-on voltage of the modified lateral SCR can be reduced to∼10V. of the. in a 0.18-μm. modified. lateral. CMOS. SCR. process,. with. and. the. the trigger. layout. diffusion. area. will. ply the trigger current to enhance the turn-on efficiency. Although the additional trigger circuit occupies some layout area, it does not add any loading effect at I/O pad, which will be discussed in Sect. 5. 2.3. Low-Voltage-Triggering. SCR [16]. The equivalent circuit of the low-voltage-triggering SCR (LVTSCR) is shown in Fig. 2(c). A short-channel NMOS device is inserted into the lateral SCR structure. The turn-on voltage of the LVTSCR is equivalent to the drain-breakdown or punch-through voltage of the inserted NMOS device. The NMOS device in the LVTSCR is parallel with the Nwell/P-well junction, so the total parasitic capacitance will become too large which is not suitable for RF applications. Other MOS-triggered SCR devices, such as gatecoupled LVTSCR, gate-grounded NMOS triggered SCR, and PMOS-trigger lateral SCR [17], [18], also have too large parasitic capacitance loading to RF circuits. 2.4. Diode-Triggered. SCR [19]. The equivalent circuit of the diode-triggered SCR is shown in Fig. 2 (d). The diode-triggered SCR employs a diode chain to trigger the PNP or NPN BJT to latch the SCR device, which has faster turn-on speed. The turn-on voltage of the diode-triggered SCR is approximately the voltage drop of the forward-biased diode chain. However, the large leakage current of the diode-triggered SCR during normal operating condition is a serious concern. Among all SCR-based devices, the lateral SCR and the modified lateral SCR devices have the lower parasitic capacitances. So, in this work, the test structures on lateral SCR and modified lateral SCR devices were studied. 3.. 3.1 (a). Test Structures tion Stripe-Structured. on SCR Devices. for RF ESD Protec-. and Waffle-Structured. SCR. (b). Figure 3 shows the device cross-sectional view of the stripe-structured SCR (SSCR) and waffle-structured SCR (WSCR). Both devices were designed with the same size of. (c). (d). Fig. 2 Equivalent circuit of (a) lateral SCR, (b) modified lateral SCR, (c) low-voltage-triggering SCR, and (d) diode-triggered SCR.. 60.62×60.62μm2.. The. SCR. devices. are. composed. of. four regions of P+/N-well/P-well/N+. The anode of the SCR device is electrically connected to P+ and N+, which are formed in the N-well. The cathode is electrically connected to N+ and P+, which are formed in the nearby Pwell/P-substrate. When a positive potential is applied between the anode and the cathode, the N-well/P-well junction is reverse-biased, so the SCR device is kept off under normal circuit operating conditions. When an ESD stress is zapped to the anode with cathode grounded, the SCR device will.

(3) LIN et al.: LOW-CAPACITANCE. AND. FAST. TURN-ON. SCR. FOR. RF ESD. PROTECTION. 1323. become highly conductive to quickly discharge ESD current due to the turn-on of latchup path [20], [21]. In the SSCR, it discharges ESD current in only two directions, whereas the WSCR discharges ESD current in four directions. Thus, the ESD robustness can be improved under the same parasitic capacitance by using the SCR with waffle layout structure. In other word, the ratio of the parasitic capacitance to ESD robustness can be minimized by realizing the SCR with waffle layout structure.. waffle-structured SCR (MWSCR). Since the large trigger diffusion increases the parasitic capacitance, the MSSCR and MWSCR were implemented with separated trigger diffusions to evaluate their ESD robustness and parasitic capacitance. The trigger diffusion areas of two MSSCR were 123.2μm2. and. 70.24μm2, devices. were. Modified SCR. Stripe-Structured. and. Waffle-Structured. These in. in. devices. a 0.18-μm. those. of. three. 264.96μm2,. the. same. shown CMOS. layout in. MWSCR. are. respectively.. Figs.. process. area 3 and. for. of 4. All 60.62×. have. experimental. been in-. vestigations.. 4.. Figure 4 shows the device cross-sectional view of the modified stripe-structured SCR (MSSCR) and the modified. and and. designed. 60.62μm2. fabricated. 3.2. 242.48μm2,. 140.48μm2,. Measured. 4.1. SCR. Device. Characteristics. Transmission Line Pulsing (TLP) Measurement. The turn-on voltage (Vturn-on),secondary breakdown current (It2), and turn-on resistance (Ron) in the holding region of the fabricated SCR devices were characterized by the TLP system. The TLP-measured I-V curves for SSCR and MSSCR are shown in Fig. 5 (a). According to the measured I-V characteristics, SSCR is turned on at about 17V. With the trigger diffusion added into the MSSCR, the turn-on voltages are reduced to about 13V. The secondary breakdown currents of all SCR devices with stripe layout structure exceed 6A, which is the limitation of TLP system used in this measurement. The TLP-measured turn-on resistance of the SSCR. (a). and. MSSCR. are. about∼1Ω.. The TLP-measured I-V curves for WSCR and MWSCR are shown in Fig. 5 (b). WSCR is turned on. (b) Fig. 3 Device cross-sectional view of (a) stripe-structured and (b) waffle-structured SCR (WSCR).. SCR (SSCR). (a). (a). (b). (b) Fig. 4. Device cross-sectional. view of (a) modified stripe-structured. (MSSCR) and (b) modified waffle-structured. SCR (MWSCR).. SCR. Fig. 5. TLP-measured. (b) WSCR and MWSCR.. I-V characteristics of (a) SSCR and MSSCR, and.

(4) IEICE. TRANS.. ELECTRON.,. VOL.E91-C,. NO.8. AUGUST. 2008. 1324. Table. * Turn-on. 1. Comparisons. voltage of CR-triggered. on measured. MSSCR. device. and MWSCR. characteristics. of SCR devices. with different. structures.. .. at about 16V, and the MWSCR are turned on at about 12V. The secondary breakdown currents of the WSCR and MWSCR all exceed 6A. The turn-on resistance of each SCR device. with. waffle. structure. results on the device devices with different 4.2. is about∼1Ω.. The. measured. characteristics of the fabricated SCR layout structures are listed in Table 1.. (a). ESD Robustness. The human-body-model (HBM) ESD robustness of the fabricated SCR devices were evaluated by the ESD simulator. All SCR devices pass the HBM ESD test (VHBM) of 8-kV, which is the measurement limitation of HBM ESD tester. In order to distinguish the ESD robustness of the SCR with stripe layout structure from the SCR with waffle layout structure, the machine-model (MM) ESD tests were. (b) Fig. 6 Layout top view with ground-signal-ground (G-S-G) pads and equivalent model of (a) including-DUT pattern and (b) excluding-DUT pattern.. greatly reduced.. is shown in Fig. 6 (b) was fabricated in the same chip. The test patterns, one including the device under test (DUT) but the other excluding the DUT, were fabricated in the same chip. The intrinsic device Y11-parameter (YDUT)can be obtained by subtracting Ypar from Ymeas, where Ymeasis the Y11-parameter of the including-DUT pattern, and Ypar is the Y11-parameter of the excluding-DUT pattern. Finally, the. 4.3. parasitic capacitance of SCR device can be extracted from the YDUTby using. performed. The MM ESD levels (VMM) of all SCR devices are within the range of 1.4-1.8kV, as listed in Table 1. Despite the MM ESD robustness of the SCR with waffle layout structure is slightly worse than that of the SCR with stripe layout structure due to the reduction of the N-well area in the waffle layout structure, the parasitic capacitance can be. Parasitic. Capacitance. Im(YDUT. In order to fit the devices for on-wafer two-port S-parameter measurement, the SCR devices were implemented with ground-signal-ground (G-S-G) pads, as shown in Fig. 6 (a). The high-frequency S-parameters were measured under the bias. of. 0.9V. (VDD/2. ing the vector parameter by using Y11= where. Z0. network. in a 0.18-μm. analyzer. can be obtained. CMOS. process). HP 8510C,. from the measured. by. us-. CESD=. (2). )/ 2πf,. where f is the operating frequency. Figure 7 shows the extracted parasitic capacitance within UWB frequencies (3.110.6GHz) of all SCR devices.. and the Y11S-parameters. 4.4. Comparison. on. Parasitic. Capacitance. and. ESD. Ro-. bustness. (1-S11)(1+S22)+S12S21 / Z0((1+S11)(1+S22)-S12S21) is the. termination. Because the SCR devices the intrinsic characteristics. resistance. , (1) and. equals. to 50Ω.. were arranged with the pads, of the SCR devices in high fre-. quency were embedded within the parasitic effects of metal interconnects and bond pads. To de-embed the intrinsic characteristics of the SCR devices, the stand-alone pad that. The ratios of the parasitic capacitance to MM ESD robustness (CESD/VMM)within UWB frequencies of all SCR devices were evaluated and compared in Fig. 8. According to the measured result, the averaged ratios of CESD/VMM of SSCR and WSCR are about 50fF/kV and 40fF/kV, respectively. The CESD/VMMratio of WSCR has a decrease of about 25% as compared with that ratio of SSCR. As to MSSCR and MWSCR, the averaged ratios of CESD/VMM.

(5) LIN et al.: LOW-CAPACITANCE. AND FAST TURN-ON. SCR FOR RF ESD PROTECTION 1325. of MSSCR and MWSCR are about 80-90fF/kV and 6075fF/kV, respectively. The CESD/VMMratios are increased with the increase of the P+ trigger diffusion area. The CESD/VMMratios of MWSCR have also a decrease of about 25%, as compared with that of MSSCR. The. variation. 10.6GHz. (ΔCESD). out structures which. of the parasitic of. the. are about. are summarized. SCR. 30-70fF in Table. capacitance with. stripe. and. and 15-50fF, 1. The. within. ratios. (ΔCESD/VMM) tures. are. SCR. in waffle. pared. within 3.1-10.6GHz of. the. compared. with. SCR in. layout. for. Fig.. 9.. to MM ESD robustness. stripe The. and. waffle. has also a significant. that of the SCR. layout. ratio(ΔCESD/VMM). in stripe. strucof. decrease. the. as com-. layout.. 3.1-. waffle. lay-. respectively of the. tance variation. 4.5. Comparison Protection. ,. among. SCR-Based. Devices. for RF ESD. capaci-. Based on the measurement results in this paper and the prior work [11], the qualitative comparisons among SCR-based devices in terms of turn-on voltage, turn-on speed, parasitic capacitance/ESD robustness, leakage current, and layout area, have been summarized in Table 2. With consideration on the merit of parasitic capacitance/ESD robustness, the proposed waffle SCR device will be a good solution for RF ESD protection. 5.. Fast Turn-on. Design. on SCR Devices. To further reduce the turn-on voltage of MSSCR and MWSCR, the P+ trigger diffusion can be treated as the trig-. Fig. 7 devices. Fig. 8. Extracted with different. Ratios. 3.1-10.6GHz. parasitic layout. of parasitic of SCR devices. capacitance. within. 3.1-10.6GHz. ger port, and the trigger current can be injected to enhance the turn-on efficiency. The equivalent circuit of the triggered MSSCR and MWSCR is shown in Fig. 10. In order to build the trigger circuit to trigger MSSCR or MWSCR without. of SCR. structures.. capacitance. to MM ESD robustness. with different. Table. layout. 2. within. Fig.. structures.. Comparisons. among. SCR-based. 9. Dependence. to MM. ESD. devices. with. devices. robustness different. of ratio of capacitance (ΔCESD/VMM) layout. structures.. for RF ESD protection.. on. variation trigger. within diffusion. 3.1-10.6GHz area. of SCR.

(6) IEICE. 1326. TRANS.. ELECTRON.,. VOL.E91-C,. NO.8. AUGUST. 2008. (a) Fig. 10. Equivalent. circuit. of triggered. MSSCR. and MWSCR.. increasing the I/O loading capacitance, the new proposed ESD protection strategy for RF ICs is shown in Fig. 11. Compared this with Fig. 1, the ESD protection devices are composed of a diode from I/O to VDD and a MSSCR or MWSCR from I/O to VSS. The trigger circuit of MSSCR or MWSCR between VDD and VSS is separated from the I/O port and not adding the I/O loading. Figure 11(a) shows the discharging path under positive-to-VSS mode (PS-mode) ESD zapping, which is a worse case of ESD events [22]. During PS-mode ESD stress, ESD current will first pass through the diode to VDD, and the trigger circuit will trigger MSSCR or MWSCR. The major ESD current will be discharged by MSSCR or MWSCR from the I/O pad to VSS. Under other ESD stress modes, including positive-to-VDD (PD-mode), negative-to-VSS (NS-mode), and negative-toVDD (ND-mode), the proposed ESD protection circuit also provides the corresponding current discharging paths with good ESD robustness, which are also shown by the dashed lines in Fig. 11. The TLP-measured I-V curves for this circuit under NS-mode ESD stresses are shown in Fig. 12, which were the I-V curves of the P-well/N-well diodes in SCRs. The I-V curve under PD-mode ESD stress was similar to the curve shown in Fig. 12, and the I-V curve for NDmode stress was the I-V curve of a triggered SCR in series with a diode. To on SCR setup to MSSCR cuit. was. demonstrate the function of the fast turn-on design devices under PS-mode stress, the experimental measure the TLP I-V characteristics of the triggered and MWSCR is shown in Fig. 13. The trigger circomposed. of. a 20-pF. capacitance. and. a 20-kΩ. re-. sistance. The RC time constant of the trigger circuit was designed in the order of 10-6-10-7s to detect ESD events. Under normal circuit operation, the trigger port of the MSSCR or MWSCR was biased at VSS to be kept off. When the ESD pulse was zapping, the trigger port was coupled to high potential by the ESD energy. Therefore, the trigger current will be injected into the trigger port by the CR trigger circuit, and the MSSCR or MWSCR will be quickly turned on. The TLP-measured I-V curves for CR-triggered MSSCR and MWSCR are shown in Figs. 14(a) and 14(b), respectively. The turn-on voltage of all CR-triggered MSSCR and MWSCR (Vturn-on*) are reduced to about 6V, as listed in Table 1. The turn-on voltages among the SCR devices under. (b). (c). (d) Fig. 11 Application of the proposed MSSCR or MWSCR devices in onchip ESD protection design for RF ICs with low-capacitance consideration, and the discharging current path under (a) PS-mode, (b) PD-mode, (c) NSmode, and (d) ND-mode ESD zapping.. different layout structures are compared in Fig. 15. The 6-V turn-on voltage of CR-triggered SCR devices is much lower than the breakdown voltage of the internal circuits in a 0.18μm. CMOS. be feasible.. process,. so. the. fast. turn-on. design. is proved. to.

(7) LIN et al.: LOW-CAPACITANCE. AND FAST TURN-ON. SCR FOR RF ESD PROTECTION 1327. Fig. 12 TLP-measured ESD stress.. I-V characteristics. of MWSCR. under. NS-mode. Fig. 15 devices. 6.. Dependence. Measurement. setup. to find I-V characteristics. of CR-triggered. diffusion. and. Design. This. section. UWB. presents with. without in. area of SCR. Fast. UWB RF PA and ESD Protection. fabricated. and MWSCR.. on trigger. 6.1. and. MSSCR. voltage. structures.. Application of Low-Capacitance SCR in RF PA. co-designed. Fig. 13. of turn-on. with different. a fully ESD. the. ESD. a. 0.13-μm. integrated. protection. circuit. CMOS. class-AB. circuit.. protection. The are. process.. Turn-on. PA. PA with. designed The. and. presented. UWB RF PA is a three-stage distributed amplifier (DA). The UWB applications cover the frequency band from 3.1GHz to 10.6GHz. The DA is intrinsically suitable for this bandwidth and widely used for PA [23]. Figure 16 shows the circuit schematic of the PA. The active core devices (M1 and M2) of each stage are in cascode topology. The cascode topology provides good voltage gain and good isolation. It also prevents drain overstress since the voltage swing may. approach. 2×VDD. at the. output. node.. The. device. size. and voltage/current bias of the cascode pair is designed to produce a particular current that gives the active core device. with. within the. a 50-Ω. loading. its operational DA. can. and optimal. for dynamic. simultaneously. load-line. its optimal range. satisfy. load-line With. a 50-Ω. resistance. such. a. conjugate. manner, match. match.. The UWB RF PA with the proposed ESD protection circuit is shown in Fig. 17. It contains a waffle-structured diode string from output (O/P) to VDD, and a MWSCR from O/P to VSS with a RC-inverter as a trigger circuit. The diode string can avoid the signals leak from O/P to. (a). VDD. since. =1.2V. in. the voltage. swing. a 0.13-μm. CMOS. may. approach. process). 2×VDD. at the. (VDD. output. node.. Besides, another set of RC-inverter-triggered SCR acts as the power-rail ESD clamp circuit to provide the discharging path between VDD and VSS. The RC time constants of the trigger circuits were designed in the order of 10-6-10-7s to detect ESD events. The capacitor of each trigger circuit was composed of a MOS capacitor and was in the area of about 1700μm2.. (b) Fig. 14 TLP-measured and (b) MWSCR.. I-V characteristics. of CR-triggered. (a) MSSCR. Under. normal. circuit. operation,. ESD. protection. circuits were all kept off. During PS-mode ESD stress, with ESD pulses zapping to O/P of the protected PA, ESD current will first flow through the diodes to VDD, and then flow into.

(8) IEICE TRANS. ELECTRON.,. 1328. Fig. 16. VOL.E91-C , NO.8 AUGUST 2008. Equivalent circuit of UWB RF PA (unprotected PA).. (a). Fig. 17. Equivalent circuit of UWB RF PA with the proposed ESD. protection circuit (ESD-protected. PA).. the RC-inverter to trigger the MWSCR. The ESD current will be discharged by the MWSCR from the O/P to VSS. Therefore, the ESD protection ability can be significantly improved. The die photos of the fabricated chips of the unprotected PA and ESD-protected PA are shown in Figs. 18(a) and 18(b), respectively.. (b) Fig. 18. 6.2. Measured. RF Performance. after. ESD. Zapping. The S-parameters of the UWB RF PA were measured by using the Agilent E8364B PNA. An Agilent E4448A spectrum analyzer and an Agilent E8257D signal generator were used to evaluate the large signal characteristics of the PA. To compare the ESD protection capability between the PA with and without ESD protection circuit, the RF performance of PA was measured again after each HBM ESD zapping.. The S21-parameter is the forward gain of the PA. The measured results of the S21 from 2 to 12 GHz of the PA without ESD protection circuit (unprotected PA) and that of the PA with ESD protection circuit (ESD-protected PA) are shown in Figs. 19(a) and 19(b), respectively. The S21 of the unprotected PA was severely degraded after HBM ESD zapping, as seen in Fig. 19(a). On the contrast, the S21 of the ESD-protected PA was still excellent matching even if the 8-kV HBM ESD test was performed (8-kV is the maximum limitation of ESD simulator). The bandwidths of the unprotected and ESD-protected PA after each HBM ESD zapping are summarized in Table 3. The averaged large tected and ESD-protected. signal power PA within. gain of the unpro3.1-10.6GHz after. Die photos of the fabricated. (a) unprotected PA and (b) ESD-. protected PA.. each HBM ESD zapping are also listed in Table 3. According to the measured data, both the bandwidth and the averaged large signal gain of the ESD-protected PA are kept fine after each HBM ESD stress, while those of the unprotected PA are seriously degraded. When the output power increases, the output swing would be compressed. The output power at 1-dB compression point (OP 1dB) can be treated as the maximum linear output power capability of the PA. Figures 20 (a) and 20 (b) show the measured results on the OP 1dB of the unprotected and ESD-protected PA, respectively. The OP 1dB of the unprotected PA was seriously degraded after HBM ESD zapping. The OP 1dB of the ESDprotected PA was not degraded even after 8-kV HBM ESD test. 7.. Conclusion. SCR. with. have. the reduced. robustness.. the The. waffle. layout. parasitic ratios. structure capacitance. of the parasitic. has under. been. verified. the same. capacitance. to ESD. to MM.

(9) LIN et al.: LOW-CAPACITANCE. AND FAST TURN-ON. SCR FOR RF ESD PROTECTION 1329. Table. 3. Bandwidth. and gain of UWB. RF PA after HBM. ESD zapping.. (a). (a). (b). (b). Fig. 19 Measured results on S21-parameter of (a) unprotected PA and (b) ESD-protected PA, after each HBM ESD zapping.. Fig. 20 Measured results of output power 1-dB compression point of (a) unprotected PA and (b) ESD-protected PA, after each HBM ESD zapping.. ESD robustness of WSCR and MWSCR have the of about 25% as compared to SSCR and MSSCR. the waffle layout structure has also been verified the variation of the parasitic capacitance within. decreases SCR with to reduce UWB fre-. quencies. Thus, SCR realized in the waffle layout structure is more suitable for on-chip ESD protection in UWB RF circuits than that realized in the stripe layout structure. Although the parasitic capacitance is increased with the added P+ trigger diffusion, the turn-on voltage can be reduced to effectively protect the RF circuits against ESD damages. The fast turn-on design on low-capacitance SCR with the waffle layout structure has also been studied and applied to the UWB RF circuit. The RF measured results have confirmed that the performance of the unprotected PA is se-. riously degraded after ESD zapping. The PA co-designed with the proposed ESD protection circuit can minimize the negative impact of ESD protection devices on RF circuit performance,. and provide. excellent. ESD robustness.. Acknowledgments. This work was supported by United Microelectronics. Cor-. poration (UMC), and National Science Council (NSC), Taiwan, under Contract of NSC 96-2221-E-009-182. References. [1] S. Voldman, ESD: RF Technology and Circuits, Wiley, New York, 2006..

(10) IEICE TRANS. ELECTRON.,. VOL.E91-C,. NO.8 AUGUST 2008. 1330. [2]. C.. Grewing,. K.. Wiesbaue, plifier. in. IEEE. Radio Voldman,. [4]. A.. Amerasekera. D. T.. for. UWB. Duvvury,. pp.. Wiley,. ESD. Puma,. in. A.. 87-90,. New. Silicon. [22]. M.-D.. ESD. Proc.. Trans.. Electron. 2004.. [23]. B.. clamp. Ballweber,. 5.5GHz. Circuits,. vol.35,. Integrated. “Whole-chip. to-VSS. 2006.. York,. Ker,. am-. power. transmitters,”. Symp.,. Devices,. G.. distributed. Circuits. and. Linten,. S.. Nakaie,. Groeseneken,. Thijs,. M.. Physical. pp.. 59-66,. M.-D.. Ker,. T.-Y.. CMOS. RF. P.. Sawada,. “RFCMOS. Int.. Symp., [6]. C.. Friedrich,. Devices, R.. CMOS no.2,. M.-D.. Jansen,. T.. ESD. and. D.. Hasebe,. Tremouilles,. W.. Decoutere,. and. S.. protection. Failure. and. Analysis. and. C.-Y.. of. Chang,. circuits,”. and. C.-M.. Lee,. LNA. with. novel. Symp.,. pp.. 204-213,. CMOS. EOS/ESD [8]. C. Richier, “Investigation 3.3V. reliability,”. Gupta,. applications. EOS/ESD [9]. pp. 231-239,. Lee,. Ong,”. design. Symp.,. pp.. [13]. Ker. charge. protection. grated. circuits,”. and. 235-249, Ker. layout. for. tronic. Test. M.-D.. T.. N.. P. Mortini, devoted. and. RF. and. to. from. Tanba,. T.. Yoshimasu,. in. standard. Lin,. Symp.,. University,. electrostatic. devices. in. Reliab.,. structure. and. Hsu, in. Electron. SCR. Int.. Jan.. ics Engineering,. no.2,. sity. Currently, Master Degree. in. waffle. input. protection. enhanced July. electrostatic. discharge. 1990.. “Substrate-triggered silicided. Devices, and. controlled. SCR. device. sub-0.25-μm. vol.50,. Chatterjee,. trical. Microelec-. 1990.. with. fully. on. ESD. no.2,. P.. rectifiers,”. Feb.. voltage. Patent. on-. process,”. 397-405,. “Low. U.S.. for. CMOS. pp.. Yang,. C.. Russ,. M.. and. K.. Verhaege, for. Proc.. EOS/ESD. M.-D.. Ker,. ESD. protection. C.-Y.. 2003.. triggering. 5,465,189,. B.. Keppens,. and. C.. for. no.3,. Nov.. pp.. Ker. generative. and. Part. vices,. vol.42,. M.-D.. Ker. ative. process. Part. II:. of. no.6,. pp.. processes,”. “Lateral. SCR. device. CMOS. Armer,. P.. for. process,”. Jozwiak,. R.. Mohn,. diode-triggered. ultra-sensitive Device. IC. Mater.. SCR. nodes. in. Reliab.,. ad-. vol.5,. 2005. Wu,. “Modeling latchup. pp.. derivation,”. 1141-1148,. Wu,. CMOS. latchup. by. June. a. positive-feedback positive. IEEE. June. pole. Electron. De-. Trans.. the. positive-feedback. a positive IEEE 1995.. transient Trans.. Electron. pole. National Taiwan,. from. the. Chiao-Tung. R.O.C.,. in 1986,. National. Chiao-Tung. Univer-. he also serves as the Director of Program in the College of Elec-. Engineering. and Computer. Science,. Na-. elevated. to. trostatic. protection. IEEE. Fellow in. 2008. with. integrated. the. citation. circuits,. and. of. “for. contributions. performance. to elec-. optimization. of. micro-systems.”. re-. transient. Guo-Xuan. Meng. received. regener-. Electronics. Engineering. and the M.S. degree. method.. ics, National. 1995.. “Modeling. evaluation,” 1149-1155,. the by. Ph. D. degrees. tional Chiao-Tung University and also as the Associate Executive Director of the National Science and Technology Program on System-on-Chip, Taiwan. He has published over 300 technical papers in the field of reliability and quality design for circuits and systems in CMOS technology in international journals and conferences. He has proposed many inventions to improve reliability and quality of integrated circuits, which have been granted with 131 US and 141 Taiwan, R.O.C., patents. His current research topics include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel applications in LCD display. He had been invited to teach or to consult on the reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC industry. Dr. Ker is a member of the Technical Program Committee and Session Chair of numerous international conferences. He was selected as the Distinguished Lecturer in IEEE Circuits and Systems Society for year 2006-2007. He also served as an Associate Editor of the IEEE Transactions on VLSI Systems. He was the President of Foundation in Taiwan ESD Association. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan, by the Junior Chamber International. In 2005, one of his patents on ESD protection design was awarded with the National Invention Award in Taiwan. Prof. Ker has been. VLSI. CMOS. C.-Y.. Quantitative. of Trans.. I: Theoretical. and. J.. of. no.6,. Avery,. controlled. CMOS. optimized. C.-Y.. process. method.. Tang,. “Speed. protection. Sept.. submicron. T.-H.. IEEE. 532-542,. L.. silicon. 2001.. Verhaege,. Trinh,. ESD. Kolluri,. 2002.. K.. technologies,”. M.-D.. vol.42,. RF. G.. triggered. shallow-trench-isolation. Dec.. Russ,. vanced. and in. 6,498,357, C.. Jozwiak,. deep. 22-31,. Chang,. Mergens,. P.. in. pp.. protection. Patent. Armer, GGNMOS. Symp.,. M.. (DTSCR). [21]. J. “GGSCR:. ESD. U.S.. [20]. Mergens,. Hsinchu,. vol.5,. device. Conf.. and. degree. Engineer-. 1988, and 1993, respectively. He is now a Full Professor with the Department of Electron-. dis-. 2007. “Efficient. 4,939,616,. K.-C.. A.. 196-199,. structure. Patent. on. IEEE. the B.S.. of Electronics. of Electronics,. inte-. CMOS. received. the M.S.. Institute. Circuits. on-chip. Mater.. Proc.. 4,896,243,. protection. Trans.. of. Duvvury,. Patent. Polgreen,. “Test. pp. C.. “Circuit. Ker. on-chip. [19]. ing and. and. Ker. the Department. CMOS. 1995.. [18]. 2000.. Ming-Dou. 2002.. Integrated. Device. protection,”. U.S.. rectifiers. 0.5-. Circuits.. proProc.. 2005.. semiconductor. [17]. integrated. J. Solid-State. T.-C.. application,”. 93-96,. SCR-based. Trans.. and. ESD. Feb.. fully. IEEE. IEEE. 1999.. Proc.. ESD. circuits. “Overview with. Structures,. U.S.. IEEE [16]. Proc.. Yu,. capacitance. pp.. RF. T.-L.. low. Frequency. Hsu,. IEEE. ESD. Rountree,. chip. Conf.,. of. Radio. C.-Y.. RF. protection,” [15]. giga-Hz. process,”. Chang,. and. Fukumi,. design. Chatterjee. R.. Juge, and strategies. CMOS. scheme. M.. K.-C.. and. scheme,” [14]. A.. 0.18μm. R.-Y.. protection. June. M.-D.. A.. NMOS. IEEE. for. technique,”. 2002.. M.-D.. pp. [12]. Allstot, “A. Jan.. 2000.. SCR. Adan,. Proc.. 31-34,. a. Circuits. “ESD. design. Zaza, protection. self-protection. A.. Hayashi,. pp.. protection. in. Peng,. Integrated. process,”. [11]. for. Higashi,. M.. D.. VLSI,”. pp. 173-183,. amplifier,”. efficient VDD-. Chun-Yu Lin received the B.S. degree from the Department of Electronics Engineering, National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 2006. He is currently working toward a Ph. D. degree at the Institute of Electronics, NCTU. His current research interests include RF circuit design and ESD protection design for RF ICs.. for. 346-354,. 2003.. K.-R.. embedded. Custom. K.. “ESD. 251-259,. Wu,. device. IEEE [10]. pp.. Y.-H.. The. tection. no.1,. with CMOS. Circuits. protection. EOS/ESD. impedance-isolation. (2GHz). Symp.,. J.-H.. and. design. submicron. Proc.. Integrated. “ESD. Proc.. P. Salome, G. Mabboux, I. on different ESD. RF. for. 2005. Chen,. integrated. Ker. RF. protection. vol.46,. distributed. 2001. [7]. ESD circuits. 2002.. Natarajan,. IEEE. optimized. Circuits and. M.. integrated. integrated. ESD:. Jeamsaksiri, G.. Waasen,. “Fully. technology,. London,. M.. S.. Sandne,. Frequency. S.. Wiley,. C.. CMOS. [3]. [5]. Winterberg,. and. Devices,. 2007,. Chiao-Tung. respectively.. and ESD protection. University,. His current design. the B.S. degree Hsinchu,. research. for RF ICs.. from. the Department. from the Institute Taiwan,. interests. include. R.O.C.,. of. of Electronin 2006. RF circuit. and. design.

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