A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system

A

2V

CMOS

Programmable Pipelined Digital Differential

Matched Filter for DS-CDMA System

-

A T +

She-Hwa Yen and Chorng-Kuang Wang

I/P - b, b, .... b,

Department of Electrical Engineering National Taiwan University, Taiwan. R.0.C

bn+l Abstract

This paper presents a 2V DS-CDMA programmable

digital matched filter with a differential and pipelined

structure. Differential PN (Pseudo-Noise) code scheme is

adopted to reduce the number of multiplication and summations (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves the hardware and the power, but also improves the operation speed, which makes PDDMF more suitable, for personal communication at high speed and low power requirements than the conventional approach. The PDDMF implemented in a

0.6um CMOS technology is clocked at 2.5 MHz and

consumes 1.6mW from a single power supply 2V. Introduction

Direct Sequence Code Division Multiple Access (DS-

CDMA) has been successfully applied to many low

bandwidth wireless communication systems. In these systems, matched filter is usually employed for code acquisition since it offers significant advantages in the speed of synchronization. However, the primary limitation of the conventional digital filters is the number of stages that is

greatly associated with the hardware implementation of multiplication and accumulation. This paper describes a CMOS low-voltage low-power programmable pipelined digital matched filter that employs a differential PN code

scheme [I] in order to reduce hardware complexity and hence

the chip size and power.

Pipelined Digital Differential Matched Filter The total number of multiplication and summation in conventional matched filter M, is 2'-1, where r is the order of the PN code polynomial generator. Obviously as the number

of stages increases, the number of M&S significantly

increases. A differential PN code scheme (Fig.1) [l] is employed to avoid this problem. The output hnction of the

matched filter can be described as :

f~(T)=[b~+lXo+b~X,+b~-lX2 . . . + b 2 X ~ - l + b l X ~ ] + f ~ ( T - l ) =[-aNxO+( aN-aN. I)x I+(aN- I-aN-2)+.

. . .

+ a , x ~ ] + f ~ ( T - 1)

where b, for i from 0 to N + l is the multiplication coefficients

of the PDDMF, and a, is the PN code coefficient of the

conventional matched filter. Since the coefficients a, of the

U

The pipelined structure, simplifies the summation circuit of the multiple input, and improves the speed of the PDDMF. Furthermore, the throughput of the PDDMF is independent of the PN code length.

Circuit Architecture

Fig.2 is a block diagram of the PDMMF for DS-CDMA receiver. The 9.6kHz input data are spread into a signal band 1.2288MHz in IS-95 based CDMA systems. Because the

SNR of the spreading signal

is

... !

*-I-

F i g 2 The programmable PN coefficients of PDDMF

decision matched filter is adopted to increase the reliability of data detection. The multiplication coefficients of PDDMF are user programmable by the PN code generator. The PN code generated by the PN generator is first stored in the PN code register. Then the differential encoder generates the multiplication coefficients according to the differential PN code scheme. It controls the M&S cell for coefficients setting. The new coefficient will be 0 when adjacent Coefficients are the same value.

1 l l l l

reset

cin

Fig.3 shows the circuit of two's complementary M&S with coefficient 2 and -2. The input data d l , d2, d3, d4 multiply the coefficient first. If the multiplication coefficient bi is -2 the pins neg and cin are set to logic 1 ; otherwise they will be set to logic 0 for bi=2.

Power Supply Technology Tap Length SamplesKhip PN Code Rate Clock Rate Power Consumption Chip Area

z

m

r-L

*

6

r

l

9 Bits Ripple Adder

U I I U

Fig.3 Circuit design for M&S cell circuit of 2 and -2

A 9 bits ripple adder performs the summation in the final.

Ripple adder is chosen for low power rather than for high speed. The chip-rate of the PN code used is 1.2288MHz, the tap length is 16 and the number of multiplication coefficients for bi= ai-ai-l = 0 is 7. Only 8 coefficients need to be multiplied, rather than 32 coefficients in the conventional 16

taps length matched

filter

time. The number of M&S is reduced to 1/4. Fig.4 is the die photo of the programmable 16 taps length PDDMF. It is fabricated in a 0.6um CMOS technology. The chip area is

1500um by 1500um.

Experimental Results

Fig.5 shows the testing results of the PDDMF by IMS logic master, The testing mode can be programmed either automatic self-test mode or normal mode. In self-test mode, the input PN code and coefficients are generated automatically. Under normal test mode whose input code is fed externally, while filter coefficients are chosen by user. In both modes, the auto-correlation results can track the PN sequence correctly.

, / I