行政院國家科學委員會專題研究計畫成果報告

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行政院國家科學委員會專題研究計畫成果報告

座標旋轉原理演算法應用於二維及三維特殊信號處理器之晶片設計與製作(I)

研究成果報告(精簡版)

計畫類別：個別型

計畫編號： NSC 98-2221-E-216-037-

執行期間： 98 年 08 月 01 日至 99 年 07 月 31 日執行單位：中華大學微電子工程學系

計畫主持人：宋志雲共同主持人：辛錫進

計畫參與人員：碩士班研究生-兼任助理人員：郭志軒博士班研究生-兼任助理人員：柯律廷

報告附件：出席國際會議研究心得報告及發表論文

處理方式：本計畫涉及專利或其他智慧財產權，1 年後可公開查詢

中華民國 99 年 09 月 03 日

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行政院國家科學委員會補助專題研究計畫 ■ 成果報告

□期中進度報告

座標旋轉原理演算法應用於二維及三維特殊信號處理器之晶片設計與製作(I)

計畫類別：■個別型計畫 □整合型計畫計畫編號：NSC 98－2221－E－216－037 執行期間： 98 年 8 月 1 日至 99 年 7 月 31 日執行機構及系所：中華大學微電子工程學系

計畫主持人：宋志雲共同主持人：辛錫進

計畫參與人員：柯律廷郭志軒

成果報告類型(依經費核定清單規定繳交)：■精簡報告 □完整報告

本計畫除繳交成果報告外，另須繳交以下出國心得報告：

□赴國外出差或研習心得報告

□赴大陸地區出差或研習心得報告

■出席國際學術會議心得報告

□國際合作研究計畫國外研究報告

處理方式：除列管計畫及下列情形者外，得立即公開查詢

█涉及專利或其他智慧財產權，█一年□二年後可公開查詢

中華民國 99 年 8 月 25 日

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(一)中英文摘要及關鍵詞:

中文摘要

本研究使用混合座標旋轉原理設計及製作直接數位頻率合成器。此一設計之架構為無乘法器，包含小量之唯獨記憶體( -位元)以及疊流資料路徑，所產生無寄生動態範圍超過84.4 dBc。系統晶片由台積電

4 16× m

.18μ

0 1P6M CMOS製程設計，並且在Xilinx陣列處理器上實體模擬。證明此一以混合座標旋轉原

理為基礎之直接數位頻率合成器適合由超大型積體電路製作，在硬體成本，功率消耗以及無寄生動態範圍上都有具備優勢。

關鍵詞: 直接數位頻率合成器，混合座標旋轉原理，系統晶片，陣列處理器，無寄生動態範圍。

英文摘要

This research presents a hybrid COordinate Rotation DIgital Computer (CORDIC) algorithm for designs and implementations of the direct digital frequency synthesizer (DDFS). The proposed multiplier-less architecture with small ROM ( -bit) and pipelined data path provides a spurious free dynamic range (SFDR) of more than 84.4 dBc. A SoC (System on Chip) has been designed by

4 16×

m .18μ

0 1P6M CMOS, and then emulated on the Xilinx FPGA. It is shown that the hybrid CORDIC-based architecture is suitable for VLSI implementations of the DDFS in terms of hardware cost, power consumption, and SFDR.

Key-Words: - DDFS, hybrid CORDIC, SoC, FPGA, SFDR.

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(二) 報告內容:

1. Introduction

The direct digital frequency synthesizer (DDFS) plays a key role in many digital communication systems. Fig.

1 depicts the conventional DDFS, which consists mainly of phase accumulator, sine/cosine generator, digital-to-analog converter, and low-pass filter. The sine/cosine generator as the core of DDFS is usually implemented by using a ROM lookup table; with high spurious free dynamic ranges (SFDR) comes a large ROM lookup table [1]. In order to reduce the size of the lookup table, many techniques were proposed [1]-[4].

The quadrant compression technique can reduce the ROM size by 75% [2]. The Sunderland architecture is to split the ROM into two smaller ones [3], and its improved version known as the Nicholas architecture results in a higher ROM-compression ratio (32:1) [4]. In [5], the polynomial hyperfolding technique with high order polynomial approximation was used to design DDFS. In [6]-[10], the angle rotation algorithm was used to design quadrature direct digital frequency synthesizer/complex mixer (QDDSM).

COordinate Rotation DIgital Computer (CORDIC) is a well known arithmetic algorithm, which evaluates various elementary functions including sine and cosine functions by using simple adders and shifters only.

Thus, CORDIC is suitable for the design of high-performance chips with VLSI technologies. Recently, the CORDIC algorithm has received a lot of attention to the design of high-performance DDFS [11]-[14], especially for the modern digital communication systems.

In this research, we propose a hybrid CORDIC algorithm for the VLSI implementation of DDFS. The remainder of this paper proceeds as follows. In section 2, the proposed hybrid CORDIC algorithm is presented. In section 3, the hardware implementation of DDFS is described. The performance analysis is given in section 4. Conclusion can be found in section 5

2. The Hybrid CORDIC Algorithm

In this section, the hybrid CORDIC algorithm is proposed, and based on which, a low-power and high-SFDR DDFS can be developed.

2.1 The modified scaling-free CORDIC algorithm

In order to reduce the number of CORDIC iterations, the input angle can be divided into encoded angles by using the modified Booth encoding (MBE) method [15]. Specifically, let

ψ

denote the input angle represented by

) 1 ( )

1

( .... ( 1)2

2 ) 1 ( 2 ) 0

( ⁻ + ⁻ ⁺ + + − ⁻ ⁻

= f ^p f ^p f w ^w

ψ

(1)

where f(i)∈{0,1}, w is the word length of operands, and 1 3

) 585 . 2

( ⎥⎥⎤= ≤ ≤ −

⎢⎢⎡ −

w i w p

. The MBE decomposition of

ψ

is as follows.

∑

⁻

=

=⁽ ¹⁾^/²

2 /

) (

w p i

β i

ψ (2) where the encoded angle:

β

(i)=

ρ

(i)2⁻ⁱ with

ρ

(i)∈{−2,−1,0,1,2}. As sin

β

(i) and cos

β

(i) can be approximated by

i i

i

i)≅ ( )= ( )2⁻ (

sin

β β ρ

(3)

) 1 2 ( 2 2

2 ) ( 2 1

) 1 (

) (

cos ≅ − i = − i ⁻ ⁱ⁺

i

β ρ

β

(4)

we have

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⎥⎦

⎢ ⎤

⎣

⎡

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

−

= −

⎥⎦

⎢ ⎤

⎣

⎡ + +

+

−

− +

−

) (

) ( 2

) ( 1 2

) (

2 ) ( 2

) ( 1 ) 1 (

) 1 (

) 1 2 ( 2 )

1 2 ( 2

i y

i x i

i

i i

i y

i x

i i

ρ ρ

ρ

(5)

i i

i z i

z( +1)= ()−

ρ

( )2⁻ (6) Fig. 2 shows the proposed architecture for the modified scaling-free CORDIC arithmetic, in which, eight shifters, two CSAs, two CLAs, two latches, and four MUXs are used; the shifters and MUXs are to determine

ρ

(i).

2.2 The modified scaling-free radix-8 CORDIC Algorithm

By using the modified angle recoding method [15]-[16], the input angle

ψ

can be divided as follows.

∑

⁻

=

−

= ^w¹ ()tan−¹2

p i

i i

φ

ψ

(7) where

φ

(i)∈{0,1}, and is the word length. The CORDIC iteration is therefore represented as w

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡

= −

⎥⎦

⎢ ⎤

⎣

⎡ + +

−

) (

) ( 1

2 ) (

2 ) ( 1

) 1 (

i y

i x i

i i

y i x

i

φ

(8)

i i

i z i

z( +1)= ()−

φ

()tan⁻¹2⁻ (9) Let . By using the Taylor series expansion, the absolute difference between

and is given by

{

0,1,2

;

3 − ∈

= n c c i

) 2 ( tan 2^c ⁻¹ ⁻³ⁿ

}

tan⁻¹(2⁻⁽³ⁿ⁻^c⁾)

Λ +

⋅

=

−

= ⁻¹ ⁻⁽³ ⁻ ⁾ ⁻¹ ⁻³ 2⁻³⁽³ ⁻⁾ 3

2 1 tan 2 2

tan ⁿ ^c ^c ⁿ ⁿ ^c

ς

(10)

where is the remaining terms of the difference betweenΛ tan⁻¹(2⁻⁽³ⁿ⁻^c⁾)and . Thus, we have 2^ctan⁻¹(2⁻³ⁿ)

3 2 3

2⁻³⁽³ⁿ⁻^c⁾ = ⁻³ⁱ

ς

≅ (11) For w-bit operands,

ς

can be ignored in the following sense

−w

ς

≤ 2 (12) Based on equations (11) and (12), we have

i w

− −

3 ≤ 2 2 ³

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w i+log 3≥

3 ₂ (14)

3 3

3 log 3

3

log₂ w ₂ w

i w ⎥⎥⎤≅

⎢⎢⎡ −

− =

≥ (15)

As a result, when 3

i> w, three consecutive terms of equation (7) can be integrated into a single term as

follows:

) 2 ( tan ) 3 ( ) 2 ( tan ) 1 3 ( ) 2 ( tan ) 2 3

( n− ⁻¹ ⁻⁽³ⁿ⁻²⁾ +

φ

n− ⁻¹ ⁻⁽³ⁿ⁻¹⁾ +

φ

n ⁻¹ ⁻⁽³ⁿ⁾

φ

) 2 ( tan ) 2 ) 3 ( 2 ) 1 3 ( 2 ) 2 3 (

( n− ⋅ ²+ n− ⋅ ¹+ n ⋅ ⁰ ⁻¹ ⁻³ⁿ

=

φ φ φ

) 2 ( tan )

(n ⁻¹ ⁻³ⁿ

=

ϕ

(16)

where

φ

(⋅)∈{0,1}, and therefore

ϕ

(n)∈{0,1,2,L,7}. It follows that the resulting radix-8 CORDIC algorithm is represented as

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡

⋅

= −

⎥⎦

⎢ ⎤

⎣

⎡ + +

−

) (

) ( 1

2 ) (

2 ) ( ) 1

) ( 1 (

) 1 (

3

8 y i

i x i

i i i K

y i x

i

ϕ

(17)

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i i

i z i

z( +1)= ( )−

ϕ

()tan⁻¹2⁻³ (18)

2 / 1 6 2 8(i) (1 (i)2 ⁱ)

K = +

ϕ

⁻ (19) The scaling factor K₈ is given by

⎡ ⎤

) (

1 3 /

8

8 K i

K

w i

p

∏

i ⁻

=

= (20)

It can be shown that the scaling factor turns out to be equal to 1 when the input angle is less than , and moreover, if the input angle is less than , equation (18) can be rewritten as [19]

2

2⁻^w/ 3

2⁻^w/

i i

i z i

z( +1)= ()−

ϕ

( )2⁻³ (21) Fig. 3 depicts the proposed architecture for the modified scaling-free radix-8 CORDIC arithmetic. In which, six shifters, two CSAs, two CLAs, and two latches are used; the shifters and switches are to determine the radices for computations. Note that the number of processors is reduced, and system throughput is increased at the cost of hardware complexity.

2.3 The proposed hybrid CORDIC Algorithm

The input angle Ω can be decomposed into a higher-angle Ω_H and a lower-angle represented as

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ΩL

⎡ ⎤

⎡ ⎤ ⎡ ⎤

∑

⁺ ⁻ ⁻

=

−

⋅ +

− −

=

+

= Ω + Ω

=

Ω ^/² ⁽ ⁾^/³ ¹

2 /

) 4 / ( 3 1 1

2 /

0

2 ) ( )

( ^u ^w^u

u i

w i u u

i L

H ρ i2⁻²ⁱ ϕ i

where w is the word length with the first u bits being the most significant bits; and are computed by using the modified scaling-free CORDIC algorithm and the modified scaling-free radix-8 CORDIC algorithm, respectively. For computation efficiency, the determination of u is as follows: 1) u must be an odd number to satisfy the MBE method, and 2)

ΩH Ω_L

2

u≥ w under the scaling-free constraint. Thus, we have

⎪⎪

⎩

⎪⎪

⎨

⎧

+

= +

+

= +

+

= +

+

= +

=

3 4 3

2

2 4 1

2

1 4 1

2

0 4 1

2

n w if , n

u (23)

Based on the above equation, the minimum iteration number of the proposed hybrid CORDIC algorithm can be obtained as shown in Fig. 4. The computations of x(i) and y(i) are therefore as follows.

For ⎥⎥⎤

⎢⎢⎡

<

≤ 2

2 i u

p ,

) ( 2 ) ( ) ( 2

) ( ) ( ) 1

(i x i ² i ⁽⁴ ¹⁾x i i ² y i

x + = −

ρ

⁻ ⁱ⁺ −

ρ

⁻ⁱ (24)

) ( 2 ) ( ) ( 2

) ( ) ( ) 1

(i y i ² i ⁽⁴ ¹⁾x i i ² y i

y + = −

ρ

⁻ ⁱ⁺ +

ρ

⁻ⁱ (25)

For ⎥⎥⎤

⎢⎢⎡ −

⎥⎥+

⎢⎢ ⎤

<⎡

⎥⎥≤

⎢⎢ ⎤

⎡

3 4

2

u w i w

u ,

⎡ ⎤ ()

2 ) ( ) ( ) 1

(i x i i ¹ ³⁽ ^/⁴ ¹⁾y i

x + = −

ϕ

^u⁻⁺^⋅ⁱ⁻^w ⁺ (26)

⎡ ⎤ ()

2 ) ( ) ( ) 1

(i y i i ¹³⁽ ^/⁴ ¹⁾x i

y + = +

ϕ

^u⁻⁺^⋅ⁱ⁻^w ⁺ (27) 3. Hardware Implementation of the Proposed DDFS

In this section, the DDFS implemented by using the hybrid CORDIC algorithm is presented. Fig. 5 shows

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the 16-bit DDFS architecture consisting mainly of phase accumulator, phase calculator, and sine/cosine generator, which is different from the conventional architecture. It is noted that the accumulated error in the sine/cosine generator is to be corrected by using the 4×16-bit correction table. Take into account DAC technology, hardware cost and practical applications, the word length of the propose DDFS is set to 16-bit.

The hybrid CORDIC-based sine/cosine generator with recursively accumulated angle

ϑ

_in is given by

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡ −

⎥=

⎦

⎢ ⎤

⎣

⎡ + +

) (

) ( cos

sin

sin cos

) 1 (

i y

i x i

y i x

in in

ϑ ϑ

ϑ

(28)

where ₁₆

2 2

π

ϑ

_in =Δ_acc , and Δ_accis an integer number. (29) For convergence, the input angle of the scale-free CORDIC algorithm is restricted as follows:

8 2 1

1 4

≅

<

∑

^w⁻ ⁻ⁱ

ϑ

in (30) From the above two equations, we have

2 1304 2¹⁶ ⋅ <

=

Δ_acc

ϑ

_in

π

(31) The architecture for the sine/cosine generator is shown in Fig. 5. In which three modified scaling-free CORDIC arithmetic units (MCORDIC-Type A) and two modified scaling-free radix-8 CORDIC arithmetic units (MCORDIC-Type B) are used.

The chip is synthesized by the TSMC 0.18 m

μ

1P6M CMOS cell libraries [17]. The layout view of the proposed DDFS is shown in Fig. 6. The core size obtained by the Synopsys^® design analyzer is . The power consumption obtained by the PrimePower^® is 6.05 mW with a clock rate of 100MHz at 1.8V. The tuning latency is 8 clock cycles. All the control signals are internally generated on-chip. The chip provides both high throughput and low gate count.

612 2

612×

μ

m

4. Performance Analysis of the Proposed DDFS

The number of correcting points versus the SFDRs with different ’s in the proposed DDFS is shown in Fig. 7. Due to trade-off between hardware cost and system performance, the correcting circuit with 16 points is implemented in the proposed DDFS. In case of 16-bit word length, as shown in Fig. 8, the high-frequency SFDR is 169.7 dBc, respectively. The mid-frequency SFDR of sine and cosine is 122 dBc, as shown in Fig. 9, respectively. The low-frequency SFDR of sine and cosine is 85.06 dBc, as shown in Fig. 10, respectively. As a result, the SFDR is above 85 dBc. Table 1 shows various comparisons of the proposed DDFS with other methods in [11] and [13]. As one can see, the proposed DDFS is superior in terms of SFDR, hardware cost, and power consumption.

) / (F_s F_o

5. Conclusion

The hybrid CORDIC-based multiplier-less DDFS architecture with small ROM and pipelined data path has been implemented. A SoC designed by 1P6M CMOS has been emulated on Xilinx XC2V6000 FPGA. For 16-bit DDFS, the SFDR of sine and cosine using the proposed architecture are more than 85.06 dBc.

Simulation results show that the hybrid CORDIC-based approach is superior to the traditional approach to the design and implementation of DDFS, in terms of SFDR, power consumption, and hardware cost. The 16-bit DDFS is a reusable IP, which can be implemented in various processes with efficient uses of hardware resources for trade-offs of performance, area, and power consumption.

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References:

[1] J. Vankka, “Methods of mapping from phase to sine amplitude in direct digital frequency synthesis,”

IEEE Proceedings of the Frequency Control Symposium, June 5-7 1996, pp.942-950.

[2] S. C. Yi, K. T. Lee, J. J. Chen, C. H. Lin, "A low power efficient direct digital frequency synthesizer based on new two-level lookup table,” IEEE Canadian Conference on Electrical and Computer Engineering 2006, May 2006, pp.963-966.

[3] D. A. Sunderland, R. A. Srauch, S. S. Wh arfield, H. T. Peterson, C. R. Cole, "CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications,” IEEE Journal of Solid-State Circuits, Vol.19, No.4, August 1984, pp.497-506.

[4] H. T. Nicholas, H. Samueli, B. Kim, "The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects," IEEE 42nd Annual Frequency Control Symposium, June 1-3 1988, pp.357-363.

[5] D. D. Caro, E. Napoli, A. G. M. Strollo, ”Direct digital frequency synthesizers with polynomial hyperfolding technique,” IEEE Transactions of Circuits and Systems-II: Express Briefs, Vol.51, No.7, July 2004, pp.337-344.

[6] D. Fu, A. N. Willson, Jr. “A high-speed processor for digital sine/cosine generation and angle rotation” in Proc. 32nd Asilomar Conf. Signals, Systems and Computers, Vol.1 1998, pp.177-181

[7] A. Torosyan, D. Fu, A. N. Willson, Jr, “A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS” IEEE Journal of Solid-State Circuits, Volume 38, Issue 6, June 2003 pp. 875 – 887 [8] S. Cheng, K. Zhang, S. Cao, X. Zhou, D. Zhou, "A 2.4-GHz ISM Band Delta-Sigma Fractional-N

Frequency Synthesizer with Automatic Calibration Technique," WSEAS Transactions on Circuits and Systems, Issue 10, Vol.7, pp.859-868, Oct. 2008

[9] I.JIVET, B.DRAGOI, "Performance Analysis of Direct Digital Synthesizer Architecture with Amplitude Sequencing," WSEAS Transactions on Circuits and Systems, Issue 1, Vol.7, pp.1-6, Jan 2008.

[10] J. W. Hong, C. L. Hou, C. M. Chang, S. T. Cheng , H. Y. Su, "Current or/And Voltage-Mode Quadrature Oscillators With Grounded Capacitors and Resistors Using FDCCIIs," WSEAS Transactions on Circuits and Systems, Issue 3, Vol.7, pp.129-138, Mar 2008.

[11] A. Madisetti, A. Y. Kwentus, A. N. Willson Jr, "A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range,” IEEE Journal of Solid-State Circuits, Vol.34, No.8, August 1999, pp.1034-1043.

[12] E. Grayver, B. Daneshrad, “Direct digital synthesis using a modified CORDIC,” IEEE International Symposium on Circuits and Systems (ISCAS '98). Vol.5, May 1998, pp.241-244.

[13] C. Y. Kang, E. E. Swartzlander Jr., “Digit-pipelined direct digital frequency synthesis based on differential CORDIC,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.53, No.5, May 2006, pp.1035-1044.

[14] T. Y. Sung, H. C. Hsin, “Design and simulation of reusable IP CORDIC core for special-purpose processors,” IET Computers & Digital Techniques, Vol.1, No.5, Sept. 2007, pp.581-589.

[15] Y. H. Hu, S. Naganathan, “An angle recoding method for CORDIC algorithm implementation,” IEEE Transactions on Computers, Vol.42, No.1, January 1993, pp.99-102.

[16] T. B. Juang, S. F. Hsiao, M. Y. Tsai, “Para-CORDIC: parallel CORDIC rotation algorithm,” IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol.51, No.8, August 2004, pp.1515-1524.

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[17]“TSMC 0.18 CMOS Design Libraries and Technical Data, v.3.2,” Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, and National Chip Implementation Center (CIC), National Science Council, Hsinchu, Taiwan, R.O.C., 2006.

Table I Comparison with previous works

CORDIC Based DDFS Madisetti [11] 1999 Swartzlander [13] 2006 This work [Sung, Hsin & Ko]

Process (

μ

m) 1.0 0.13 0.18

Core Area (mm²) 0.306 0.176 0.35 0.15 0.375

Maximum Sampling Rate (MHz) 80.4 85.7 1018 1052 100

Power Consumption (mw) 40.602 20.8251 350 143 6.056

Power Consumption (mw/MHz) 0.505 0.243 0.343 0.134 0.06

SFDR (dB_c) 81 62.1 90 60 85.06

Output Resolution (bits) 16 16 16 11 16

Tuning Latency (clock cycles) 16 16 -- -- 8

Phase increment

Phase

accumulator

+

sin/cos generator Digital to analog Low pass filiter converter

Fig. 1 The conventional DDFS architecture

1 2−

→ⁱ ²→ⁱ⁺¹

CSA

CLA

CSA

CLA

xin y_in

xout y_out

Latch Latch

MUX

→i ²^→ⁱ⁻¹ ²^→ⁱ⁺¹

MUX

→i

MUX MUX

−1

→ⁱ

−1

→ⁱ

Fig. 2 The proposed architecture of modified scaling-free CORDIC arithmetic for computing (MCORDIC-Type A)

θH

(10)

−2

→ⁱ →ⁱ⁻¹ →ⁱ

CSA

CLA

CSA

CLA

xin yⁱⁿ

xout y_out

Latch Latch

→i

−1

→ⁱ

−2

→ⁱ

Fig. 3 The architecture of modified scaling-free radix-8 CORDIC arithmetic for computing θ_L(MCORDIC-Type B)

R e g

R e g Phase

Accumulator

Phase Calculator

Operation Radix Generator

Pipeline CORDIC

Array

M U X

R e g 16

[15:12]

16 16

4

16 3*7 3*7

16

Sin output

Cos output

Δacc

Sine/Cosine Generator

4

16

16 4

Δacc

AccumulatorΔ^acc

16

Correc- tion Table 16*2

Fig. 4 The 16-bit DDFS architecture

MCORDIC Type A Iteration I

Register ϑin

16

16 16

MCORDIC Type A Iteration II

MCORDIC Type A Iteration III

MCORDIC Type B Iteration IV

MCORDIC Type B Iteration V Operation Radix Generator

3 3 3 3 3

3*7

Register

Error Correcting Phase

MUX

Cos Output

Sin Output Correcting

Table

4

16*2 16*2

Fig. 5 The architecture of sine/cosine generator (Theϑ_inis an accumulated angle)

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Fig. 6 The layout view of the proposed DDFS

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7

-220 -200 -180 -160 -140 -120 -100 -80 -60

X: 4 Y: -89.69

X: 4 Y: -168.6

X: 4 Y: -84.42

Correction Points log2(N)

SFDR (dBc)

Fs/Fo=32768 Fs/Fo=16384 Fs/Fo=128

0 5 10 15 20 25 30

-200 -150 -100 -50 0

X: 17 Y: -169.7

Normalizrd Frequency

SFDR (DB)

Fig. 7 Plot of the number of correcting points versus SFDRs with different (F_s/F_o)’s

Fig.8 High-frequency SFDR using the proposed 16-bit DDFS (169.7 dBc)

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0 20 40 60 80 100 120 140 160 -200

-180 -160 -140 -120 -100 -80 -60 -40 -20 0

X: 17 Y: -122

SFDR (DB)

Fig.9 Mid-frequency SFDR using the proposed 16-bit DDFS (122 dBc)

-20 0 20 40 60 80 100 120 140

-250 -200 -150 -100 -50 0

X: 17 Y: -85.06

SFDR (DB)

Fig.10 Low-frequency SFDR using the proposed 16-bit DDFS (85.06 dBc)

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國科會補助專題研究計畫成果報告自評表

請就研究內容與原計畫相符程度、達成預期目標情況、研究成果之學術或應用價值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）、是否適合在學術期刊發表或申請專利、主要發現或其他有關價值等，作一綜合評估。

1. 請就研究內容與原計畫相符程度、達成預期目標情況作一綜合評估

■ 達成目標

□ 未達成目標（請說明，以 100 字為限）

□ 實驗失敗

□ 因故實驗中斷

□ 其他原因說明：

2. 研究成果在學術期刊發表或申請專利等情形：

論文：■已發表 □未發表之文稿 □撰寫中 □無專利：□已獲得 ■申請中 □無

技轉：□已技轉 □洽談中 ■無其他：（以 100 字為限）

3. 請依學術成就、技術創新、社會影響等方面，評估研究成果之學術或應用價值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）（以 500 字為限）

本研究使用混合座標旋轉原理設計及製作直接數位頻率合成器。此一設計之架構為無乘法器，包含小量之唯獨記憶體( -位元)以及疊流資料路徑，所產生無寄生動態範圍超過 84.4 dBc。系統晶片由台積電

4 16×

.18μm

0 1P6M CMOS 製程設計，並且在 Xilinx 陣列處理器上

實體模擬。證明此一以混合座標旋轉原理為基礎之直接數位頻率合成器適合由超大型積體電路製作，在硬體成本，功率消耗以及無寄生動態範圍上都有具備優勢。非常適用於無線網路之晶片。

未來將進一步研究硬體架構的精簡，高頻之無寄生動態範圍提升以及雜訊比(PSNR)的改進。

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國科會補助計畫衍生研發成果推廣資料表

日期：99年8月25日

國科會補助計畫

計畫名稱：座標旋轉原理演算法應用於二維及三維特殊信號處理器之晶片設計與製作(I)

計畫主持人：宋志雲

計畫編號：NSC 98-2221-E-216 -037 領域：積體電路及系統設計

（中文）高無寄生動態範圍及無乘法器之直接數位頻率合成器

研發成果名稱

（英文）High-SFDR and Multiplierless Direct Digital Frequency

Synthesizer

成果歸屬機構

^中華大學

發明人 (創作人)

宋志雲

（中文）使用混合座標旋轉原理設計及製作直接數位頻率合成器。此一設計之架構為無乘法器，包含小量之唯獨記憶體(16X4 - 位元)以及疊流資料路徑，所產生無寄生動態範圍超過 84.4 dBc。

系統晶片由台積電 1P6M CMOS 製程設計，並且在 Xilinx 陣列處理器上實體模擬。證明此一以混合座標旋轉原理為基礎之直接數位頻率合成器適合由超大型積體電路製作，在硬體成本，功率消耗以及無寄生動態範圍上都有具備優勢。本合成器於高頻條件下, 有更高之無寄生動態範圍，達到169.7dBc。比較現存的直接數位頻率合成器，其有非常好的無寄生動態範圍。

技術說明

（英文）This research presents a hybrid COordinate Rotation DIgital Computer (CORDIC) algorithm for designs and implementations of the direct digital frequency synthesizer (DDFS). The proposed multiplier-less architecture with small ROM (16X4 -bit) and pipelined data path provides a spurious free dynamic range (SFDR) of more than 84.4 dBc.A SoC (System on Chip) has been designed by 1P6M CMOS, and then emulated on the Xilinx FPGA. It is shown that the hybrid CORDIC-based architecture is suitable for VLSI implementations of the DDFS in terms of hardware cost, power consumption, and SFDR. In case of 16-bit word length, the high-frequency SFDR is 169.7 dBc.As one can see, the proposed DDFS is superior in terms of SFDR, hardware cost, and power consumption.

產業別

^晶片設計

技術/產品應用範圍

無線數位高頻寬網絡設備及晶片

技術移轉可行性及預期效益

可轉移晶片設計原始碼及相關實驗資料，改進相關設備之性能。

註：本項研發成果若尚未申請專利，請勿揭露可申請專利之主要內容。

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國科會補助專題研究計畫項下出席國際學術會議心得報告

計畫編號

NSC 98-2221-E-216-037

計畫名稱

座標旋轉原理演算法應用於二維及三維特殊信號處理器之晶片設計與製作(I)

出國人員

姓名宋志雲服務機構及職稱

中華大學微電子工程學系教授

會議時間

99 年 4 月 11 日至

99 年 4 月 13 日

會議地點

^{中國杭州市}

會議名稱

⁹

th WSEAS International Conference on Instrumentation, Measurement, Circuit and Systems

發表論文題目

(1) Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter (2) Folded Reconfigurable Architecture for VLSI Wavelet Filter (3) A Novel Linear Array for Discrete Cosine Transform

一、參加會議經過

發表論文三篇，9^th WSEAS International Conference on Instrumentation, Measurement, Circuit and Systems並

與與會人士討論，並擔任兩場討論會之Session Chair。本研討會為 WSEAS 之重要研討會，歷史

悠久，至少有二十年以上之歷史。本人發表之三篇論文接獲選為最佳論文(Best Papers)，並邀請增加篇幅在其期刊WSEAS Transactions on Circuits and Systems (EI)登出。本人發表之論文，引起大家極大興趣，會中廣泛討論內容。

二、與會心得

此一研討會為WSEAS 重要研討會，與會人士均為一時之選。會中可認識相關領域的領導人物，機會

難得。論文如獲最佳論文，延伸後將獲得該學會之期刊(EI)刊登。與相關人士討論在台灣主辦此一國際研討會之可能性。

三、考察參觀活動(無是項活動者略)

四、建議

鼓勵在教學之學校教師投稿此一研討會，並組Special Session，因為有指標性意義。同時爭取 WSEAS

類似權威性研討會之主辦權，以增加台灣之國際學術地位。

五、攜回資料名稱及內容

研討會之論文光碟及紙本論文集。

(16)

附錄一:本計畫發表之相關論文

國際期刊:

1. Tze-Yun Sung, Hsi-Chin Hsin, Yi-Peng Cheng, “Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems”, Digital Signal Processing, vol. 20, no. 2, 2010, pp. 511-527. (SCI) NSC 98-2221-E-216 -037.

2. Tze-Yun Sung, Yaw-Shih Shieh, Hsi-Chin Hsin, “An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm”, Mathematical Problems in Engineering, vol. 2010, Article ID 185398, 21 pages, doi:10.1155/2010/185398, 2010. (SCI), NSC 98-2221-E-216 -037.

3. Yaw-Shih Shieh,Tze-Yun Sung (通訊作者),Hsi-Chin Hsin, “A Novel Linear Array for Discrete Cosine Transform”, WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Issue 5, Volume 9, May 2010, pp.

335-346. (EI) , NSC 98-2221-E-216 -037.

4. Tze-Yun Sung,Hsi-Chin Hsin, “Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter”, WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Issue 5, Volume 9, May 2010, pp. 347-357. (EI) , NSC 98-2221-E-216 -037.

5. Tze-Yun Sung,Hsi-Chin Hsin, “Multiplierless, Reconfigurable Folded Architecture for VLSI Wavelet”, WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Issue 5, Volume 9, May 2010, pp. 358-368. (EI) , NSC 98-2221-E-216 -037.

國內期刊:

1. Tze-Yun Sung, Hsi-Chin Hsin, Sheng-Dong Chang, “Reconfigurable VLSI Architecture for 9/7-5/3 Discrete Wavelet Transform”, Chung Hua Journal of Science and Engineering (中華理工學刊), vol. 7, no. 3, Sept. 2009, pp. 63-70. NSC 98-2221-E-216 -037.

2. Tze-Yun Sung, Hsi-Chin Hsin, Tsuo-Fu Wang, “VLSI Reconfigurable Architecture for 9/7-5/3 Lifting-Based Discrete Wavelet Transform”, Chung Hua Journal of Science and Engineering (中華理工學刊), vol. 7, no. 4, Dec. 2009, pp. 63-70. NSC 98-2221-E-216 -037.

國際研討會:

1. Yaw-Shih Shieh, Tze-Yun Sung(通訊作者), Hsi-Chin Hsin, “A Novel Linear Array for Discrete Cosine Transform” 9th WSEAS Int. Conference on INSTRUMENTATION, MEASUREMENT, CIRCUITS and SYSTEMS, April 2010, pp. 27-32. (EI) , NSC 98-2221-E-216 -037.

2. Tze-Yun Sung, Hsi-Chin Hsin, “Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter,” 9th WSEAS Int. Conference on INSTRUMENTATION, MEASUREMENT, CIRCUITS and SYSTEMS, April 2010, pp. 15-20. (EI) , NSC 98-2221-E-216 -037.

3. Tze-Yun Sung, Hsi-Chin Hsin, “Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter,” 9th WSEAS Int. Conference on INSTRUMENTATION, MEASUREMENT, CIRCUITS and SYSTEMS, April 2010, pp. 21-26. (EI) , NSC 98-2221-E-216 -037.

4.

國內研討會:

1. Yaw-Shih Shieh, Tze-Yun Sung(通訊作者), Hsin-Chin Hsin, “A Novel VLSI Linear Array for Discrete

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Cosine Transform and Its Inverse,” 8^th Conference of Microelectronics Technology and Applications (2010-CMTA), Kaohsung City, Taiwan, May 2010, pp.241-250. NSC 98-2221-E-216 -037.

2. Tze-Yun Sung, Hsin-Chin Hsin, “Multiplierless, Folded Reconfigurable Architecture for VLSI Wavelet Filter,” 8^th Conference of Microelectronics Technology and Applications (2010-CMTA), Kaohsung City, Taiwan, May 2010, pp. 251-258. NSC 98-2221-E-216 -037.

(18)

國科會補助專題研究計畫項下出席國際學術會議心得報告

計畫編號

NSC 98-2221-E-216-037

計畫名稱

座標旋轉原理演算法應用於二維及三維特殊信號處理器之晶片設計與製作(I)

出國人員

姓名宋志雲服務機構及職稱

中華大學微電子工程學系教授

會議時間

99 年 4 月 11 日至

99 年 4 月 13 日

會議地點

^{中國杭州市}

會議名稱

⁹

th WSEAS International Conference on Instrumentation, Measurement, Circuit and Systems

發表論文題目

(1) Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter (2) Folded Reconfigurable Architecture for VLSI Wavelet Filter (3) A Novel Linear Array for Discrete Cosine Transform

一、參加會議經過

發表論文三篇，9^th WSEAS International Conference on Instrumentation, Measurement, Circuit and Systems並與

與會人士討論，並擔任兩場討論會之Session Chair。本研討會為 WSEAS 之重要研討會，歷史悠久，

至少有二十年以上之歷史。本人發表之三篇論文接獲選為最佳論文(Best Papers)，並邀請增加篇幅在其期刊WSEAS Transactions on Circuits and Systems (EI)登出。本人發表之論文，引起大家極大興趣，

會中廣泛討論內容。

二、與會心得

此一研討會為WSEAS 重要研討會，與會人士均為一時之選。會中可認識相關領域的領導人物，機會難

得。論文如獲最佳論文，延伸後將獲得該學會之期刊(EI)刊登。與相關人士討論在台灣主辦此一國際研討會之可能性。

三、考察參觀活動(無是項活動者略)

四、建議

鼓勵在教學之學校教師投稿此一研討會，並組Special Session，因為有指標性意義。同時爭取 WSEAS

類似權威性研討會之主辦權，以增加台灣之國際學術地位。

五、攜回資料名稱及內容

研討會之論文光碟及紙本論文集。

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Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter

Tze-Yun Sung¹ Hsi-Chin Hsin²

1Department of Microelectronics Engineering Chung Hua University

707, Sec. 2, Wufu Road, Hsinchu City 300-12, Taiwan bobsung@chu.edu.tw

2Department of Computer Science and Information Engineering National United University

1, Lien-Da, Miao-Li, 36003, Taiwan hsin@nuu.edu.tw

Abstract: - In this paper, the high-efficient and reconfigurable lined-based architectures for the 9/7-5/3 discrete wavelet transform (DWT) based on lifting scheme are proposed. The proposed parallel and pipelined architectures consist of a horizontal filter (HF) and a vertical filter (VF). The critical paths of the proposed architectures are reduced. Filter coefficients of the biorthogonal 9/7-5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware In the proposed architectures, all multiplications are performed using less shifts and additions. The proposed reconfigurable architecture is 100% hardware utilization and ultra low-power. The proposed reconfigurable architectures have regular structure, simple control flow, high throughput and high scalability. Thus, they are very suitable for new-generation image compression systems, such as JPEG-2000.

Key-Words: - Reconfigurable architecture, 9/7-5/3 discrete wavelet transform (DWT), horizontal filter (HF), vertical filter (VF), lifting scheme.

1 Introduction

In the field of digital image processing, the JPEG-2000 standard uses the scalar wavelet transform for image compression [1]; hence, the two-dimensional (2-D) discrete wavelet transform (DWT) and IDWT has recently been used as a powerful tool for image coding/decoding systems.

Two-dimensional DWT/IDWT demands massive computations, hence, it requires a parallel and pipelined architecture to perform real-time or on-line video and image coding and decoding, and to implement high-efficiency application-specific integrated circuits (ASIC) or field programmable gate array (FPGA). At the kernel of the compression stage of the system is the DWT.

Swelden proposed using the biorthogonal 9/7 wavelet based on lifting scheme for lossy compression [2]. The symmetry of the biorthogonal 9/7 filters and the fact that they are almost orthogonal [2] make them good candidates for image compression application. Gall and Tabatai proposed using the biorthogonal 5/3 wavelet based on lifting scheme for lossless compression [3]. The goal of the proposed architectures is to embed the 5/3 DWT computation into the 9/7 DWT computation. The coefficients of the filter are quantized before hardware implementation; hence, the multiplier can

be replaced by limited quantity of shift registers and adders. Thus, the system hardware is saved, and the system throughput is improved significantly.

In this paper, we proposed a high-efficient architecture for the even and odd parts of 1-D DWT based on lifting scheme. The advantages of the proposed architectures are 100% hardware- utilization, multiplier-less, regular structure, simple control flow and high scalability.

The remainder of the paper is organized as follows.

Section 2 presents the lifting-based 2-D discrete wavelet transform algorithm, and derives new mathematical formulas. In Section 3, the high-efficient and reconfigurable architecture for the lifting-based 2-D DWT are proposed. Finally, comparison of performance between the proposed reconfigurable architecture and previous works is made with conclusions given in section 4.

2 The Lifting-Based 2-D DWT Algorithm

Usually the Lifting-based DWT requires less computation compared to the convolution-based approach. However, the savings depend on the length of the filters. During the lifting implementation, no-extra memory buffer is required because of the

Proceedings of the 9th WSEAS Int. Conference on INSTRUMENTATION, MEASUREMENT, CIRCUITS and SYSTEMS

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in-place computation feature of lifting. This is particularly suitable for the hardware implementation with limited available on-chip memory. Many papers proposed the algorithms and architectures of DWT [3]-[11], but they require massive computation. In 1996, Sweldens proposed a new lifting-based DWT architecture, which requires half of hardware compared to the conventional approaches [2].

2.1 The 9/7 2-D DWT Algorithm

The 9/7 discrete wavelet transform factoring into lifting scheme is represented as [12]:

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡ +

⎥⎦

⎢ ⎤

⎣

⎡ +

⎥⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

= ⁻ ⁻

ζ ζ δ

γ β

α

/ 1 0

0 1

) 1 (

0 1

1 0

) 1 ( 1 1 ) 1 (

0 1 1

0

) 1 ( 1

~ ¹ ¹

7 / 9

z

z z

P z

(1)

where α,β,γ andδ are the coefficients of lifting scheme, and ζ and 1/ζ are scale normalization factors.

The architecture based on lifting scheme consists of splitting module, two lifting modules and scaling modules. The architecture of 9/7 1-D DWT based on lifting scheme is shown in Figure 1.

The 9/7 2-D DWT is a multilevel decomposition technique. According to the architecture of 9/7 1-D DWT based on lifting scheme, the architecture of modified 9/7 2-D DWT based on lifting scheme can be derived and shown in Figure 2.

2.2 The modified 9/7 2-D DWT Algorithm According to equation (1), the transform matrix of the 9/7 DWT based on lifting scheme is modified as

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

⎥⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

=

−

ζ ζ δ

γ

β α

/ 1 0

0 1

) 1 (

0 1 1

0

) 1 ( 1

1 ) 1 (

0 1 1

0

) 1 ( ) 1

(

1

1 1

~

z z

z z z

P

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

⎥⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

=

−

ζ αβγδ αβγδζ δ

δ γ

γ

β β α

α

/ 0

0 /

1 ) 1 (

0 / 1 / 1 0

) 1 ( / 1

/ 1 ) 1 (

0 / 1 / 1 0

) 1 ( / 1

1 1

z z

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

⎥⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

=

−

ζ αβγ αβγδζ γδ

βγ

αβ α

/ 0

0 1

1 0 / 1 / 1 0

1 1

0 / 1 / 1 0

1 1

z z

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

⎥⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

=

−

1 0 1

1

0 0 1

1

0 0

1 1

0 0

1 1

K K z

D C

z

z B A

z

(2)

where A=1/α , B=1/αβ ,C=1/βγ , D=1/γδ , αβγδζ

0 =

K ,and K₁=αβγ /ζ . 2.3 The 5/3 2-D DWT Algorithm

The data flow of 5/3 1-D DWT based on lifting scheme is shown in Figure 3.

The 5/3 2-D DWT is a multilevel decomposition technique; that decomposes into four subbands such as HH, HL, LH and LL. The data flow of 5/3 2-D DWT based on lifting scheme can be derived and shown in Figure 4. The 5/3 discrete wavelet transform factoring into lifting scheme is represented as [10]:

⎥⎦

⎢ ⎤

⎣

⎡

⎥⎦

⎢ ⎤

⎣

⎡

⎥ +

⎦

⎢ ⎤

⎣

⎡ +

= ⁻

1 0

0 1

1 ) 1 (

0 1 1

0

) 1 (

~ 1 ¹

3 /

5 z

P z

β α

(3)

3 The High-Efficient and

Reconfigurable Architectures for 9/7 and 5/3 Lifting-Based 2-D DWT

The proposed reconfigurable architecture for 5/3 and 9/7 lifting based 2-D DWT including horizontal filter (HF) and vertical filter (VF) is shown in Figure 5. In this reconfigurable architecture, the architecture of horizontal filter and the architecture of vertical filter are shown in Figure 6 and 7, respectively. The proposed reconfigurable architecture for modified horizontal filter (HF) consists of eleven delay units, seventeen multiplexers and two processing elements (PEs). The PE(A/B/E) performs O1 for data output 5/3(1) and PE(C/D/F) performs O2 for data output 9/7(1). The architecture of PE(A/B/E) and the architecture of PE(C/D/F) are shown in Figure 8 and 9, respectively. The architecture of scaling normalization (SN) is shown in Figure 10. Filter coefficients of the biorthogonal 9/7 and 5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architecture, all multiplications are performed using shifts and additions after approximating the coefficients as a Booth binary recoded format (BBRF). The constant multiplier shown in Figure 11 consists of two carry-save-adders (CSA(4,2)) , a Carry Lookahead Adder (CLA) , and six hardwire shifters and replaces conventional

(21)

multiplier )(⊗ in PE(A/B/E), PE(C/D/F) and SN.

Figure 12 shows architectures of line delays LD, LD1, LD2 and LD3 in vertical filter. We handle borders by the symmetric extension method [10]. Hence, the quality of reconstructed images can be improved.

The proposed reconfigurable architectures for 9/7 and 5/3 DWT reduce the critical path [13]-[19].

In N×N 2-D DWT, it requires

4 ) 1 1 3 ( ) 4 2 1 1 ( 10

9J + N − _J + N² − _J computation cycles (addition operations) with N²/4+9N memories to perform 9/7 2-D DWT, where J is number of levels. It requires

4 ) 1 1 3 ( ) 2 2 1 1 ( 2

4J + N − _J + N² − _J computation cycles (addition operations) with N²/4+3.5N memories to perform 5/3 2-D DWT, where J is number of levels. Both of two architectures are 100%

hardware utilization.

4 Conclusion

Filter coefficients are quantized before implementation using the biorthogonal 9/7 and 5/3 wavelet. The hardware is cost-effective and the system is high-speed. The proposed architecture in 9/7 DWT reduces power dissipation by m compared with conventional architectures in m-bit operand (low-power utilization).

The proposed architecture in 5/3 DWT with 24-bit fixed point operations had been applied to 512×512original images Lena is shown in Figures 13(a) and the reconstructed images Lena is shown in Figure 13(b), respectively. The PSNRs of the reconstructed images Lena is 32.554dB. Hence, the proposed reconfigurable architecture has been applied to image compression with great satisfaction.

In this paper, the high-efficient and low-power reconfigurable architecture for 2-D DWT has been proposed. The proposed reconfigurable architecture

performs compression in

J a

J N T

N

J+ − + − ))⋅

4 1 1 3 ( ) 4 2 1 1 ( 10 9

( ² computation

time for 9/7 DWT and

J a

J N T

N − + − ))⋅

4 1 1 3 ( ) 2 2 1 1 2 (

(3 ² for 5/3 DWT,

where the time unit (Ta is time of addition operation).

The critical paths are 3T_a for 9/7 DWT and 2T_a for 5/3 DWT, and the output latency time are49T_a for 9/7 DWT and 11T_a for 5/3 DWT. Buffer sizes areN²/4+9N for 9/7 DWT and N²/4+3.5N for

5/3 DWT. The control complexity is very simple.

The comparisons between previous works [13]

[18] and this work are shown in Table 1 for 9/7 DWT and Table 2 for 5/3 DWT.

The advantages of the proposed reconfigurable architecture are 100% hardware utilization and ultra low-power. The architecture has regular structure, simple control flow, high throughput and high scalability. Thus, it is very suitable for new-generation image compression systems, such as JPEG-2000. The proposed reconfigurable DWT is a reusable IP, which can be implemented in various processes and combined with an efficient use of hardware resources for the trade-offs of performance, area, and power consumption.

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[7] D. Taubman, “High performance scalable image compression with EBCOT,” IEEE Trans. Image Processing, Vol. 9, 2000. pp. 1158-1170.

[8] R. Kronland-Martinet, J. Morlet, A. Grossman,

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