Electrical and reliability characteristics of polycrystalline silicon thin-film transistors
with high- Eu2O3 gate dielectrics
Li-Chen Yen, Chia-Wei Hu, Tsung-Yu Chiang, Tien-Sheng Chao, and Tung-Ming Pan
Citation: Applied Physics Letters 100, 173509 (2012); doi: 10.1063/1.4705472
View online: http://dx.doi.org/10.1063/1.4705472
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/100/17?ver=pdfcov
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Electrical and reliability characteristics of polycrystalline silicon thin-film
transistors with high-j Eu
2O
3gate dielectrics
Li-Chen Yen,1Chia-Wei Hu,2Tsung-Yu Chiang,1Tien-Sheng Chao,1and Tung-Ming Pan2,a)
1
Department of Electrophysics, National Chiao Tung University, Hsinchu 30010, Taiwan 2
Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan
(Received 7 February 2012; accepted 8 April 2012; published online 25 April 2012)
In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3gate dielectric. High-j Eu2O3LTPS-TFT
annealed at 500C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm2/V-s, a small subthreshold swing of 142 mV/decade, and a high Ion/Ioff current ratio of
1.34 107. These significant improvements are attributed to the high gate-capacitance density due
to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide
thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device. VC 2012 American Institute of
Physics. [http://dx.doi.org/10.1063/1.4705472]
Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are known as attractive candidates for active matrix liquid-phase crystal display panel, three-dimensional (3-D) circuit integration, and system-on-panel (SOP) applications.1–3The ultra-thin SiO2(<2 nm) is
inevi-table to excessive leakage current due to the direct tunnel-ing.4 A low dielectric constant and high leakage current of thin SiO2 gate oxide in complementary
metal-oxide-semi-conductor (CMOS) devices hinder it to be used in low power and high performance applications. In contrary, high-j gate dielectrics can significantly reduce the gate leakage current for a given effective oxide thickness (EOT) and increase the gate capacitance density, causing high performance in LTPS-TFT. Rare-earth oxide materials, such as La2O3,5
CeO2,6and Dy2O3,7have been recently studied extensively
as promising gate dielectrics in advanced CMOS technology due to their high permittivity, large energy bandgap, and high thermodynamic stability with Si.8 Although many research efforts have been explored to improve the electrical performance of TFT devices,9,10 few investigations have been conducted on the positive bias temperature instability (PBTI) in high-j gate oxide LTPS-TFTs, and the mechanism of bias and temperature induced instabilities in the TFT devi-ces is still not clear. In this paper, a high-performance LTPS-TFT device incorporating a high-j Eu2O3gate dielectric is
demonstrated. Furthermore, the most important bias temper-ature instabilities are investigated in high-j Eu2O3
LTPS-TFTs.
The n-channel LTPS-TFTs were fabricated on 6-in. Si substrates. A 500 nm-thick SiO2was grown on the Si wafer
by a standard wet oxidation process. A 50 nm-thick undoped amorphous-Si (a-Si) layer was deposited on SiO2using
low-pressure chemical vapor deposition at 550C. The deposited a-Si layer was then re-crystallized by the solid-phase-crystal-lization (SPC) process at 600C for 24 h in N2ambient. The
phosphorous ion implantation was done with an energy of 80 keV and a dose of 5 1015cm2 to define source/drain (S/D) regions. The implantation was activated by the thermal treatment at 600C for 12 h. The Eu2O3 gate dielectric
(2.4 nm) was deposited on the polycrystalline silicon film by electron-beam evaporation method, followed by thermal annealing at 500 and 600C for 30 min in N2 ambient to
improve the gate dielectric quality. An interfacial layer (2 nm) was observed between poly-Si film and Eu2O3
dielectric, which was confirmed by cross section TEM image in Fig.1(a). Subsequently, Eu2O3film was removed in the S/
D regions by dry etching system. Finally, 300 nm-thick Al was deposited by physical vapor deposition to pattern the gate and S/D electrodes. The schematic cross-sectional view of the Eu2O3LTPS-TFT device structure was shown in Fig.
1(b). The threshold voltage (VTH) was defined as the gate
voltage at which the drain-current reaches 100 nAW/L at VDS¼ 0.5 V. The field effect mobility (lFE) is derived from
the value of maximum transconductance of the TFT device. The well-behaved IDS–VGS transfer characteristics of
the high-j Eu2O3 LTPS-TFT devices annealed at 500 and
600C are shown in Fig. 2. The TFT device annealed at 500C exhibits high performance, including a very low VTH
of 0.16 V, a high field effect mobility (lFE) of 44 cm2/V-s,
and a small subthreshold swing (S.S.) of 142.2 mV/decade, compared with the device annealed at 600C. This may be attributed to the superior gate dielectric and low interface trap density at the dielectric/poly-Si interface.11In addition, these devices show a low gate-induced drain leakage current of 1012 A. The EOT and the dielectric constant (j) of Eu2O3film annealed at 500C were evaluated as 2.5 nm
and 19, respectively, corroborated well with the above results. The Ion/Ioffvalue of 1.34 107in the LTPS-TFT
de-vice annealed at 500C is larger than that of device annealed at 600C (8.44 106). The positive threshold voltage shift in these LTPS-TFT devices can be ascribed by the interfacial electron trapping due to the presence of an unrestrained silicate layer at the dielectric/poly-Si interface.12,13 For the a)E-mail: [email protected]. Tel: 886-3-211-8800 Ext. 3349. Fax:
886-3-211-8507.
0003-6951/2012/100(17)/173509/3/$30.00 100, 173509-1 VC2012 American Institute of Physics
APPLIED PHYSICS LETTERS 100, 173509 (2012)
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Eu2O3 film annealed at 600C, a higher VTH shift was
observed. This behavior may be due to the formation of thicker silicate layer at the oxide/poly-Si interface.14
Figure 3 shows the output characteristics (IDS–VDS) of
the high-j Eu2O3LTPS-TFTs annealed at 500 and 600C. It
can be seen that the driving current of LTPS-TFT device annealed at 500C increases significantly compared to that of device annealed at 600C. The plausible mechanism may be the higher field effect mobility of charge carrier and the smaller threshold voltage of the device. The high driving
current would be very promising for the application of SOP and 3-D circuit integration. The important device parameters of Eu2O3 dielectric incorporated LTPS-TFTs are listed in
TableI. An improvement in device performance is observed compared with other recently published works with different gate dielectrics including SiO2,15 Y2O3,16 HfO2,17 and
Pr2O3.18 The Eu2O3 LTPS-TFT can speedily fill the trap
states at the grain boundary and fast turn on the device due to the ultra thin EOT and large gate capacitance density.17
The bias temperature instability of the high-j Eu2O3
LTPS-TFT device is investigated under 25 and 85C. A dc voltage in the range between 1.5 and 2 V was applied to the gate with the source and drain grounded. Fig.4(a)shows the threshold voltage shift of the high-j Eu2O3 LTPS-TFT
de-vice under constant voltage stress (CVS) for different condi-tions. The turn-around phenomenon was observed for 1.5 V stress voltage at 25C. The injected electrons from sub-strates are trapped in the interfacial layer without Si-O bonds breaking, which cause the positive VTHshifts. This
phenom-enon can be interpreted by the modified reaction-diffusion model based on electric stress induced defect generation mechanism.19After 100 s of CVS, the threshold voltage shift direction switches from positive to negative with increasing stress time, suggesting the electron detrapping from Eu2O3
film. On the other hand, the PBTI measurement shows that a larger stress gate voltage leads to a more severe degradation in the VTHshift, which indicates that bias temperature
insta-bilities for high-j Eu2O3 LTPS-TFT are electrically
acti-vated. Fig. 4(b) shows the effect of PBTI stress on the transfer characteristics of the n-channel LTPS-TFTs. It was found that the VTHvalue changes from positive to negative
after PBTI stress, indicating that the PBTI stress generates more positive interface trap states in the device. In addition, the field effect mobility degrades after the PBTI stress. For positive bias stress, the accelerated electrons would break the weak grain boundary bonding, resulting in a large
FIG. 1. (a) TEM cross-sectional image of the stacked Eu2O3/SiOxgate dielectric annealed at
500C and (b) cross-sectional view of the high-j Eu2O3LTPS-TFT device structure.
FIG. 2. Transfer characteristics (IDS–VGSand lFE) of the Eu2O3LTPS-TFT
devices annealed at 500 and 600C, measured at V
DS¼ 0.5 V.
FIG. 3. Output characteristic IDS–VDSof high-j Eu2O3LTPS-TFT devices
annealed at 500 and 600C.
TABLE I. Comparison of device parameters for LTPS-TFTs fabricated with a SiO2, Y2O3, HfO2, Pr2O3, and Eu2O3.
SiO2 Y2O3 HfO2 Pr2O3 Eu2O3 W/L 10/10 10/5 0.1/1 10/10 10/10 VTH(V) 12 1.76 0.3 1.58 0.16 S.S. (mV/decade) 2060 269 280 276 142.2 EOT (nm) 50 8.6 7.3 6.5 2.51 lFE(cm2/V-s) 11 32.7 39 28.33 44.07 Ion/Ioff 4.65 106 1.83 107 9.7 106 3.9 106 1.34 107
173509-2 Yen et al. Appl. Phys. Lett. 100, 173509 (2012)
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number of defects into the poly-Si channel film and/or the interfacial layer to generate the oxygen vacancy (VO2þ) and
interstitial oxygen (IO2).20The VO2þwould accumulate in
the interfacial layer and the IO2 would diffuse/drift into
Eu2O3bulk under positive bias, as shown in Fig. 5(a). The
VO2þ is a shallower defect compared with the VO0 in the
energy-band diagram, as illustrated in Fig.5(b). This nega-tive shift may be attributed to electron de-traps from deep level IO2, possibly indicating that it occupied at a lower
level than the work function of Al. Under PBTI stress, the electron de-trap film in the Eu2O3is dominant than electron
trapping.
In summary, a high-performance LTPS-TFT device fea-turing an ultra thin Eu2O3 gate dielectric is demonstrated.
High lFE, low VTH, large Ion/Ioff, and excellent S.S. are
achieved in the n-channel poly-Si LTPS-TFT due to the adequate quality of the gate dielectric with some unre-strained silicate layer served as stacked gate dielectric. Con-sequently, it is very promising for the application of SOP technology due to the high electron mobility of the device. In addition, the mechanism of PBTI in high-j Eu2O3LTPS
TFT is investigated. PBTI may be attributed to the creation of defects in poly-Si TFT channel by breaking of Si–O bonds at the grain boundaries and/or the interfacial layer between
Eu2O3and poly-Si film, and thus, the oxygen ions or
vacan-cies will diffuse/drift into the Eu2O3film to degrade the
de-vice performance.
The authors would like to thank the members of the Nano Device Laboratory for their technical help. This pro-ject was supporting by the National Science Council (NSC) of China under contract no. NSC-98-2221-E-182-056-MY3.
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FIG. 4. (a) Threshold voltage shift as a function of stress time for high-k Eu2O3
LTPS-TFT devices annealed at 500C
under various positive biases and tempera-tures. (b) Transfer characteristics of the high-j Eu2O3 LTPS-TFT device before
and after PBTI stress.
FIG. 5. (a) Modified reaction-diffusion model and (b) energy-band diagram of the high-j Eu2O3LTPS-TFT device under PBTI stress.
173509-3 Yen et al. Appl. Phys. Lett. 100, 173509 (2012)
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