A Wide Tuning Range G
m
–C Filter for Multi-Mode
CMOS Direct-Conversion Wireless Receivers
Tien-Yu Lo, Chung-Chih Hung, Senior Member, IEEE, and Mohammed Ismail, Fellow, IEEE
Abstract—A third-order channel selection filter for multi-mode
direct-conversion receivers is presented. The filter is designed with a Butterworth prototype and with the target wireless appli-cations of Bluetooth, cdma2000, Wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs. Linear-region MOS transistors are used to perform voltage-to-current conversion. The wide tuning range is achieved by the current multipliers and linear voltage-to-current converters. Implemented in the TSMC 0.18 m CMOS process, the measurement results show that the filter can operate successfully over a cutoff frequency range of 500 kHz to 20 MHz, and is compliant with the requirements of different wire-less applications. The power consumption is 4.1 mW to 11.1 mW for minimum and maximum cutoff frequencies respectively from a 1.2 V supply voltage. The circuit performance compares favorably with previously reported works.
Index Terms—Current multiplier, direct-conversion receiver,
multi-mode, transconductor, wide tuning range.
I. INTRODUCTION
A
S THE LEVEL of integration in RF transceivers in-creases, CMOS emerges as the technology with the greatest potential for cost effectiveness where RF, mixed-signal and digital circuits are integrated in a single system-on-chip (SoC). This is particularly true when multi-mode wireless chip sets are embedded into mobile computing or multimedia systems. When designing a wireless receiver, one of the most important tasks is to design the channel filtering to separate the desired signal from the unwanted ones. Recent demand for multi-standard transceivers calls for adopting direct-conversion architectures to achieve the highest level of integration and for ease of system design. Fig. 1 shows a block diagram of a direct-conversion receiver. It converts the RF signal with both desired and unwanted signals, directly to baseband. Since the unwanted signals are still left at adjacent channel, the received signal is selected by the channel selection filter for further demodulation. However, an array or a stack of channel selection filters in a multi-standard radio design may not be power-efficient and would need large chip areas. Therefore,Manuscript received November 27, 2007; revised April 11, 2009. Current version published August 26, 2009.
T.-Y. Lo is with MediaTek Inc., Hsinchu, Taiwan (e-mail: tienyu.lo@gmail. com).
C.-C. Hung is with the Department of Communication Engineering, National Chiao Tung University, Hsinchu, Taiwan (e-mail: cchung@mail.nctu.edu.tw).
M. Ismail is with the Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210 USA (e-mail: ismail@ece. osu.edu).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2009.2023154
Fig. 1. Simplified block diagram of a direct-conversion receiver.
there is a strong motivation to realize a single baseband channel select filter such that it meets the requirements of multi-mode applications.
This work focuses on the design of such a multi-mode channel selection filter and is targeting direct-conversion radio architectures. The filter is designed based on a G –C filter topology, and has a wide continuous tuning range. The large tuning range is designed to meet the wireless specifications of Bluetooth (650 kHz), cdma2000 (700 kHz), Wideband CDMA (2.2 MHz), IEEE 802.11a/g (10 MHz), IEEE 802.11b (12 MHz), IEEE 802.11n (20 MHz) wireless LANs applica-tions. These specifications cover the frequency range from 650 kHz to 20 MHz.
Most G –C filters encounter noise and linearity tradeoff when they are utilized for large tuning-range application. They usually suffer from either low linearity or high noise. From system level analysis, the input-referred noise within the spec-ified bandwidth can be determined by giving the RF front-end gain. The noise level defines the sensitivity of a receiver where the minimum acceptable level can be detected, and the gain of the RF front-end section should be chosen so that the output stage would not saturate under system specification. From the Friis equation, the noise figure (NF) of the receiver is given by
(1)
where , and are the noise figure of
re-ceiver, RF front-end, and analog baseband. The analog base-band includes the analog filter and the programmable gain am-plifier. When the output impedance of the RF front-end is given by , the input-referred noise of analog baseband section can be expressed as
(2) where is the Boltzmann coefficient and is the input-re-ferred noise power specified for 1 Hz bandwidth. Therefore, we can relax required noise specification by giving a larger RF
the noise specification of the baseband stage can be relaxed. The analysis for a multi-mode receiver front-end requires a range of input signal magnitude specifications that cover all the operation modes. Assuming that the receiver provides a NF of 9 dB, an overall IIP3 of 9 dBm, and a gain requirement between 10 and 100 dB, the range of all the requirements for the baseband sec-tion is the result of an optimal tradeoff among gain, noise, and linearity throughout the receiver blocks. By giving the system analysis and the scenario simulated over the receiver, the ac-ceptable levels of the filter IIP3 for GSM/cdam2000, Wideband CDMA, and IEEE 802.11 mode are 19.2 Bm, 21.1 dBm, and 19.6 dBm, respectively.
For the G –C topology, a transconductor is used as a basic building block [1]–[5], and the transconductance value is pro-portional to the 3 dB cutoff frequency of the filter. The ap-plication mode is selected by changing the transconductance, and a tuning ratio of 30 is required. However, when process and temperature variations are taken into account, a tuning ratio of more than 50 should be achieved and the linearity performance should be still maintained at acceptable levels.
In this paper, Section II develops the proposed high linearity transconductor with a wide transconductance tuning range. The third-order Butterworth G –C filter which meets the required specification is presented in Section III. Section IV presents the measurement results and compares the proposed design with the state of the art. Finally, conclusions are addressed in Section V.
II. PROPOSEDTRANSCONDUCTORCIRCUIT
The main function of a transconductor is to convert the input voltage into the output current with a linear transformation factor, and the transconductor employed in filters must be linear over the input signal swing range. On the other hand, the transconductance should be tuned to compensate for process and temperature variations, and we can model it as a voltage controlled current source. In the circuit implementation, bipolar transistors offer wide transconductance tunable range because the collector current can be varied with little change in the base-emitter voltage. In contrast, the bias of the MOS transis-tors should be varied significantly and the supply voltage would then limit the tuning range, which implies the requirement of a higher supply voltage. Thus, a high linearity and wide tuning range transconductor in a low voltage CMOS technology would not only be needed for multi-mode wireless applications but also be helpful to combine with digital circuits for a system on a chip design.
relationship for the circuit in Fig. 2(b) is presumably obtained. From a simplified BISM Level 3 model, the drain current is given by
where (4)
where is the body effect factor and is the surface inversion
potential. , and are the width and
length of the device, respectively, is the oxide capacitance per unit channel area, is the low-field mobility, and is the NMOS threshold voltage. and are the gate-to-source and drain-to-gate-to-source voltages, respectively. By taking the process and temperature variation into consideration, can be chosen to be a value of 1.2.
We can now see that the output current would not really hold a linear relationship to the input voltage owing to the additional second term in (4), which thus degrades the linearity of the transconductor. We can find that the second term in (4) forms a square-law equation. Previous research [6] reports that an-other transistor could be added to cancel out the second term in (4) based on the large signal square-law equation in the sat-uration region. Thus, the output current would be proportional to the input voltage, and the transconductance can be tuned by adjusting the bias voltage at the gate terminal. In the circuit, the 40 dB total harmonic distortion (THD) was reported. There are several disadvantages of this linearization technique. First, extra complex circuit should be included for current cancella-tion, and this technique needs an extra operational amplifier, which implies more power consumption. Second, the constraint of linear region operation, , should be held and this condition is hard to sustain under wide tuning requirement. Finally, it would not work well in modern nanoscale CMOS technologies owing to the fact that short channel effects would alter the square-law behavior and then degrades nonlinearity cancellation.
Since the compensation technique reported in [6] is based on a single-ended structure and is not suitable to provide the re-quired high linearity and low power for transconductor design in modern CMOS process, a differential structure can be simply used to cancel out the second term in (4). Therefore, we can take the single-ended circuit of Fig. 2(b) and use it in a fully differen-tial mode as shown in Fig. 2(c). To obtain the voltage-to-current
Fig. 2. (a) Conventional transconductor. (b) MOSFET-only transconductor. (c) Differential transconductor.
characteristics of the circuit, the input differential voltages at the gate of transistors M1 and M2, are given by
(5) (6) where is the input common-mode voltage and is the input differential voltage. The gate terminals of the linear-region transistors M7 and M8 will be biased at an appropriate voltage, , to make sure the linear region operation is achieved. The second term in (4) can be cancelled out by the inherent differ-ential structure, and thus the output current would be given by
(7) The equation shows that a linear voltage-to-current conversion is obtained, and that the output current is dependent on the bias voltage and the input common-mode voltage.
B. The Proposed Transconductor With Tuning Scheme
Followed the basic concept of the differential structure in Fig. 2(c), wide range transconductance tuning is hard to achieve by adjusting and . In general, should be biased at a higher voltage, such as the supply rail, and then the tran-sistor would always work in deep linear region and perform a highly linear operation. Thus, a high linearity current multiplier would be required following the voltage-to-current conversion. Fig. 3 shows the concept of the transconductor, which has a wide transconductance range. In the proposed transconductor, the linear voltage-to-current conversion is performed first, and then the transconductance is tuned over a wide range using the translinear loop that follows. The translinear loop is to pro-vide the function of current multiplier. Through the use of the feedback loop, linear voltage-to-current conversion can be ob-tained owing to the fact that the input voltage would be equal to the drain voltage of transistors M1 and M2. Thus, the current flowing through resistors and would have a very high linearity relationship with the input voltage. The current multi-plier is composed by transistors M1 to M4, resistors and
Fig. 3. Concept of a wide tuning range transconductor.
, and current source . Transistors M1 to M4 are biased to operate in the weak inversion region while suitable device sizes are used. A single expression of the transistor model useful in weak, moderate, and strong inversion regions with larger than a few times of the thermal voltage , is employed [7]
(8) where is the fitting parameter, is the subthreshold slope factor, is the transistor threshold voltage, and is the thermal voltage. The inversion factor defined by is often used to define the boundaries between the MOS inversion regions. When , the operation region is corresponding to the strong inversion. On the opposite, the operation region is cor-responding to the weak inversion when . The expression can fit the case of the general weak to strong inversion equa-tions. For a MOSFET operating in the weak inversion region, its current exhibits an exponential dependence on , and can be expressed from (8) to obtain
(12) The current output from the differential pair of transistors M3 and M4 can be expressed by
(13)
(14) Finally, the output current is given by
(15) Thus, the output current is equal to a scaled value of the input current. The transconductance tuning can be achieved and the scaling can be determined by the bias current . In the cir-cuit, the transconductance in the weak inversion region can be expressed as
(16) In case of a large current, transistors M3 and M4 will enter into the saturation region while transistors M1 and M2 are still in the weak inversion region. From the equation of a differential amplifier in the saturation region, the output current
can be expressed as
(17) where is the gate differential voltage expressed in (12), and the value can be simplified by neglecting high order terms from a Taylor series expansion. Therefore, we can have
(18)
dependent on the square value of at this condition, rather than the linear scaled fashion in (16).
When the tuning current becomes larger, transistors M3 and M4 will enter into the moderate inversion region. We can use (8) and is defined between 0.1 and 10 to express moderate inversion operation. By using the expression for moderate inver-sion region, it is hard to have a simple general form for transcon-ductance in the transconductor. Thus, the numerical behavior is applied to simulation, and the behavior shows that the tran-conductacne is in proportional to the function of current , and has an inverse proportion to input common-mode voltage. The analysis also predicts the THD of less than 55 dB for the current multiplier in moderate inversion region where the worst case occurs at . The scaled output current can be com-bined with the highly linear voltage-to-current conversion, and then the proposed wide tuning range linear transconductor can be achieved.
C. The Final Circuit Implementation
Fig. 4 shows the final circuit implementation of the proposed transconductor. The linear region transistors are used as the re-sistor and in Fig. 3. Unfortunately, short channel effects still occur and high order nonlinearity components degrade the linearity of the V-I conversion, especially for nanoscale tech-nologies because (4) is a simplified approximate model. Thus, any distortion components should be analyzed and a new de-sign methodology should be applied to perform a high linearity conversion. For a linear region transistor, the transistor model which takes the mobility effect into consideration is expressed as [8]
(21)
where is the mobility reduction coefficient and is the de-fault device equivalent resistance in the linear region. In the equation, the value of would be set to one for simplification.
By giving , ,
and , we can derive the voltage-to-current characteristic of MOS transistors M13 and M14. To analyze the linearity of the voltage against the drain current, a Taylor
Fig. 4. Final implementation of the proposed transconductor with the CMFB circuit.
series expansion is used and then the relationship would be ex-pressed by
(22) where and are as given in the equation at the bottom of the page.
Therefore, the third-order harmonic distortion term can be approximated to (23), shown at the bottom of the page.
Owing to the non-ideal characteristic of the linear region MOS transistor, the linearity performance would be degraded. In the equation, the first-order term defines the transconduc-tance of the MOS resistor. The even-order harmonic terms can be cancelled out by the differential structure and thus the third-order harmonic distortion would become the dominant component. We can find that to minimize the third-order dis-tortion term of the circuit, a small should be taken. In the theoretical analysis, a 20 dB increase can be achieved for a 3 dB decrease of the input common-mode voltage. However,
compared with the calculated value, an 18.8 dB increase of linearity performance is obtained in simulation, and a value of smaller than 60 dB can be achieved for an optimized input common-mode voltage. In addition, since resistors and shown in Fig. 3 are used to provide a suitable bias point when tuning the transconductance, the resistance would be small in our circuit and can be replaced by a transistor in the linear region. Therefore, the transistor M17 with large aspect ratio in Fig. 4 is introduced.
Fig. 5 shows the large signal simulation with respect to the function of the differential input voltage. The tuning range of 2 S to 110 S corresponding to the scaled value of current can be obtained. The tuning ratio of more than 55 can be achieved, and it is suitable for our applications. We can find that transistors M3 and M4 would operate from weak inversion region to saturation region at large bias current, and the scaled function would become a radical expression.
The CMFB circuit, which is composed by transistors MF1 to MF8, is used for the differential structure. The aspect ratio of the transistor M18 would be twice the value of the transis-tors MF1 and MF2 for suitable operation. The purpose of the CMFB circuit is to balance the voltage over the entire range
Fig. 5. Simulated G range of the proposed transconductor.
of the transconductor output nodes. The feedback loop forces the output common-mode voltage to the desired value, and then the linearity of the input transistors in the following transcon-ductor circuit would be maintained. In our circuit, the maximum output swing range is defined by the maximum input signal, and the correct swing operation is confirmed by simulation. To ob-tain higher gain at low supply voltage, large sizes of transistors MF3 to MF6 are selected and these transistors operate in the weak inversion region. However, the CMFB gain would be re-duced at large input swing. When the gain of the CMFB circuit is reduced, it will lead to an offset voltage to the input node of next stage and then affect the linearity of voltage-to-current con-version. Thus, the distortion would become a little worse than expected when large signal appears within the filter cutoff fre-quency. This effect can be recovered by using extra resistors to replace differential pair for averaging differential signals.
D. Nonidealities in the Proposed Circuit
The thermal noise is a combination of the noise generated by the voltage-to-current conversion core and the current multi-plier. In order to obtain the noise performance, a noise model validated in the weak to strong inversion region is required. As the model in [9] is introduced, the input-referred thermal noise is as shown in (24) at the bottom of the page, where is the Boltzmann constant and is the noise parameter at satu-ration, subthreshold, and linear regions. From the equation, the noise contribution can be divided into two parts. One is con-tributed by the feedback amplifier, which is composed by tran-sistors M5 to M12, and the other is the devices in the
nega-tors M13 and M14 are operated in the linear region, and the transconductance can be increased by giving a large transistor aspect ratio and gate overdrive voltage. We should note that to achieve a larger transconductance, the bias current would become larger to consume more power. Thus, a small input common-mode voltage can be used to maintain the bias cur-rent while the overall transconductance derived from (16) and (20) tends to increase. In this circuit, even the high linearity cur-rent multiplier would contribute extra noise in the wide tuning transconductor, it is fortunate that half of the multiplier is com-bined with the voltage-to-current core, and thus only transistors M1 to M4 are added for current scaling. This condition reduces the contributed noise from the current multiplier. In our simu-lation, a 3 dB increase of the aspect ratio could result in about 3 dB increase of the noise performance.
The impact of flicker noise should also be taken into consider-ation. In this design, the device sizes of the transistors which de-termine the flicker noise are increased to reduce the flicker noise, and the transistor length is designed to ten times of the min-imal size used in the process. The larger size of the device also decreases the effect of channel length modulation and increase the output impedance. We should note that the large device size would induce more parasitic capacitance, and thus not only the unity-gain frequency is decreased but also the voltage-to-cur-rent conversion linearity at high speed is degraded. Since the flicker noise contributes only part of the noise in our design, the tradeoff between the noise and speed should be taken into consideration.
The mismatch is caused by the random variation of the process in physical quantities of identically designed devices. The random mismatch comes from the fabrication tolerances, and it produces the even-order distortion terms in differential structure. In the circuit, the linearity of the voltage-to-current conversion core is not sensitive to the mismatch owing to
Fig. 6. Block diagram of the third-order Butterworth filter.
the feedback topology. The mismatch of the input transistor dimensions and threshold voltage will just produce a DC offset voltage at the resistor terminals. Thus, the converted output current would behave only first-order fashion to the input voltage. When the linear region transistors are introduced, the offset voltage will induce a slight variation of transconductance as the short channel effect is simply neglected, and then the linearity performance can be hold. However, when the mis-match between linear region transistors M13 and M14 occurs, the voltage-to-current conversion would provide second-order distortion and degrade the linearity performance. In addition to the voltage-to-current conversion core, mismatch problem would get a higher nonlinear effect on the current multiplier. Simulation results show an increase of 3 dB in the second har-monic distortion term for a 2% mismatch of transistors M1 and M2. Thus, large transistor length is suitable for the multiplier in our design. This condition also helps the multiplier to achieve a higher linearity operation since it tends to work under the weak inversion operation.
III. FILTERARCHITECTURE
From the demonstration of the passive ladder prototype, the third-order Butterworth low-pass G –C filter, consisting of seven identical transconductors, is used as shown in Fig. 6.
In this low-pass filter design, the time constant of the filter is determined only by the G C ratio, where G is the transcon-ductance and C is the loading capacitance. The loading capacitor is realized from metal–insulator–metal structure. The transcon-ductance would be programmable and has a nominal value of S. The 6 dB gain loss of the passive prototype has been compensated at the input of the filter by increasing the transcon-ductance by a factor of two. The other transconductors would be set to the same value so that frequency tuning can be achieved from a single source. Dynamic range scaling was applied, and we have made sure the output swing of each transconductor is equal to the maximum range. Since the filter is synthesized by Butterworth ladder prototype, which behaves all-pole charac-teristic, the quality factor is equal to 1. Therefore, no peaking will appear near the cutoff frequency. The cutoff frequency of the G –C filter is tuned by changing the bias current in our proposed transconductor. The automatic frequency tuning circuitry has not been investigated for this filter. However, the
Fig. 7. Chip micrograph.
tuning circuitry can be developed with digitally controlled cir-cuits in a system on chip solution by choosing a number of cur-rent sources for multi-mode selection. In addition, Q tuning cir-cuits are not considered here with the intrinsic quality of the low Q structure.
The output common-mode voltage of each block would be fixed by three CMFB circuits in the filter. The CMFB circuit is shown in Fig. 4. The bias current of the CMFB circuit should be changed according to the value, and then the performance of the common-mode control topology can be maintained.
IV. MEASUREMENTRESULTS
The transconductor and the filter were designed in the TSMC 0.18 m CMOS process. The chip micrograph is shown in Fig. 7 with the active area less than 0.23 mm .
The transconductor has been examined in the frequency domain to obtain its linearity performance. Fig. 8 shows the spectrum of the transconductor through inter-modulation char-acterization by applying two-tone signals near 20 MHz with the amplitude of 0.6 voltage. In this measurement, the transconductance is 100 S and the loading resistor is 50 ohm. The result shows the third-order inter-modulation distortion (IM3) is around 54 dB. The measured performance is smaller than the expected value from simulation. This is owing to the deviation of the feedback amplifier gain and the effect of parasitic capacitance at high frequency.
Fig. 9 illustrates the filter frequency response at 1.2 V supply voltage. We should note that the magnitude is normalized owing
Fig. 8. Two-tone test of the proposed transconductor.
Fig. 9. (a) Measured frequency responses of the proposed multi-mode filter. (b) Frequency response of IEEE 802.11 mode with an extension to 100 MHz.
to the use of the output buffer. The cutoff frequency can be tuned from 500 kHz to 20 MHz, and the range covers the specifi-cations of Bluetooth, cdma2000, Wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs. The IM3 test yield the IIP3 re-sults of 22.3 dBm, 21.8 dBm, 20.5 dBm, 20.2 dBm, and 19 dBm for each wireless specification, respectively.
The measured input-referred noise spectrum density at 70 C is summarized in Table I. Since the cutoff frequency of the
Fig. 10. In-band IIP3 between Bluetooth/cdma2000 and IEEE 802.11n setting.
G –C filter is programmed by adjusting the transconductance, the filter can be considered as a constant-capacitance network. In [10], the integrated output thermal noise is shown to be inde-pendent to the frequency scaling factor from analysis, and the dynamic range is almost the same over the tuning range. We can find that the measured input-referred noise density value in Table I has an inverse proportion factor rather than a square-rooted inverse proportion factor to the scaled frequency. The deviation of the expected value is owing to the circuit flicker noise at low frequency and extra circuit on PCB board at high frequency. The measured noise gives an 80 dB dynamic range at IEEE 802.11 mode for 40 dB IM3.
The DC offset decreases the dynamic signal swing, and then reduce the gain and linearity performance of the receiver. The offset cancellation loop/algorithm is usually used to compensate DC values while still maintaining the well performance of the system. The measured input second-order intercept point (IIP2), which can stand for the second-order distortion performance for every wireless mode, is also shown. Moreover, the linearity performance of out-of-band blocking interferences is measured. The value is described by out-of-band IIP3 in Table I. The IIP3 plot for highest and lowest cutoff frequency setting is shown in Fig. 10.
Table II summarizes the filter type and detailed information for several filters reported in recent years. A figure of merit (FOM), which is independent to the tuning ratio, is used to eval-uate the filter performance [11]
(25) where is the total power of the filter, is the number of poles, is the cutoff-frequency, is the normal-ized spurious-free dynamic range, with
(26) where is the input-referred noise power. In this paper, the FOM of this filter is plotted versus the supply in Fig. 11 and
TABLE I
PERFORMANCESUMMARY OFTHISWORK
TABLE II
COMPARISONWITHPREVIOUSLYREPORTEDWORKS
Fig. 11. FOM versus supply comparison with previously published works.
favorably compared to other published works, where some of them are not G –C prototypes. In this figure, symbols L
and H denote the lowest and highest frequency for each filter, respectively.
V. CONCLUSION
The CMOS implementation of a third-order Butterworth low-pass G –C filter for multi-mode applications is presented. The transconductor is designed by the combination of a voltage-to-current circuit and a voltage-to-current multiplier to achieve both the high linearity and wide tuning range simultaneously. Through the use of the wide tuning range linear transconductor as a building block, the cutoff frequency of the channel selection filter can be widely tuned from 500 kHz to 20 MHz, which meets the speci-fications of Bluetooth, cdma2000, Wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs under direct-conversion architec-ture. The theoretical analysis of the operation and the measure-ment results are provided to demonstrate the validity of the filter.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Implemen-tation Center of Taiwan for supporting the chip fabrication.
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Tien-Yu Lo received the B.S., M.S., and Ph.D.
de-grees in communication engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001, 2003 and 2007, respectively.
Since 2008, he has been with the Analog Circuit Design Division, MediaTek Inc., Hsinchu, Taiwan, as an Analog IC Designer. His research interests include analog and mixed-signal circuit design with partic-ular focus on the topic of continuous-time filters and analog-to-digital converters.
Mohammed Ismail (F’97) received the B.S. and
M.S. degrees in electronics and communications from Cairo University, Cairo, Egypt, and the Ph.D. degree in electrical engineering from the University of Manitoba, Canada.
He has over 25 years experience of R&D in the fields of analog, RF and mixed-signal integrated cir-cuits. He has held several positions in both industry and academia and has served as a corporate consul-tant to nearly 30 companies in the US, Europe, and the Far East. He is Professor of electrical and com-puter engineering and the Founding Director of the Analog VLSI Lab at The Ohio State University, Columbus, and of the RaMSiS Group at KTH–Royal In-stitute of Technology, Stockholm, Sweden. His current interest lies in research involving digitally programmable/configurable integrated CMOS radios with focus on low voltage/low power “first-pass” solutions for cognitive radios, 3 G and 4 G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has co-edited and coauthored several books, including
Analog VLSI Signal and Information Processing (McGraw Hill). His most
re-cent book is Radio Design in Nanometer Technologies, (Springer, 2007). He advised the thesis work of 45 Ph.D. students and of over 85 M.S. students. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Firstpass Technologies Inc., a developer of CMOS radio and mixed-signal IPs for hand-held wireless applications.
Dr. Ismail has been the recipient of several awards, including the US National Science Foundation Presidential Young Investigator Award, the US Semicon-ductor Research Corp Inventor Recognition Awards in 1992 and 1993, The Col-lege of Engineering Lumley Research Award in 1992,1997, 2002 and 2007 and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the
Interna-tional Journal of Analog Integrated Circuits and Signal Processing (Springer)
and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE transactions, is on the International Advisory Boards of several journals, and was on the Board of Governors of the IEEE Circuits and Systems Society. He is the founder of ICECS, the CAS flagship Conference for Region 8.
