IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 3, MARCH 2013 435
Backside-Process-Induced Junction Leakage and
Process Improvement of Cu TSV Based
on Cu/Sn and BCB Hybrid Bonding
Yao-Jen Chang, Cheng-Ta Ko, Tsung-Han Yu, Cheng-Hao Chiang, and Kuan-Neng Chen, Senior Member, IEEE
Abstract—Wafer-level 3-D integration using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn–BCB hybrid bonding is investi-gated with electrical leakage current. With the well-fabricated Cu TSVs and Cu/Sn bond structures, the leakage current path in this scheme due to backside process was found, and the corresponding mechanism is discussed. The leakage current can be solved by the modified backside process. The improved 3-D integration scheme shows extremely low leakage current and no visible defects inside Cu TSV.
Index Terms—Hybrid bonding, leakage current, through-silicon via (TSV), 3-D integration.
I. INTRODUCTION
T
HREE-dimensional integrated circuits have received widespread recognition as the most promising solution for the next semiconductor generation since this technology has the potential to break through the limitation of traditional 2-D scaling and provides a lot of merits, such as smaller form factor, lower power dissipation, lower transmission delay, and the great capability of heterogeneous integration [1], [2]. Several wafer-level 3-D integration schemes have been developed by using Cu through-silicon vias (TSVs) and bonding technologies for establishing the baseline of 3-D platforms vertically linked with several different functional blocks [3]–[9].One wafer-level 3-D integration scheme with Cu TSVs and fine-pitch Cu/Sn-microbump-to-BCB hybrid bonding was pro-posed [9]. One advantage of the hybrid bonding integration scheme is low bonding temperature (< 250 ◦C) without any cracks and issue of underfilling. The simplified carrierless process can reduce cost, remove the risk of handling wafers, and increase yield and throughput. Exceptional results of reliability tests [10] indicate an excellent bonding strength against oxida-tion and corrosion through the BCB reinforcement. However,
Manuscript received November 27, 2012; revised December 22, 2012; accepted January 2, 2013. Date of publication January 23, 2013; date of current version February 20, 2013. This work was supported in part by the Ministry of Education in Taiwan under the ATU Program and in part by the National Science Council through Grant NSC 101-2628-E-009-005. The review of this letter was arranged by Editor S. List.
Y.-J. Chang, T.-H. Yu, C.-H. Chiang, and K.-N. Chen are with the Depart-ment of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]).
C.-T. Ko is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the Electronics and Op-toelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu 31040, Taiwan.
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2013.2238213
TABLE I
TSV PARAMETERS, INCLUDINGVIADIAMETER, PITCH,ANDVIA
DEPTH,ANDCORRESPONDINGRESULTS OFA∗ANDRS
other than the quality of the bonding structure and TSV in this 3-D integration scheme, the integration of RDL and TSV using polymer as isolation may be challenging and needs extra attention.
In this letter, we investigate the backside-process-induced TSV leakage current, which might be ignored and not addressed in the fabrication of 3-D integration platforms. The procedure to verify the failure location and possible transport mechanism is described. The electrical characteristics and OBIRCH results simultaneously indicate that the leakage current comes from the Ti overlaying on Si. Finally, the improved backside process is developed and shows an extremely low leakage current in this 3-D integration platform.
II. EXPERIMENT
The fabrication of this 3-D integration scheme employs the following key technologies: Cu TSVs, fine-pitch Cu/Sn microbumps, patterned BCB, hybrid bonding, wafer thinning, and backside RDL process. First, 200-mm silicon wafers were cleaned and lithographed for fabricating 5- and 10-μm Cu TSVs by using the sequence of 40-μm-deep DRIE for via opening, ∼400-nm PE-TEOS oxide liner deposition, TiN/Cu deposition as barrier/seed layer, ECD Cu, and overburden CMP. To optimize the hybrid bonding quality, both silicon wafers were electroplated with 3-μm-thick Cu and then 2-μm-thick Sn for fabricating bumps with surrounding 4-μm-thick BCB. After the two wafers were face-to-face Cu/Sn-BCB hybrid bonded at 250 ◦C for 30 min under a contact force of 5000 mbar and a vacuum pressure of 10−3torr, the top wafer was thinned down to 40 μm, followed by CMP to expose Cu TSVs. Finally, the wafer backside was covered with passivation polyimide (PI), Ti adhesion layer, and backside RDL to complete this wafer-level 3-D integration hybrid scheme. Table I lists the dimension and design of the TSV parameters, including via diameter, pitch, and TSV depth, used in this study.
436 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 3, MARCH 2013
Fig. 1. (a) SEM image of the backside RDL and Cu TSV (5-μm diameter and 40-μm depth), (b) schematic diagram of the leakage current path, (c) I–V characteristics of Cu TSVs without process improvement, and (d) the leakage current location investigation of Cu TSV by OBIRCH analysis.
III. RESULTS ANDDISCUSSION
Fig. 1(a) shows the SEM image of the RDL and Cu TSV junction area. Passivation PI which provides the electrical iso-lation is patterned around Cu TSV. However, the large opening of passivation PI creates an unexpected contact area between the Ti adhesion layer of RDL and the Si substrate. As shown in Fig. 1(b), TSV leakage can be regarded as the injection current passing through the Ti/Si junction and forwarding toward the horizontal direction until it reaches another side. The following equations can theoretically express the overall resistance in series and the transport current [11]:
Rtotal= rD+ RS = A∗·∂JMS ∂V −1 + RS (1) JMS = JS exp qV ηkT − 1 . (2)
Herein, rDis the Ti/Si junction resistance, A∗ is the effective
junction area of adhesion Ti overlaying, RS is the series
resis-tance of the current path under the isolation layer, and JSis the
reverse-saturation current density [11].
An Agilent 4156C precision analyzer collocated with a two-point SMU system was applied on one Cu TSV with voltage sweeping from the ground to Vdd (0–5 V), while the leakage current in the neighbor Cu TSV was simultaneously measured. The I–V characteristics of the TSV leakage with 5- and 10-μm diameters for different pitches are summarized in Fig. 1(c). It could be readily seen that the larger pitch of both two TSV sizes in the I–V plot exhibits the same decreased shift of the leakage current in the voltage region from 2 to 5 V, and the result of the 5-μm TSV is slightly lower than that of the 10-μm one. Moreover, no matter how the TSV size or pitch changes, the current always initially increases exponentially at low applied voltage and then becomes linear when the voltage is larger than
Fig. 2. Electrical characterization of the 3-D integration scheme: (a) Two dominations of the R–V characteristics, (b) I–V characteristics of the structure using the improved process, and (c) SEM image of the structure using the improved backside process.
2 V. However, the large TSV leakage current (> 3 μA at 5 V) injection into the substrate may cause large thermionic noise to interfere the property of device operation.
Since the scant information in the I–V curve cannot explain its real transport behavior, location, path flow, and related parameters, OBIRCH analysis was applied to investigate the leakage current location, as shown in Fig. 1(d). As the applied voltage reaches 3 V, thermal sensitive laser points out that the accurate locations of leakage current are at corner junctions of the Cu TSV and backside RDL. It also indicates that the possible discharge path in this 3-D integration structure comes from the contact area of Ti from the RDL and the Si substrate, as shown in Fig. 1(b).
To further explore the mechanism of TSV leakage, one 50 μm× 50 μm Ti/Si metal–semiconductor junction was fab-ricated, and then, its normalized I–V characteristics were mea-sured, as shown in Fig. 1(c). The behavior of this Ti/Si junction can simulate the impact of the induced junction leakage current in TSV. Based on the characteristics of the fabricated metal-semiconductor Ti/Si junction, the TSV leakage should increase exponentially with the corresponding built-in VD= 0.6 V.
The R–V characteristics of the fabricated Ti/Si junction and Cu TSVs with different sizes/pitches can be obtained by the inverse of differential I–V , as shown in Fig. 2(a). All the TSV leakage curves present two main regions. It can be clearly inspected that, under low applied voltage, the large resistance of the Ti/Si metal-semiconductor junction results in an initial large TSV resistance. As the voltage increases, the resistance of the Ti/Si metal-semiconductor junction exponentially de-creases. The effect of rD becomes minor, while the constant RS dominates the TSV leakage. Table I also lists the effective
CHANG et al.: BACKSIDE-PROCESS-INDUCED JUNCTION LEAKAGE AND PROCESS IMPROVEMENT OF Cu TSV 437
Fig. 3. XTEM images in the middle of the TSV at (a) the copper side and (b) silicon side.
junction area (A∗) of the TSV leakage and the pitch-relative RS
extracted by using (1) and (2), respectively.
In order to decrease the leakage current, the adhesion layer of the Ti overlaying area A∗, which may come from overbur-den CMP, passivation PI, and backside Cu RDL, should be minimized. One improved fabrication using Si recessed and modified backside process can effectively achieve almost zero leakage current in this 3-D integration scheme. This modified approach has narrower via opening and thicker passivation PI layer. Fig. 2(b) shows the I–V characteristics of the modified 3-D integration with different TSV sizes. All TSVs with the modified backside process have extremely low leakage current of 20 pA at 5 V, showing an excellent isolation property. In addition, Fig. 2(c) shows no Ti overlaying on Si in the TSV and RDL region using the modified backside process.
Cu TSV using the improved fabrication process was also in-vestigated at different locations to ensure the overall insulation and filling quality. Fig. 3(a) and (b) shows the XTEM images in the middle of the TSV. There are no visible stacking fault around scalloped silicon and crack in the oxide liner, indicating that the leakage current inside the TSV should be extremely low, which is consistent with the measurement results.
IV. CONCLUSION
In this letter, the backside-process-induced TSV leakage current in the 3-D integration scheme with Cu TSVs and
Cu/Sn–BCB hybrid bonding has been investigated. The leakage current was inspected by OBIRCH analysis and compared with the typical Ti/Si metal–semiconductor junction current. These results identified the leakage location and proved the mechanism proposed. One improved process was employed in Cu TSVs, showing extremely low leakage current without visible defects. The improved Cu TSV scheme provides the fabrication feasibility in 3-D integration applications.
REFERENCES
[1] S. Koester, A. Young, R. Yu, S. Purushothaman, K. N. Chen, D. La Tulipe, N. Rana, L. Shi, M. Wordeman, and E. Sprogis, “Wafer-level 3D integration technology,” IBM J. Res. Develop., vol. 52, no. 6, pp. 583–597, Nov. 2008.
[2] C. T. Ko and K. N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectron. Reliab., vol. 50, no. 4, pp. 481–488, Apr. 2010.
[3] J. Q. Lu, “3-D hyperintegration and packaging technologies for micro–nano systems,” Proc. IEEE, vol. 97, no. 1, pp. 18–30, Jan. 2009.
[4] R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proc. IEEE, vol. 94, no. 6, pp. 1214–1224, Jun. 2006.
[5] K. N. Chen, S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y. M. Lin, J. Q. Lu, A. M. Young, M. Ieong, and W. Haensch, “Structure, design and process control for Cu bonded interconnects in 3D integrated circuits,” in Proc. IEDM, San Francisco, CA, Dec. 2006, pp. 1–4.
[6] T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, “New 3-D integration technology using self-assembly technique,” in IEDM Tech.
Dig., Washington, DC, Dec. 2005, pp. 348–351.
[7] R. Yu, F. Liu, R. Polastre, K. N. Chen, X. Liu, L. Shi, E. Perfecto, N. Klymko, M. Chace, and T. Shaw, “Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding,” in VLSI
Symp. Tech. Dig., Honolulu, HI, Jun. 2009, pp. 170–171.
[8] J. McMahon, E. Chan, S. Lee, R. Gutmann, and J. Q. Lu, “Bonding interfaces in wafer-level metal/adhesive bonded 3D integration,” in Proc.
58th ECTC, Lake Buena Vista, FL, May 2008, pp. 871–878.
[9] C. T. Ko, Z. C. Hsiao, Y. J. Chang, P. S. Chen, Y. J. Hwang, H. C. Fu, J.-H. Huang, C.-W. Chiang, S.-S. Sheu, Y.-H. Chen, W.-C. Lo, and K.-N. Chen, “A wafer-level three-dimensional integration scheme with Cu TSVs based on microbump/adhesive hybrid bonding for three-dimensional memory application,” IEEE Trans. Device Mater. Rel., vol. 12, no. 2, pp. 209–216, Jun. 2012.
[10] Y.-J. Chang, C.-T. Ko, and K.-N. Chen, “Electrical and reliability in-vestigation of Cu TSVs with low-temperature Cu/Sn and BCB hybrid bond scheme,” IEEE Electron Device Lett., vol. 34, no. 1, pp. 102–104, Jan. 2013.
[11] S. M. Sze, Physics of Semiconductor Devices. Hoboken, NJ: Wiley, 1981.
