A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film

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A physical model for the hysteresis phenomenon of the ultrathin ZrO 2 film

J. C. Wang, S. H. Chiao, C. L. Lee, T. F. Lei, Y. M. Lin, M. F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang

Citation: Journal of Applied Physics 92, 3936 (2002); doi: 10.1063/1.1498964

View online: http://dx.doi.org/10.1063/1.1498964

View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/92/7?ver=pdfcov

Published by the AIP Publishing

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A physical model for the hysteresis phenomenon of the ultrathin

ZrO

2

film

J. C. Wang, S. H. Chiao, C. L. Lee,a) and T. F. Lei

Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, Republic of China

Y. M. Lin, M. F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang

Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, Republic of China 共Received 4 March 2002; accepted for publication 12 June 2002兲

This work studies and presents an inner-interface trapping physical model for the ultra-thin

共effective oxide thickness⫽15 Å兲 zirconium oxide 共ZrO2兲 film to explain its hysteresis phenomenon. The shift of the capacitance–voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination 共⬃45 mV兲. The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance–voltage characteristics and the different turn-around voltages of the current density–voltage characteristics of the zirconium dielectrics. © 2002 American Institute

of Physics. 关DOI: 10.1063/1.1498964兴

I. INTRODUCTION

For the very deep submicron complementary metal– oxide–semiconductor 共CMOS兲 device, the international technology roadmap for semiconductors共ITRS兲 predicts that a sub-16 Å silicon dioxide gate dielectric is needed for the sub-0.1␮m CMOS device.1A SiO2 gate oxide of that thick-ness has been shown to have a leakage current of the range of 1–10 A/cm2.2,3 Recently, there was much work4 –16 on studying ZrO2to replace SiO2as the gate dielectric due to its high dielectric constant 共⬃25兲, wide energy bandgap 共⬃7.8 eV兲,8high stability with the Si surface,17and low post depo-sition annealing temperature 共⬃500 °C兲.4Its electrical prop-erties were also reported to be good enough as the candidate for the gate dielectrics for the deep sub-micron device.

Unfortunately, for ZrO2, there is the hysteresis phenomenon in its capacitance–voltage 共C–V兲 characteristics.11,13,14,18 This hysteresis will induce a flat-band voltage shift, consequently a threshold voltage instabil-ity when it is applied to the MSO field-effect transistor as the gate dielectrics. It was reported that the hysteresis phenom-enon might be due to chemical contaminations, the stress-induced defect formation, or mobile ions.19 In this article, this phenomenon is studied and an inner-interface trapping model is presented to explain it.

II. EXPERIMENT

Al/TiN/ZrO₂/Zr-silicate/p-Si capacitors with an area of 7.85⫻10⫺5 cm2 were fabricated on 8-in. p-type Si wafers. First, the ZrO2 film of 50 Å was deposited by atomic layer chemical vapor deposition, which was performed at a tem-perature of 300 °C and a pressure of about 1 Torr. The pre-cursors used for the deposition were ZrCl4 and H2O. After

the gate dielectric was formed, a TiN film of 250 Å was deposited by metal organic chemical vapor deposition. The sample was then annealed in the furnace for 10 min in an N2 ambient at 400 °C. A 5000 Å Al film was deposited on the wafer by a thermal coater. After that, the gate of the capacitor was defined lithographically and etched. Finally, a 5000 Å Al film was also deposited on the back side of the wafer to form the ohmic contact. The effective oxide thickness共EOT兲 was estimated by the high frequency 共0.1 MHz兲 C–V in the strong accumulation region without considering quantum mechanical effects. Moreover, the physical thickness was checked by a transmission electron microscopy 共TEM兲 to obtain the dielectric constant. The electrical properties were

a兲_{Electronic mail: [email protected]}

FIG. 1. Plots of negative current density vs voltage characteristics of the zirconium dielectrics, where the inset shows the high frequency capacitance vs voltage characteristics with the voltage swept from inversion to accumu-lation.

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measured by using an HP 4156B semiconductor parameter analyzer and an HP4284A precision LCR meter.

III. RESULTS AND DISCUSSION

Figure 1 shows the negative current density–voltage

共J–V兲 characteristics, where the inset shows the high

fre-quency C–V characteristics swept from inversion to accumu-lation, of the fabricated ZrO₂film, for which the EOT value derived is 15 Å. The TEM micrograph of the cross section of the film is shown in Fig. 2, where the physical thickness was measured to be 53.7 Å. In the TEM picture, it is also ob-served that there exists an interfacial layer of about 10 Å, referred as Zr-silicate,20 at the ZrO2/Si interface. It is be-lieved that this silicate layer plays an important role in cre-ating the hysteresis observed in the zirconium dielectrics as explained later. The effective dielectric constant derived based on the physical thickness, including the interfacial Zr-silicate layer, is larger than 20. The sample shows a leakage current density lower than 10⫺6A/cm2 at Vg⫽⫺1 V, which is comparable with the values reported before.4 –7 Figure 3 shows the measured time-to-breakdown 共TBD兲 data of the dielectrics at room temperature and 150 °C respectively, and

FIG. 2. TEM image of the zirconium dielectrics.

FIG. 3. The measured TBDdata of the sample at room temperature and the

150 °C respectively, and the derived TBDdata for the scaled area of 0.1 cm2

and the 0.01% failure rate for the samples.

FIG. 4. 共a兲 Hysteresis phenomenon of the zirconium dielectrics sweeping from accumulation 共solid line兲 and from inversion 共dashed line兲 without light illumination.共b兲 Hysteresis phenomenon of the zirconium dielectrics sweeping from accumulation with 共dashed line兲 and without 共solid line兲 light illumination. The hysteresis phenomenon sweeping from inversion is in inset.

FIG. 5. High frequency capacitance vs voltage distortion under bias-temperature stress of the zirconium dielectrics, where the inset shows the enlargement between 50 to 100 pF.

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the derived T_BDdata for the scaled area of 0.1 cm2 and the 0.01% failure rate for the samples.21,22In the above, the data for the area scaling and the 0.01% line were derived from the Weibull distribution of the 150 °C data assuming a random distribution of breakdown sites.23The derived maximum op-erating voltage could be, in these conditions, as high as 1.6 V, which is much higher than 1 V for the sub-0.1␮m device as obtained from the ITRS roadmap.

Figure 4共a兲 shows the hysteresis in the C–V characteris-tics of the sample without light illumination. The solid line is

FIG. 6. 共a兲 Inner-interface trapping model of the zirconium dielectrics sweeping from accumulation共Vg⫽⫺2.0 V兲 without light illumination. 共b兲

Inner-interface trapping model of the zirconium dielectrics sweeping from inversion共Vg⫽⫹1.0 V兲 without light illumination. 共c兲 Inner-interface

trap-ping model of the zirconium dielectrics sweetrap-ping from inversion 共Vg ⫽⫹1.0 V兲 with light illumination.

FIG. 7. Hsyteresis phenomenon of the zirconium dielectrics sweeping from accumulation for the thinner zirconium oxide共solid line兲 and thicker one 共dashed line兲 without light illumination.

FIG. 8. 共a兲 Absolute values of the current-density vs voltage characteristics sweeping from accumulation to inversion.共Turn-around voltage⫽⫺0.4 V兲. 共b兲 Absolute values of the current-density vs voltage characteristics sweep-ing from inversion to accumulation.共Turn-around voltage⫽⫹0.5 V兲.

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the C–V characteristics for measuring the curve by sweeping the voltage from accumulation to inversion and then sweep-ing back 共⫺2.0 V⇒⫹1.0 V⇒⫺2.0 V兲. A shift of about 45 mV is observed. The dashed line is the curve measured by sweeping from inversion to accumulation and then sweeping back. A shift of 45 mV is also observed. However, when light was applied during the measurement, the shift increased to 110 mV, as shown in Fig. 4共b兲. To explore the reason for this phenomenon, a bias temperature stress 共BTS兲 of Vg

⫽⫾0.7 V, 125 °C for 30 min was applied to the sample. For

BTS of both positive and negative polarities, as shown in Fig. 5, no significant C–V curve shifts were observed. It was concluded that the hysteresis phenomenon was not caused by the mobile ion effect.

As revealed by the TEM picture of Fig. 2, there exists a thin silicate layer between the ZrO2and silicon substrate. An energy band diagram of the TiN/ZrO2/Zr-silicate/p-Si struc-ture was recently reported.24 Due to the imperfect structure of the interface between the ZrO₂and Zr-silicate, it would be expected that this interface would act as charge trapping cen-ters. Therefore, an inner-interface trapping model as shown in Fig. 6 is proposed to explain the hysteresis phenomenon. When the capacitor is first at accumulation 共Vg⫽⫺2.0 V兲, majority carriers 共holes for the p-type Si substrate兲 tunnel from p-Si substrate through the Zr-silicate layer and are trapped at the inner-interface, as shown in Fig. 6共a兲. When the voltage is swept toward the positive direction, the C–V curve shifts negatively. Then, when the voltage is swept to the positive side to make the capacitor stay at inversion

共Vg⫽⫹1.0 V兲, the trapped holes at the inner-interface will be de-trapped and at the same time minority carriers 共elec-trons兲 will tunnel from the p-Si substrate and trapped at the inner-interface, as shown in Fig. 6共b兲. This makes the C–V curve shift positively when the voltage is swept toward the negative side. The mechanism makes the C–V curve have a hysteresis loop. As a light illumination is applied to the semi-conductor, electron–hole pairs will be generated 关see Fig. 6共c兲兴, which make the above phenomenon more evident. Es-pecially, the light illumination makes a more significant ef-fect on minority carriers as seen from Fig. 4共b兲, where a larger voltage shift of 110 mV was observed for the voltage sweeping from inversion toward accumulation. The change on the majority carrier concentration was insignificant, thus making almost the same C–V curve as the voltage was swept from accumulation toward inversion.

Figure 7 shows the C–V curve shifts for two different thicknesses of the zirconium dielectrics. It shows that the thicker zirconium dielectric 共dashed line兲 has a larger C–V curve voltage shift共100 mV兲 than that 共45 mV兲 of the thin-ner. Based on our proposed model, as the thickness of the zirconium dielectrics increases, the relative distance of the inner-interface as compared to the total thickness of the di-electrics will be closer to the silicon substrate, resulting more shift of the C–V curve. Figures 8共a兲 and 8共b兲 show the ab-solute current density–voltage 共兩J兩–V兲 characteristics of the dielectrics measured with the voltage swept from accumula-tion to inversion and from inversion to accumulaaccumula-tion respec-tively. For Fig. 8共a兲, the current is negative and becomes positive at the gate voltage equaling ⫺0.4 V, but for Fig.

8共b兲, the current is positive and becomes negative at the gate voltage equaling ⫹0.5 V. This difference in the turn-around voltages of the current can also be explained by using the inner-interface trapping model. As the capacitor is at the ac-cumulation region, holes are trapped at the inner-interface

关see Fig. 6共a兲兴, making the turn-around voltage of the current

be at ⫺0.4 V when the gate voltage is swept toward the inversion region; while as the capacitor is at the inversion region, electrons are trapped at the inner-interface 关see Fig. 6共b兲兴, making the turn-around voltage of the current be at

⫹0.5 V when the gate voltage is swept towards

accumula-tion.

IV. CONCLUSION

In conclusion, the hysteresis phenomenon of the zirco-nium dielectrics can be explained by using an inner-interface trapping model. The influence of light illumination on the hysteresis phenomenon is quite serious because of more charges trapped at the ZrO₂/Si-silicate interface. The model well explains not only the hysteresis effect but also the thick-ness effect of the C–V characteristics and the different turn-around voltages on the J–V characteristics of the zirconium dielectrics capacitor.

ACKNOWLEDGMENTS

The authors would like to thank ASM Far East Market-ing Ltd. and National Nano Device Laboratory, ROC, for their technical help, and National Science Council, ROC, for their financial support under Contract No. NSC90-2215-E009-070.

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