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A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped
Polycrystalline Silicon Nanowires
View the table of contents for this issue, or go to the journal homepage for more 2013 Jpn. J. Appl. Phys. 52 04CC18
(http://iopscience.iop.org/1347-4065/52/4S/04CC18)
A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped
Polycrystalline Silicon Nanowires
Horng-Chih Lin1;2, Zer-Ming Lin1, and Tiao-Yuan Huang1
1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan 2National Nano Device Laboratories, Hsinchu 300, Taiwan
E-mail: [email protected]
Received September 21, 2012; accepted December 15, 2012; published online March 21, 2013
In this study, we proposed a new methodology for probing the electrical properties of heavily doped polycrystalline silicon (poly-Si) nanowires (NWs), including active doping concentration, mobility, and interface fixed charge density. Implementation of this procedure is based on the modulation of the device operation of a gate-all-around (GAA) junctionless (J-less) transistor from the gated resistor mode to the ungated one. The extracted carrier concentration in the NW is found to be much lower than that of Hall measurements, while a negative fixed charge density is identified with the procedure. Dopant segregation at the oxide interface is postulated to be closely related to these observations.
# 2013 The Japan Society of Applied Physics
1. Introduction
Recently, junctionless (J-less) transistors, which have a degenerately doped channel with a doping type identical to that of the source/drain (S/D), have been proposed as an alternative candidate in the manufacturing of extremely scaled metal–oxide–semiconductor (MOS) devices,1,2) as well as three-dimensional (3D) stacked NAND Flash memory.3)Such a scheme is not only free from the difficulty in forming shallow and uniform S/D junctions but also shows much reduced parasitic series resistance.1,2) This is especially important for the 3D architectural Flash memory schemes3,4) whose S/D doping process is difficult to ac-complish with the implant technique. An additional unique feature of the 3D memory structure is the utilization of a polycrystalline silicon (poly-Si) layer as the channel material. In this regard, a novel implantation-free gate-all-around (GAA) poly-Si nanowire (NW) J-less transistor has recently been developed by our group.5)In this architecture,
the complexity of the process could be greatly simplified because the implantation is skipped by employing a heavily in situ phosphorous-doped S/D and channel simultane-ously formed by low-pressure chemical vapor deposition (LPCVD), making it very attractive for 3D electronics integration. To optimize the device performance, assessment of the values of active doping concentration and mobility of the in situ doped poly-Si NW is essential. Conventional techniques such as Hall measurement, four-probe technique, and secondary ion mass spectrometry (SIMS) have been widely adopted to characterize the doping properties of poly-Si films.6–8)However, these methods may not be appropriate for the poly-Si NW structure, as they do not take into account the effects drawn by the surface of the NW and dopant segregation.9) In one of the previous works,10) the
active doping concentration of in situ phosphorous-doped Si NWs was studied. However, the value of mobility used in the analysis for extracting the carrier concentration was approximated by the result of the Hall measurement, leading one to question the accuracy of the analysis. In this work, we propose a new methodology to extract major parameters, such as the active doping concentration and mobility of the NW channel as well as the fixed-charge density of NWs, based on the concept of the switching in device operation
characteristics between gated- and ungated-resistor behav-iors of J-less transistors.
The remaining part of this paper is organized as follows: In Sect. 2, we present the impact of NW cross-sectional area on the device characteristics and discuss the operation of the J-less devices, including the interesting leaky characteristics of the NW devices with a rather large cross-sectional area. Then, a theoretical model is detailed in Sect. 3 to establish the relations among different parameters. In Sect. 4, the above theoretical background is verified with experimental results. A method for determining the gate voltages corresponding to the switching of transport behaviors is also presented. Results of the major parameters extracted by the developed procedure are further discussed. Finally, Sect. 5 summarizes the major contributions and observations of this work.
2. Impact of the Cross-sectional Area of Nanowires Figure 1 schematically shows the transfer curve of a GAA n-channel J-less transistor. For simplicity, the cross section of the NW channel is assumed to be round, with a suffi-ciently large diameter so that it will not be fully depleted
VFB Depletion region
Quasi neutral region
xdepl< xm xdepl= xm
Gate Voltage, V
GDrain Current
, I
D VG1Fig. 1. (Color online) Schematic illustration of the transfer characteristics of a GAA J-less transistor with a rather thick round NW channel. The device is normally on due to the high channel doping and the drain current starts to decrease as the gate voltage decreases from VFBdue to the formation of a
surface depletion layer with a width of Xdepl. However, the current will
reach a lower bound as Xdepl reaches a maximum value Xm.
even if a highly negative gate voltage is applied (see discussion later). Certainly, the operation of the device is quite different from that of conventional inversion mode transistors considering the channel doping, which is very high and of the same type as that of the source and drain. Such a feature is structurally similar to the accumulation-mode (AM) devices.11–14)However, although bearing some
resemblance to the AM device at first glance, the J-less device is actually quite different in terms of the operation characteristics. Specifically, conventional AM transistors usually adopt a channel doping concentration (e.g.,4 1016 and 5 1017cm3)11,12) far lower than that of the S/D region, albeit with the same doping type. So, as the device is turned on, the drain current (ID) conduction takes place in an accumulation layer (carrier concentration typically= 1019cm3 channel doping) formed in the channel surface near the oxide interface. In contrast, the channel doping concentration of J-less devices is typically about or higher than 1 1019cm3,1,2) making the operation distinctly different from those of conventional AM and inversion-mode (IM) devices. This can be understood from Fig. 1 in which the flat-band voltage (VFB) corresponds to a point in the transfer curve in the regime of the on-state operation.15)
As the gate voltage (VG) decreases from VFB, a surface depletion region starts to form in the NW channel, so the NW can be roughly divided into the surface depletion and quasi neutral regions, as shown in Fig. 1. Note that, because of the high carrier concentration in the quasi neutral region, the current conduction of the J-less devices is mainly through the channel body rather than being confined to a region near the oxide interface, in strong contrast to that of the AM devices.
As VGfurther decreases, the depletion region is widened and thus leads to a reduction in IDowing to the shrinkage of the effective conduction area (i.e., the quasi neutral region) of the channel. This implies that the off-state current of the J-less devices is strongly dependent on the cross-sectional feature size of the NW channel. Specifically, if the NW size is not small enough to allow full depletion of the NW by the highly negative gate bias, the lower bound of the leakage current will be set by the component conducting through the quasi neutral region remaining in the core of the NW channel, as shown in Fig. 1. Another fact that should be noted is that the voltage drop in the depletion region of a heavily doped semiconductor is limited by its band gap.16) For heavily doped Si, the band gap is about 1 eV.17) This means that the width of the depletion region (Xdepl) has an upper limit. As a result, a rather thick NW channel will not be fully depleted even under a highly negative gate bias, and the quasi neutral region remaining in the middle of the channel continues to allow current to conduct through. This occurs as VG reduces to a specific value denoted as VG1 in Fig. 1, where Xdeplreaches its maximum (Xm). In the regime VG< VG1, the quasi neutral region becomes ‘‘ungated’’ since its cross-sectional area is basically no longer affected by the gate bias. As a result, the leakage current remains constant in this regime, as shown in Fig. 1. To effectively shut down the conduction when the device is off, the quasi neutral region in the channel core should be eliminated. This explains why a J-less device demands its channel to be ultrathin or tiny to acquire a high on/off current ratio in operation.1,2,5)
None-theless, the methodology developed in this work shows that useful information is still contained in the leakage characteristics of J-less devices with a rather thick channel body.
To confirm the aforementioned inferences, we character-ize the GAA J-less transistors with in situ phosphorous-doped poly-Si NW channels of different cross-sectional areas. The 3D schematic structure and top view of the fabricated GAA J-less transistors are shown in Figs. 2(a) and 2(b), respectively. As can be seen in the figures, a pair of nþ poly-Si NW channels is gated with an nþ poly-Si gate thus normally-on device characteristics are expected. The fabrication flow of the characterized devices is described in Ref.5. In this work, two types of device with different cross-sectional NW dimensions were fabricated and char-acterized. Figure 3 shows the cross-sectional scanning electron microscopy (SEM) image of one of them, denoted as Device A, which has a rectangular-shaped cross section with an area of 70 27 nm2. Figure 4(a) compares the transfer characteristics of Device A with those of a device (denoted as Device B) characterized in the previous work5) with a much smaller cross-sectional area of approximately 23 12 nm2. The strong impact drawn by the NW size can be clearly seen in Fig. 4(a). Device A shows very leaky characteristics and unapparent switching behavior. In contrast, sharply off characteristics are observed for Device B, and the minimum ID of the transfer curves in the off-state regime is comparable to or lower than the
Si Substrate Thermal Oxide
Gate
Doped Poly-Si NW ChannelDrain
Source
(a) Source Drain N+Poly-Si Gate Doped poly-Si NW channel wrapped by the gate A B D C (b)Fig. 2. (Color online) (a) Stereo and (b) top views of the fabricated GAA J-less poly-Si NW transistor. In the top view, the NW channels wrapped by the gate are intentionally shown.
H.-C. Lin et al. Jpn. J. Appl. Phys. 52 (2013) 04CC18
sensitivity (1013A) of the measurement system. Such a finding is reasonable considering the fact that the tiny NW size of Device B allows the effective depletion of the whole channels and thus the complete shut-down of the current conduction when the device is off.1,2)
To confirm the existence of the ungated region in the operation of the device with sufficiently large NWs, the ID–VG characteristics of Device A, measured in a highly negative VG regime at VD ranging from 0.25–1.25 V are shown in Fig. 4(b). In the figure, as expected, two distinct regions can be identified and divided by VGat9:1 V, which is denoted as VG1 in Fig. 1. (Precise determination of VG1 is given in Sect. 4.) As VG is smaller than 9:1 V, ID is essentially independent of VG and linearly proportional to VD. These features indicate that the conduction is resistor-like and no longer governed by the applied gate bias.
Although Device A with wider poly-Si NW channels could not be turned off effectively, its transfer characteristics are cleverly analyzed to acquire the active doping concen-tration and mobility of the in situ phosphorous-doped poly-Si NWs. Details about the methodology including theoretical analysis and experimental verification are elaborated in the next sections.
3. Theoretical Background
The cross-sectional view of the device along line A–B shown in Fig. 2(b) is plotted in Fig. 5, where H, W, EOT, and n denote the height, width, effective oxide thickness, and active doping (or carrier) concentration of the heavily phosphorous-doped poly-Si NW channel, respectively. As has been pointed out in the discussion of Fig. 1, a surface
depletion region exists as VGis smaller than VFB. Owing to the rather thick structure and the heavy channel doping, the investigated Device A is partially depleted during off-state operation and the maximum depletion width Xmis expected to be much smaller than both H and W. This allows us to use the 1D Poisson’s equation to calculate the electric potential in the depletion region at a position far from the corners shown in Fig. 5. The 1D Poisson’s equation along the x-direction [Fig. 2(b)] is expressed as
d2ðxÞ dx2 ¼
qn "Si
; ð1Þ
where is the electric potential, "Siis the dielectric constant of silicon, and q is the electric charge. In Fig. 5, x ¼ 0 corresponds to the interface between the top gate oxide and the NW channel. The two boundary conditions applied for solving Eq. (1) are listed below:
Eðx ¼ XdeplÞ ¼ 0; ð2Þ
ðx ¼ XdeplÞ ¼ 0; ð3Þ
where Eðx ¼ XdeplÞ and ðx ¼ XdeplÞ are the electric field and electric potential, respectively, at the edge of the depletion region. Here, we assume that the applied VD is
27nm
70nm
Device A
NW
Fig. 3. (Color online) Cross-sectional SEM image of Device A along line AB shown in Fig. 2(b). This device has a rectangular-shaped cross section with an area of70 27 nm2. VD=0.1,1 V LG=5µµm VG(V) -2 -1 0 1 2 3 I D (A) 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 Device B 23 × 12 nm2 EOT = 10 nm Device A 70 × 27 nm2 EOT = 18 nm (a) Device A VD=0.25~1.25 V VG(V) -12 -10 -8 -6 -4 -2 0 2 4 I D (A) 0 1x10-6 2x10-6 3x10-6 4x10-6 5x10-6 6x10-6 VG1= -9.1 V (0.25 V per step) (b)
Fig. 4. (Color online) (a) ID–VGcharacteristics of Devices A and B.
Device B has a much smaller cross-sectional area of around23 12 nm2.5) (b) Transfer characteristics of Device A measured at various VDvalues. The
small, so its impact on the potential and electric field is negligible. By applying the two boundary conditions to solve Eq. (1), the solution of electric potential can be expressed as ðxÞ ¼ qnXdepl "Si x qnðx 2þ Xdepl2Þ 2"Si ; 0 < x Xdepl: ð4Þ To turn off an n-channel J-less transistor, the gate bias is decreased to increase Xdepland thus decreases the area of the quasi neutral region in the NW core available for current conduction. As mentioned above, Xdepl is limited by the maximum voltage drop in the NW, which is close to the band gap of Si.16)The maximum depletion width, Xm, and the gate voltage as Xmis reached, VG1, can be expressed as follows:17) Xm¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2"SiE g=2 þ kT =q lnðn=niÞ qn s ; ð5Þ VG1¼ VFB qnXm Cox Eg 2 þ kT q ln n ni ; ð6Þ VFB¼ Eg 2 kT q ln n ni Qfix Cox ; ð7Þ
where Qfix, Cox, ni, Eg, and kT =q are the fixed charges at the oxide/channel interface, gate oxide capacitance per unit area, intrinsic carrier concentration, silicon band gap, and thermal energy at room temperature, respectively. As VGis more negative than VG1, Xmis reached and retained. In other words, the device operation changes from a gated resistor (as VG> VG1) to an ungated one (as VG< VG1) in which the current flow is conducted through the quasi-neutral core region with a conduction area not affected by the gate bias. Figure 6 shows the cross section along the C–D cutline (i.e., along the source-to-drain direction) in Fig. 2(b) showing the situation as Xm is reached. For a long-channel device operated at a low VD, Xmshould be quite uniform across the channel and, from Fig. 5, the area for the leakage current of the ungated resistor to conduct can be approximated as H W 2ðH þ WÞXmþ 4Xm2. Thus, the resistance of the ungated resistor, R, can be expressed with the following form: R ¼ VD ID ¼ L nqðH W 2ðH þ WÞXmþ 4Xm2Þ ; ð8Þ where is the effective mobility. R can be obtained from the information contained in the ungated operation regime, i.e., VG< VG1.
4. Experimental Verification and Discussion
In Fig. 4(b), more precise determination of VG1 could be achieved by plotting the transconductance (Gm) as a function of VG, and the results are shown in Fig. 7. Since Gmis the differentiation of IDto VG, it should suddenly drop to zero when the conduction of the device transfers from gated- to ungated-resistor behavior. This transition indeed occurs in the figure, and VG1 can be extracted as the gate voltage when Gm drops to zero, which is 9:1 V in this case. Moreover, VFB can also be determined as the gate voltage corresponding to the Gm peaks in Fig. 7. The major reason is as follows. As mentioned above, the depletion region exists as VG is smaller than VFB, and contributes to the additional equivalent oxide thickness (EOTdepl) of the gate dielectric:16)
EOTdepl¼X depl"SiO2
"Si : ð9Þ
N+Poly-Si Gate
Gate oxide (EOT=18nm)
x N+Poly-Si NW (electron concentration n) Xdepl(VG) W H y
Fig. 5. (Color online) Schematic illustration of the cross-sectional structure of the GAA J-less transistor when VG< VFBalong line AB shown
in Fig. 2(b). Source Drain N+Poly-Si Gate Gate Insulator N+Poly-Si Gate Gate Insulator Xm
Fig. 6. (Color online) Schematic illustration of the cross-sectional structure of the GAA J-less transistor when VG< VG1along line CD shown
in Fig. 2(b). Device A VD=0.25~1.25V VG(V) -12 -10 -8 -6 -4 -2 0 2 4 Gm(S) 0 200x10-9 400x10-9 600x10-9 800x10-9 1x10-6 VG1=-9.1 V VFB=2.88 V (0.25V per step)
Fig. 7. (Color online) Gmversus VGfor Device A measured at various
VDvalues. VG1and VFBcan be precisely determined from the plots.
H.-C. Lin et al. Jpn. J. Appl. Phys. 52 (2013) 04CC18
The additional EOT contributed by Xdepl decreases with increasing VG, one of the two major reasons responsible for the increase in Gm as VG< VFB. The other reason is the increase in the conduction area of the quasi neutral region. When VFB is reached, the two mechanisms quench. The further increase in IDwhen VG is larger than VFB is due to the conduction through the surface accumulation layer and the conduction has a much weaker dependence on VG as compared with the aforementioned two mechanisms. There-fore, the peak of Gm is resulted at VFB. From Fig. 7, it is seen that the VG corresponding to Gm peaks shows a very weak dependence on the applied VD, and the corresponding VG (2.88 V) is determined to be VFB. With this value, a negative fixed charge density (Qfix) of 3:25 1012cm2 can be extracted from Eq. (7). Next, the active doping concentration (n) of the doped poly-Si NW can be extracted to be 1:18 1019cm3 by substituting the VG1 and VFB values into Eq. (6).
To extract R and , ID in Fig. 4(b) measured at VG¼ 10 V is re-plotted and shown as a function of VDin Fig. 8. In this figure, it can be seen that the current is proportional to the drain voltage and its slope, which is equal to 1=R, is 4:5 107A/V. On the basis of this result and Eq. (8), the mobility of the doped poly-Si NW of Device A is determined to be 52.5 cm2V1s1. Note that, on the basis of the extracted n value, the estimated Xm is around 10 nm, which is much smaller than W (¼ 70 nm) and H (¼ 27 nm) of the NW and supports the assumption made for the derivation of Eq. (8).
Table I lists the measured results from SIMS, Hall measurements, and the proposed methodology. Both SIMS and Hall measurements were performed on a 400-nm-thick blanket film. Note that the carrier concentration measured from Hall measurements is smaller than the dopant con-centration obtained from the SIMS analysis, indicating the occurrence of dopant precipitation and segregation. More importantly, the carrier concentration is further reduced in the NW sample. One possible explanation for this observa-tion is the segregaobserva-tion of phosphorous atoms to the oxide interface from the poly-Si NW.9,18) A reduction in the concentration of phosphorous in the Si material may also explain the increase in the effective carrier mobility of the NW sample as compared with the Hall mobility.
To further verify the accuracy of the methodology proposed in Fig. 7 for determining VFB, we simulate the electric potential across the middle of the NW along the y-direction (see Fig. 5) under various gate bias conditions with a TCAD tool.19) In the simulation, the n and Qfix extracted from the above procedure are taken into account and the results are shown in Fig. 9. It can be seen that the electric potential is almost flat at VG¼ 2:88 V, confirming the feature of flat-band condition. Note that the negative value of Qfix is reported for the first time. Certainly, its origin needs more efforts to be unveiled, but the aforemen-tioned segregation of phosphorous to the oxide interface should play an essential role in such a finding. Finally, although the NW material studied in this study is poly-crystalline in nature, there should be no doubt about the applicability of this scheme to monocrystalline NWs. 5. Conclusions
A simple procedure without a complicated or expensive measurement setup is proposed in this study to extract the major electrical properties of in situ phosphorous-doped poly-Si NWs, including the effective active doping con-centration, mobility, and interface fixed charge density. The principles of this methodology rely on the operation of a GAA J-less transistor with rather thick NW cross-sectional dimensions. Such a device exhibits an ungated operation behavior when gate bias is sufficiently negative, i.e., VG5 VG1, which is clearly observed in the practical measure-ments. Moreover, the gate voltage corresponding to VG1and VFB can be precisely determined from the Gm-vs-VG plots.
VD(V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID (A) 0 100x10-9 200x10-9 300x10-9 400x10-9 500x10-9 600x10-9 700x10-9 VG= -10 V Slope = 4.5 x 10-7A/V
Fig. 8. IDextracted from Fig. 4(b) at VG¼ 10 V as a function of VD.
VG= -3.12~4.88V (2V per step) X(µµm) 0.00 0.02 0.04 0.06 potential(V) 0.1 0.2 0.3 0.4 0.5 0.6 VD= 0.1V
V
G=V
FB=2.88 V
Fig. 9. (Color online) Simulated electric potential distributions in the middle of the NW along the y-axis at VD¼ 0:1 V and various VGvalues.
The result shown for VG¼ 2:88 V confirms the flat-band condition.
Table I. Results of SIMS, Hall measurements, and the proposed methodology.
SIMS Hall This work Test structure Blanket
thin filmaÞ Blanket thin filmaÞ NW J-less transistor Dopant or carrier concentration (cm3) 1020 7 1019 1:18 1019 Mobility (cm2V1s1) — 42.7 52.5 a) 400 nm thick.
Mobility could also be determined from the characteristics of the GAA J-less transistor operated in the ungated-resistor region. The extracted carrier concentration is significantly lower than that obtained from Hall measurements performed on blanket thin films. Segregation of phosphorous at the gate oxide/NW interface is postulated to be the major reason for the observed disparity. We have also identified the presence of negative fixed charges at the oxide interface, which is likely related to the dopant segregation as well.
Acknowledgments
The authors would like to thank the National Nano Device Laboratories (NDL) and the Nano Facility Center of the NCTU for assistance in device fabrication. This work was supported in part by the Ministry of Education in Taiwan under the ATU Program, and the National Science Council under contract No. NSC 99-2221-E-009-172 and No. NSC 99-2221-E-009-167-MY3.
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