116 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999
A Class-B Output Buffer for Flat-Panel-Display Column Driver
Pang-Cheng Yu and Jiin-Chuan Wu
Abstract— Due to the large number of output buffers on a
column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8-m CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5-V supply and 600-pF load, the maximum tracking error is67 mV. The measured static current is 24A. The settling time for 4-V swing to within 0.2% is 8s, which is more than adequate for driving 12802 1024 pixels liquid crystal displays with 86-Hz frame rate and 256 gray levels in each color.
Index Terms— Class-B amplifier, flat-panel display, output
buffer.
I. INTRODUCTION
T
HERE are three special requirements for the output buffer for a flat-panel-display column driver [1], [2]. First, a large number of output buffers are needed. For a 640 480 pixels color panel, the number of analog buffersneeded is . For a high-end 1280 1024
color panel, the number of output buffers is 3840. Many column-driver IC’s must be used to achieve the number of outputs needed. However, to reduce system cost and increase reliability, the total number of driver IC’s used should be minimized. Thus, the first requirement of the output buffer is that its die area must be minimized in order to put more output drivers on one chip. Second, since the liquid crystal displays (LCD’s) are commonly used in portable systems that are battery powered, the power dissipation must be minimized to extend the battery lifetime. Thus, the second requirement is low power dissipation. Third, the input to the output buffer is always step function because the pixels are updated row by row. The output voltage must settle within a horizontal scanning time. The horizontal scanning frequency ranges from 31.5 to 97.8 KHz. With stepwise input, the theoretical lower limit of the output buffer is 0.5 , where is the signal frequency, is the load capacitance, is the voltage swing of the column signal, and is the supply voltage. The power dissipation of a column driver is dependent on the image displayed. The maximum power dissipation occurs when the image on a column is alternating black and white pixel by pixel, i.e., both the frequency and the signal voltage
Manuscript received November 3, 1997; revised April 6, 1998. This work was supported by the National Science Council under Contract NSC86-2215-E-009-053 and by the Chip Implementation Center, Taiwan, R.O.C.
The authors are with the Integrated Circuit and Systems Laboratory, Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan 300 R.O.C. (e-mail: jcwu@alab.ee.nctu.edu.tw).
Publisher Item Identifier S 0018-9200(99)00407-2.
swing are maximum. On the other hand, when the image on a column is a constant gray level, the theoretical dynamic power is zero because both and are zero.
To reduce power dissipation, a class-A amplifier with vari-able bias current was used [3]. The amplitude of the output-stage bias current is controlled by a digital pulse. In the first one-third of the scan-line period, a large bias current is used to make sure the output is settled within this period. For the rest of the scan-line period, a much smaller bias current is used to hold the output value. However, when the gray level does not change much in a column, this scheme wastes too much power. A dynamic biasing technique [4] was proposed to increase the bias current of the differential input stage of a two-stage amplifier, when the input voltage difference is large. This technique does not reduce the output-stage bias current. A class-B amplifier [5], [6] has a better power efficiency. But the sizes of the output transistors are large because the gate-to-source voltages are smaller than the supply voltage. To reduce both die area and power dissipation, another scheme [7] precharges the output to the supply voltage at the beginning of each scan-line period. Then the output voltage is discharged toward 0 V, and the output voltage is compared with the input voltage using a comparator. The discharging stops when the output voltage is equal to the input voltage. This scheme has no static power and is compact. However, it wastes dynamic power when the gray level in a column does not change much. Furthermore, its final voltage is always smaller than the input, due to the finite response time of the comparator.
In this paper, a class-B CMOS output buffer is proposed because it has a better power efficiency. To reduce the size of the output stage, nonlinear elements (the comparators) are included in the series-shunt feedback path. In Section II, the output buffer design is described. The experimental results are shown in Section III. A conclusion is given in Section IV.
II. DESIGN OF BUFFER AMPLIFIER
Fig. 1 is the block diagram of the proposed class-B output buffer. It has a common source output stage, which offers good swing characteristics, high efficiency, and low nonlinear distortion. The basic structure of this buffer is not new [5], [6]. The main difference is that the error amplifiers in [5] and [6] are replaced by the comparators and an inverter, which are nonlinear. The comparators and inverter serve as series-shunt negative feedback to reduce the output resistance. The output of the comparator is designed to be either or 0 V, i.e., when the output transistor is turned on to charge or discharge the output node, the gate-to-source voltage is always . In this way, a smaller output transistor can be used. The two comparators, Cmp1 and Cmp2, are identical. For ease of discussion, assume that the offset voltages of the comparators are zero and that the process model is typical.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999 117
Fig. 1. Block diagram of class-B output buffer.
Fig. 2 shows the complete circuit diagram of the buffer amplifier. The comparator Cmp1 consists of an NMOS-input differential amplifier (M1–M6) and an inverter INV1 (M9 and M10). To eliminate quiescent current when is equal to , the outputs of the comparators should be , so that both output transistors and are completely turned off. To make when
—where and are the noninverting and inverting inputs of the comparator, respectively—the common-mode output voltage of the differential amplifier must be smaller than the logic threshold voltage of the inverter. With NMOS-input transistors, the input common-mode range of the differential pair is from 1 to 5 V. The output voltage varies from 3.71 to 3.65 V when the input common-mode voltage is varied from 1 to 5 V. The logic threshold of INV1 is designed to be 4.06 V. Thus, the common-mode output of the differential pair is 0.35–0.41 V lower than the logic threshold of the inverter INV1, which ensures that both output transistors are off when
.
The voltage gain of the differential pair is 34. Thus, when mV, the voltage on node P (Fig. 1) will be a logical low voltage, i.e., the output PMOS will be turned on.
Similarly, when mV, the output NMOS
will be turned on. Thus, when has been charged or discharged to within 10 mV of , i.e.,
mV, both output transistors are off and the maximum tacking error is 10 mV. In this way, when input voltage changes, only one of the two output transistors will be turned on to make the output follow the input. Once the output voltage is within the maximum tacking error, both output transistors are off. Thus, the dynamic power can approach the theoretical lower limit of 0.5 . Since the threshold mismatch in a CMOS process could be as large as 10 mV, the influence of the comparator’s offset voltage must be considered. With the sign of the offset voltages defined in Fig. 1, the operation of the output buffer becomes:
1) when mV, the output PMOS
will be turned on;
2) when mV, the output NMOS
will be turned on;
3) when mV mV ,
both output transistors are off.
Thus, if mV and mV, then both
output transistors are off when mV
mV. If mV and mV, then both output
transistors are off when mV mV.
It can be seen that a positive comparator offset increases the safety margin for short-circuit current but also increases volt-age error. A negative offset reduces the margin for short-circuit current, but voltage error is also reduced. In this design, when negative offset is more than 10 mV, the margin is reduced to zero, i.e., short-circuit current occurs when . Note that a class-B amplifier has crossover distortion. In this design, the crossover distortion is the tracking error. When the tracking error is reduced to zero, the circuit becomes a class-A amplifier. The designed nominal tracking error is a tradeoff between output accuracy and immunity to comparator offset.
Since the thin-film-transistor LCD can display up to 256 gray levels in each color, each gray level is 16 mV at 4.096 V full scale. Thus, the output buffer must have a voltage error less than 8 mV. Without comparator offset, the designed input resolution of the output buffer is 10 mV, i.e., about 0.6 least significant bit (LSB). When process varies, the output common-mode voltage of the differential pair and the inverter’s logic threshold voltage both vary in the same direction so that the difference between these two voltages remains at about 35 mV. The voltage gain of the differential pair varies between 32 and 36 over process variations and 0–100 C temperature range. Thus, the input resolution of the output buffer remains at about 10 mV.
The ac analysis of this output buffer was done with V and the negative input node, V, so that Cmp1 and Mp are operating in linear region. The output loading is 600 pF. The dc gain is 88 dB at room temperature and with typical process. There are three poles: the dominant pole, which occurs at 90 Hz, is caused by the output node; the second pole, at 2 MHz, is caused by the differential pair’s output node; and the third pole, at 100 MHz, is caused by the INV1 inverter’s output node. The unity-gain bandwidth is 1.3 MHz; the phase margin is 50 . Since the output node is the dominant pole, reducing output load capacitance increases the bandwidth but reduces phase margin. Increasing the bias current of the differential stage or reducing the input capacitance of the INV1 inverter can move the second pole outward, which increases the phase margin.
III. EXPERIMENTAL RESULTS
The proposed output buffer amplifier was fabricated using a 0.8- m CMOS technology and a 5- m CMOS 24-V tech-nology. The latter is for field emission devices applications, which require a higher voltage rating. Both chips functioned. Since the design principles are the same, only the results from the 0.8- m CMOS chip are reported. The die photograph of the output buffer is shown in Fig. 3. The active area of an output buffer is 230 140 m excluding input and output pads. Fig. 4 shows the measured result of the output buffer with 10 KHz triangular input and 600 pF load capacitance; the input voltage range is 1–5 V. The lower trace is the input and the upper trace is the output. The output basically
118 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999
Fig. 2. Circuit diagram of class-B output buffer.
Fig. 3. The microphotograph of the die.
follows the input. The step response with 50 KHz square wave input and 600 pF load capacitance (not including parasitic capacitance of the test circuit) is shown in Fig. 5. The lower trace is the input whose voltage changes between 1 and 5 V. The upper trace is the output, and the time for the output to settle within 0.2% (0.5 LSB) of the final voltage is 8 and 3 s for the rising and falling edges, respectively. The supply current for the output stage is 131 A, and the supply current for the rest of the circuit (static bias current) is 24 A. When input frequency is varied from 1 to 50 KHz, the static bias current remained unchanged and the output-stage current varied linearly with the frequency. The theoretical output-stage current at 50 KHz is 120 A, i.e., the measured current corresponds to a 650 pF loading.
An example of the steady-state error of the output buffer is shown in Fig. 6. To show the small error voltage, the signals are ac coupled. The input is a 100 mV swing square wave. The output swing is 108 mV. Thus, the average tracking error is 4 mV. The tracking errors of the output buffer for input voltages ranging from 1 to 5 V are shown in Fig. 7. The input voltage is changed in 0.1 V steps quasi-statically. The errors are all within 7 mV. For inputs between 1.2 and 5 V, the errors are
Fig. 4. The output voltage of the output buffer with 10 KHz triangle wave input. The lower trace is input.
Fig. 5. The step response of class-B output buffer for 600 pF load capac-itance.
smaller (within 4 mV). The steady-state output-stage current is always zero, and the static bias current increases from 21 to 30 A when input increases from 1 to 5 V. Note that the tracking error depends on the input’s slope and step size. Thus, the results shown in Fig. 7 do not cover all possible cases.
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Fig. 6. Step response for small input signal.
Fig. 7. Tracking error versus input voltage for output buffer.
IV. CONCLUSION
A compact, low static power class-B output buffer amplifier for driving a large capacitance load in flat-panel display is
presented. The minimum voltage resolution of this buffer is decided by the comparator. Namely, it is the difference between the common-mode output voltage of the differential pair and the logic threshold voltage of the inverter INV1 divided by the voltage gain of the differential stage. The slew rate of the output buffer is decided by the transistor sizes of the output stage, supply voltage, and load capacitance. Because when the output transistor is turned on, it is fully turned on, the output transistor sizes are much smaller than those of class A and AB buffers. With these two parameters fixed, the bandwidth and bias current of the differential pair can be decided accordingly to obtain stable operation. An experimental prototype output buffer was implemented in a 0.8 m CMOS technology. With 5 V supply voltage and 600 pF load capacitance, the measured static current is 24 A; the maximum tracking error voltage is 7 mV; the output voltage swing is from 1 to 5 V. The settling time for 4 V swing to 0.2% is 8 s, which is more than adequate for driving a 1280 1024 pixels LCD panel with an 86 Hz frame rate, which requires a settling time of less than 10 s.
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[4] B. W. Lee and B. J. Sheu, “A high-speed CMOS amplifier with dynamic frequency compensation,” in Proc. IEEE CICC 1990, New York, May 1990, pp. 8.4.1–8.4.4.
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