Abstract—In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18- m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermod-ulation intercept point of the entire circuit are 16 dB, 17.4 dB, and 1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only 9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.
Index Terms—Balun, low-noise amplifier (LNA), low power, low voltage, mixer, resonator coupling network (RCN), transformers.
I. INTRODUCTION
U
LTRA-LOW power consumption is essential to numerous emerging applications in wireless communications with portable devices. It is especially critical to wireless sensor networks to allow long lasting use of sensor nodes, fixed or portable, without battery replacement after installation. This helps ubiquity in data collection, such as personal healthcare inspection in wireless body-area networks (WBANs) or alarm sensing in intelligent buildings. As pointed out in [1], average power consumption shall be limited to be in the order of 10 W to ensure appropriate battery lifetime extension. This calls for maximum power consumption less than few milliwatts in low duty-cycle wireless data transmissions [2]. Published literature shows that the measured baseband power consumption canManuscript received September 24, 2010; revised February 20, 2011; ac-cepted February 25, 2011. Date of publication April 11, 2011; date of current version June 15, 2011. This work was jointly supported by the National Sci-ence Council, Taiwan, under Grant NSC 98-2220-E-009-064 and the Ministry of Economic Affairs (MOEA) under Project 98-EC-17-A-03-S1-005.
C.-H. Li and C.-N. Kuo are with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: chli.ee99g@nctu.edu.tw; cnkuo@mail.nctu.edu.tw).
Y.-L. Liu was with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan. She is now with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan (e-mail: ylliup@tsmc.com).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2011.2130534
be as low as a few tens of microwatts [3]. Since RF front-end circuits typically consume much more than that of the base-band circuitry, it is therefore worthy of great effort on power reduction in the RF circuits.
Low supply voltage is an effective method to reduce power consumption. It also meets the technology trend of scaling down gate length and increases the possibility of using a single solar-cell source of 400 mV. Consequently, the popular cascode topology that utilizes current reuse is inappropriate. The folded topology with two dc current paths also needs careful design to reduce the total current level.
Different techniques have been applied to the ultra-low power receiver design. The receiver front-end operated at 2.4 GHz and adopts a differential passive mixer without any low-noise am-plifier (LNA) [1]. Although a passive topology consumes less power, it does not contribute conversion gain and it may need more power consumption in the latter stage to provide an ade-quate gain to the entire circuit. In [2], a dual-conversion receiver is implemented at 900 MHz using a self-biased CMOS-inverter LNA with a supply voltage of 1.6 V. Yet the circuit calls for a high supply voltage, not suitable for low-voltage application. Common-gate LNA as a transconductance of the mixer is em-ployed in another approach using fully differential design [4]. The front-end circuitry, however, uses a cascode topology, in-appropriate for low supply voltage.
The technique of using a transformer is an alternative in the front-end circuit design [5]. Placed between the LNA and mixer, a transformer not only acts as a balun, but also provides a voltage gain or a current gain. An ideal lossless transformer calls for a coupling coefficient of unity and an inductance value of in-finity. The theoretical current gain relies on the coil turn ratio , a frequency-independent quantity to achieve the maximal power transfer condition. Hence, a high turn ratio is desired to supply a high gain. For instance, of 4 is used in [6]. In practice, how-ever, of an on-chip transformer cannot easily achieve unity [7]. A high turn ratio also usually causes a low self-resonance frequency because of large parasitic capacitance. Moreover, a transformer with a high turn ratio usually occupies a large area, which increases the cost dramatically. Consequently the current gain is very limited.
In this work, the resonator coupling technique is applied to overcome the aforementioned disadvantage of using a trans-former alone. The resonator coupling network (RCN) can pro-vide a high current gain at resonance, in addition to the single-to-differential conversion. The RCN has been applied to implement a wideband LNA [8], a wideband multimode voltage-control-loed oscillator (VCO) [9], [10], and a low-power downconver-sion mixer [11]. Nevertheless, the physics behind it is not well
Fig. 1. Direct downconversion receiver front-circuit under consideration, in-cluding the LNA, balun, and mixer. The balun is implemented by an RCN.
explained. It will be shown soon that the RCN gives the same maximal current gain (MCG) as an ideal transformer in the crit-ical coupling condition.
A low-power receiver front-end is designed in 0.18- m RF CMOS technology. The circuit is for the application of wireless sensor nodes operated at the 5-GHz industrial–scientific–med-ical (ISM) unlicensed frequency band. Several techniques are combined to achieve sub-milliwatt power consumption, including the folded topology with 0.6-V low supply voltage and the RCN for signal current gain. The device biasing con-dition is optimized by inspecting a composite figure of merit (FOM). A guideline is introduced for design optimization. All the design efforts successfully ensure low power consumption. In Section II, design consideration of each sub-circuit is dis-cussed. The measurement data are presented and summarized in Section III. Finally, Section IV concludes this paper.
II. DESIGNCONSIDERATION
The receiver front-end architecture under consideration is shown in Fig. 1. The direct conversion architecture is adopted for the concern of the minimal number of components. This architecture eliminates the need of an image filter. Circuit blocks inside the dashed box are designed, including an LNA, a balun, and a double-balanced mixer. Applied to the sensor node of short-distance body-area networks, the receiver does not require a high sensitivity level. On the other hand, power constraint is the major concern in order to prolong the battery life. From the viewpoint of system design, most of the gain budget shall be assigned to the LNA, and therefore it contributes the most to power consumption.
Fig. 2 shows the proposed front-end circuit, which makes use of the resonator coupling technique. For the supply voltage as low as 0.6 V, it calls for a single-transistor microwave ampli-fier for the LNA [12] to avoid transistor stacking. However, the low supply voltage may limit the linearity due to small voltage headroom. Therefore, LNA signaling is preferred to be in the current domain. The LNA is single-ended to account for the typical antenna configuration. It takes a balun to convert sig-nals into the differential form for better noise immunity in the receiver path. The differential currents at the balun output are commuting by the switching stages of the mixer for the purpose of frequency conversion. The self-mixing issue related to local oscillator (LO)-to-RF isolation in the mixer design is critical to receivers adopting the direction conversion architecture. Since LO leakages appear out of phase in the double-balanced mixer input, LO-to-RF isolation is high and the self-mixing issue is minimized.
Fig. 2. Circuit schematic of the receiver front-end, including a single transistor LNA, a double-balanced mixer, and an RCN functioned as a balun and provides current gain.
Fig. 3. (a) Cascode LAN circuit. (b) Single-transistor LNA for low supply voltage.
Although active implementation of a balun [13], [14] con-tributes signal gain, they consume dc power while contributing additional noise to the receiver front-end. On the other hand, passive transformers, causing no dc voltage drop, are attractive in this power-constraint project. The proposed RCN not only functions as a balun, but also provides current amplification by impedance transformation without power consumption. More-over, the dc block characteristic allows the LNA and the mixer connected in a folded topology. Low supply voltage is therefore feasible.
In this design, only the mixer in the in-phase (I) channel is designed. Another mixer for the quadrature (Q) channel can be implemented similarly. Offering I and Q signal channels might be viable to realize modern modulation schemes in some relia-bility-critical applications such as healthcare monitoring.
A. LNA Circuit Design
As shown in Fig. 3(a), the conventional cascode configuration has good stability and high reverse isolation [15]. The minimum dc biasing at the output node, however, is limited to keep both transistors at saturation [16]. The low supply voltage of 0.6 V yields to insufficient headroom to sustain good linearity perfor-mance. As mentioned in [17], a larger effective voltage results in higher linearity of a transistor. This leads to the design using a single transistor, as shown in Fig. 3(b). The external compo-nents, and , allow the LNA to simultaneously achieve power matching and noise matching [18].
find the optimal biasing condition.
Several FOM definitions are first reviewed to determine the bias condition. The FOM of evaluates the conversion efficiency of dc power to transconductance, or gain, and usu-ally leads to the biasing condition in the weak inversion region [20]. For RF design, the FOM of was proposed to include , taking the device frequency response into consider-ation [21]. This FOM represents the gain-bandwidth product to evaluate the performance of the high-frequency circuit. Further-more, it is also critical to include the linearity and noise perfor-mance as far as an LNA circuit is concerned. Since the FOM of a tuned LNA is usually defined as [22]
(1) it is then meaningful to define a FOM for transistor biasing as
(2) where represents the device third-order linearity under a given bias condition without any impedance matching network.
Fig. 4(a) and (b) plots each device parameter and FOM of an nMOS transistor, respectively, with respect to the current den-sity under the supply voltage of 0.6 V. The optimal FOM posi-tion is dependent on , the LNA load resistance, since it affects the linearity performance due to the nonlinearity of the output conductance . As is small, is dominated by the non-linearity of . When becomes large, the nonlinearity of becomes remarkable, and tends to cancel the nonlinearity at smaller . Larger could give higher , but the re-sult is more sensitive to bias current. Therefore, given the effec-tive loading resistance from the RCN, current density is chosen as 8.8 A m in the final design, somewhat adjusted to opti-mize the overall performance.
One major concern of the single-transistor LNA is the sta-bility issue. The electrical feedback due to the gate–drain ca-pacitance is significant such that bilateral amplifier design is necessary. This undesired feedback causes the amplifier to ap-pear as conditionally stable at 5.5 GHz. The load stability circle typically cuts into the upper region of the Smith chart, as shown in Fig. 5, which means a capacitive load is preferred to avoid in-stability. An inductive load, however, is necessary to tune out the capacitive output impedance at the drain port to enlarge the gain level. To the cascode LNA circuit in Fig. 3(a), this is not an issue at all since the load impedance presented by the common-gate transistor is low and capacitive. Not only the Miller feed-back of is decreased, but also the load impedance sits in the stable region.
To alleviate the stability issue, the transistor shall be stabi-lized by adding external components without much degradation
Fig. 4. (a) Variation of each device parameter versus the drain current density. (b) Calculated FOMs to determine the biasing condition. Each FOM has been normalized to the highest value within the supply current range.
Fig. 5. (a) Load stability circles of the single-transistor LNA at 5.5 GHz with and without reactive stabilization. (b) Smith chart showing the noise and power matching whenC and L are included. S means the complex conjugate ofS .
to the noise performance. It turns out that the two reactive com-ponents, the gate–source capacitor and the source inductor , also benefit stabilization. Fig. 5(a) shows that the load sta-bility circles move out of the Smith chart after adding of 0.91 nH and of 0.1 pF. This gives room for impedance matching without the stability concern. In addition to the oper-ating frequency, the stability condition is inspected over a large frequency range from 100 MHz to 10 GHz to ensure that the LNA is stable. and also help the LNA to achieve noise
Fig. 6. Conversion trans-impedance gain versus LO power for different load resistances.A is the current conversion gain from the mixer input to IF output. LO power is referred to 50.
and power matching at the frequency of interest, as illustrated in Fig. 5(b).
The output resistance of the LNA should be as high as pos-sible to possess a high MCG while the transistor still stays in the best FOM. Consequently the LNA size is chosen as 25 m to present the output resistance and capacitance of 7.68 k , and 30 fF, respectively.
B. Mixer Circuit Design
A double-balanced mixer is preferred for better port-to-port isolation and less even-order distortion. The latter is especially critical in the direct downconversion receiver.
The mixer circuit typically consists of a transconductor stage and a current-switching stage, such as the Gilbert cell. The transconductor transfers the RF input voltage into current. In this design, the LNA is directly utilized as the transconductor. The scheme can reduce the required power consumption. The switching stage - performs current switching for frequency conversion. pMOS transistors are chosen in the switching pair due to their lower flicker noise as compared to nMOS transistors. Ideally only one switching path of the switching stage is on at a time. Nonideal switching, however, degrades circuit performance, such as gain and noise contri-bution. To make the switching more ideal, a large transistor is chosen and the biasing point is set near threshold voltage. Such biasing reduces power consumption. Although it may degrade the noise performance, a high NF is tolerable for the application to wireless sensor networks.
Consideration of mixer optimization is twofold. One is to maximize the trans-impedance conversion gain, and the other is to lower the required LO level. The former typically calls for a large LO level. The latter is important to decrease the power consumption in the LO generation circuit. The optimization re-lies on careful choice of the load resistance .
Fig. 6 shows the conversion gain of the mixer under different values versus LO power for the given bias of 0.44 V. The LO power is referred to 50- impedance. The maximum conversion gain tends to be larger for larger , and the LO power for the maximum gain moves toward a smaller value. If the bias of pMOS becomes larger, the LO power for the maximum gain can be even smaller. The largest is actually
Fig. 7. (a) Proposed RCN and (b) equivalent circuit of the RCN consisting of the equivalent models of the LNA, mixer, and transformer.
limited by linearity performance. is selected as 1.6 k in this design. The required LO power is 6.5 dBm for the max-imum gain, but it is determined as 9 dBm for the sake of better tradeoff between gain and linearity, with a decrease of 1.4 dB in the gain level.
The input resistance of the mixer is required to be small for a high current gain, which, in turn, calls for high in - . The value of is chosen as 3.62 mA/V to make a tradeoff between the LO power and RCN gain. Hence, the transistor size is chosen as 137.5 m, resulting in the resistance of 276 and the capacitance of 100 fF at the mixer input.
C. RCN Formulation
Between the LNA and mixer, an RCN needs to be designed carefully to convert the single-ended RF signal into the dif-ferential form, while it also provides a high current gain by impedance transformation.
In the proposed front-end, the RCN can be modeled as illus-trated in Fig. 7(a). One resonator ( and ) is connected to the output of the LNA, and two resonators ( , , , and ) are connected to the mixer input using a center-tapped coil. The magnetic coupling in the transformer transfers the current signal from one resonator to the others. The mutual inductance between the primary and secondary coils is designated as . The coupling coefficient is defined as
(3) , , , , , and represent the parasitics of the transformer. The LNA output impedance and the mixer input
impedance are modeled by , , , and ,
respectively. Since the transformer is symmetric to the virtual ground of the secondary coil, the RCN can be analyzed by a two-port network, as shown in Fig. 7(b), without loss of gener-ality. The coupled coils are replaced with an equivalent T-cir-cuit. The ohmic resistors and are neglected to simplify the analysis. Therefore, the RCN includes the parasitics of the LNA, mixer, and transformer.
The current gain , of the RCN can be derived by current division formulation at each node using the imped-ances , , and . In [11], the design parameters of an RCN are obtained by numerical simulations. The current gain formula appears too complicated to give much insight. Actually it will be shown soon that the MCG condition only depends on the ratio of the LNA output resistance to the mixer input resistance. For convenience, and are defined as the resonant frequencies of those two uncoupled resonators with the frequency ratio of ,
and (4)
In the coupled network, the natural resonance frequencies can be expressed in term of , , and as
(5)
(6)
At these two natural resonance frequencies, signal can be cou-pled from the LNA into the RCN, and transferred to the mixer in the most efficient manner. Either one can be chosen as the circuit operating frequency, designated as hereafter. In the following analysis, it is assumed that the quality factors of ,
, and are large enough, higher than 3.
The current division ratio of at resonance is determined by , and can be derived as
(7)
where is the frequency ratio of normalized to and is the transformer turn ratio defined as
(8) at resonance increases rapidly when is small and is high. Thus, high magnetic coupling and a low turn ratio are de-sired to make close to the maximal value of 1.
The current gain is derived using the resonator quality factor. As illustrated in Fig. 8, can be modeled as an
in-Note that depends linearly on and increases as decreases, in agreement with the trends to improve . That is, it is preferred to make weak magnetic coupling to enlarge the current gain . The opposite requirements on to optimize and result in an optimal value to achieve the maximal total gain.
can be obtained by current division of and . Ac-tually, the maximum gain of occurs at the resonance fre-quency of the resonator comprised by and and equals to the tank quality factor at . Since the circuit operating frequency deviates from , becomes somewhat less. It can be derived as
(10)
The approximation is valid since in
the frequency band of interest. Finally, is given by (11)
It can be observed from (10) and (11) that the effects of on the total gain cancel with each other, indicating that the maximum current gain level is independent of .
The total current gain can be obtained simply by multiplying (7) and (9)–(11) together
(12) It is more convenient for design to replace with other quanti-ties by using (5) and (6). The total gain can be rewritten as
TABLE I
COMPARISON BETWEEN THEREQUIREMENT OF THE
TRANSFORMER AND THERCNFORMCG
The parasitic capacitance of the transformer can be absorbed into the design.
Consider the case if an ideal transformer with the turn ratio is applied as the balun. The current gain follows the impedance transformation as
(14)
The maximum value is when or in the
impedance match condition. The value can hold up over a wide frequency range.
In the RCN case, the on-chip coupling coefficient hardly achieves unity as an ideal transformer. To explore the MCG con-dition, (13) is differentiated with respect to and . It leads to the result
(15) Essentially it represents impedance matching at the LNA output. It also meets the critical coupling condition that energy is cou-pled from the LNA to the RCN with the highest efficiency. The impedance match condition also holds at the mixer input. This can explain why the RCN presents the MCG at resonance fre-quencies. Given the critical coupling condition, the MCG is
(16) The results of those two cases are very interesting. The MCG is determined only by the ratio of and . Although , the maximum gain of the RCN gets to the same result as an ideal transformer if and are chosen properly by (15) without the condition of and infinite inductance. This greatly eases the design of an on-chip transformer where unity is very unlikely to be realized. Furthermore, it is also possible that the turn ratio of the RCN is smaller than , which is con-strained by . The advantage simply comes from the tradeoff of bandwidth. The comparison between the requirement of the transformer and the RCN designed for MCG is summarized in Table I to emphasize the benefits of using the RCN.
D. RCN Design
By designing the LNA and mixer to have a high resistance ratio of , the RCN can give a high current gain without any power consumption. As aforementioned, is 7.68 k and is 276 . The design goal is an MCG at
Fig. 9. Contour plots of the current gain with respect to the coupling coefficient k and r. (a) n = 1, (b) n = 2, (c) n = 3, and (d) n = 4.
the center frequency of 5.5 GHz. If designed by an ideal transformer, the required turn ratio is larger than 5.
RCN design is governed by (13) and (15). Current gain is generally determined by (13). If the combination of , , and deviates from the condition of (15), the critical coupling fails. Indeed there are infinite solutions of the combination. A contour plot of the current gain can be exploited to optimize the RCN design. Fig. 9 illustrates the contour plots in various values from 1 to 4 over the range of from 0 to 3. Note that the regions
of and correspond to the cases of and
, respectively. It can be observed that the MCG reaches the ideal value of 2.64 calculated by (16), no matter what the value is. It can be also found that the MCG occurs in both
and , different from that in [11], where only is chosen to obtain a higher gain. When , however, the bandwidth appears to be narrow, and it is not easy to implement the element values on chip. Moreover, the contour lines change more slowly when , indicating that the current gain is less sensitive to variation. It is, therefore, preferred to choose , i.e., is designed at . More specifically, is chosen around 0.5 in this work.
The RCN input impedance over the frequency of interest af-fects LNA linearity, as demonstrated in Fig. 4. In order to in-vestigate the influence of the RCN parameters on the LNA lin-earity, the contour plot of the RCN input impedance is plotted in Fig. 10. The RCN input impedance shows a similar trend as that of the current gain. When is larger and is smaller, the impedance is less susceptible to variation, and so does the LNA linearity. Furthermore, Fig. 4 shows that the LNA bias cur-rent remains similarly for the highest third-order intermodula-tion intercept point (IIP3) when is large. If the implemented
Fig. 10. Contour plots of the RCN input impedance with respect to the coupling coefficientk and r. (a) n = 1, (b) n = 2, (c) n = 3, and (d) n = 4. The unit is k.
RCN does not translate exactly optimal load to the LNA, the LNA bias can be finely tuned for higher IIP3.
The design flow of the RCN can be arranged as follows. First, is selected as 3. The optimal coupling coefficient is ob-tained to be 0.46 by (15), but it can range from 0.4 to 0.7 without much degradation of the current gain according to Fig. 9(c). The ratio of 0.52 then can be determined from (5). With and known, and are also decided to be 5.72 and 11 GHz, re-spectively. and are related by the turn ratio . With the consideration of on-chip transformer feasibility, and are designed as 4.5 and 0.5 nH, respectively. Finally, and are determined as 172 and 418 fF, respectively. Since the values of and are close to the total parasitic capacitances from the resonators, LNA, and mixer, no additional capacitor is required. The design flow is summarized in Fig. 11.
The designed transformer is shown in Fig. 12, where the port of the primary coil is connected to the LNA, and and of the secondary are linked to the double-balanced mixer. The design needs to meet the high difference ratio of and . The width of the secondary coil is set as 10 m, and of the pri-mary is 8 m. The outside dimension (OD) is designed as 260 m such that the line length reaches the self-inductance require-ments of and . The square root of the physical turn ratio is only 2. When the mutual inductance is taken into consideration, the effective turn ratio is expected to be close to the required value of 3. Since the transformer allows significant variation, the spacing of 2 m is chosen to make the occupied area as small as possible. It takes the electromagnetic (EM) simulator of
Fig. 11. Design flow for RCN design.
Fig. 12. Proposed transformer in the RNC.w and w are the width of primary and secondary inductors, respectively.OD is the outside dimension.
Ansoft Designer only a few moments of iteration to determine the final physical dimension.
The extracted parameters from the EM simulation yield to of 0.64, of 2.76, of 4.41 nH, and of 0.58 nH. The difference between the desired and implemented values of and is quite tolerable for the current gain design. Nevertheless, the parasitic ohmic resistance, of 8.04 and of 2.41 , causes the MCG to further drop down to 2.1. Thus, the RCN differentially provides a current gain of 4.2 ( 12 dB).
Although of 3 is demonstrated in this design, small as 1 as one and small of 0.14 are sufficient to achieve the MCG. Consequently, the chip area can be smaller than that by using an ideal transformer. The tradeoff is an accurate design of the coupling coefficient .
III. EXPERIMENTALRESULTS
The front-end circuit is fabricated in Tiawan Semicon-ductor Manufacturing Company (TSMC) 0.18- m RF CMOS technology. The micrograph is shown in Fig. 13. The die size is 1.16 0.75 mm , including bonding pads. Measure-ments were conducted by chip-on-board setup. DC pads are wire-bonded on a printed circuit board (PCB) board. High-frequency signals are through on-wafer probing with a ground–signal–ground (GSG) probe for the RF input and a ground–signal–ground–signal–ground (GSGSG) probe for the LO signal. The differential IF output signal is converted to a single-ended form by an on-board OP amplifier with
Fig. 13. Micrograph of the fabricated low-power receiver front-end circuit in 0.18-m RF CMOS technology.
Fig. 14. Measured input return loss.
model of AD8011 from Analog Devices connected in unit gain. The differential input impedance of the OP amplifier is chosen as 16 k to emulate a high IF loading impedance. A 50- resistor is added in series at the OP amplifier output for impedance matching to 50- measurement systems such that a 6-dB voltage gain shall be compensated in all the gain measurements.
The supply voltage is set as 0.6 V in the measurements. The total quiescent dc power consumption is 0.33 mW. The power becomes 0.53 mW as the LO signal of 9.5 dBm is injected under operation. Even if an additional mixer is taken into account for both I/Q channels, the total front-end power consumption is still around 1 mW. Fig. 14 plots the measured input return loss with a small frequency shift to 5.25 GHz. How-ever, at 5.5 GHz is still better than 16 dB. The bandwidth is around 1 GHz, of which the input return loss is better than 10 dB.
Fig. 15 illustrates the conversion gain versus LO power. The trend is similar to Fig. 6. The LO power is chosen as 9.5 dBm to obtain the highest gain of 17.4 dB, and this LO power is used in the measurements of IF bandwidth and linearity. Fig. 16 shows the measured IF bandwidth around 7 MHz, different from the simulated one around 300 MHz. This bandwidth
Fig. 15. Measured conversion gain versus LO power. The LO power of09.5 dBm corresponds to the highest voltage conversion gain.
Fig. 16. Measured voltage conversion gain is about 17.4 dB with the IF band-width of 7 MHz, limited by the OP amplifier output buffer.
Fig. 17. MeasuredIIP is around 01.5 dBm.
discrepancy arrives from the frequency response of the OP amplifier output buffer. It can be improved by using a wideband OP amplifier.
The measurement is conducted by a two-tone test. The measured is 1.5 dBm, as indicated in Fig. 17. The 1-dB compression point is also measured as 14 dBm. The measured NF is 7.8 dB at the IF frequency of 1 MHz. Table II summarizes the circuit performance and makes a comparison with previous works. The receiver front-end using the RCN shows excellent performance of the best FOM.
(1) Using single balanced mixer. (2) Power consumption contains I and Q mixers. (3) Including electrostatic discharge (ESD) protection in the input. (4) IIP3 of021 dBm estimated from P . (5) Half total power consumption of 9.7 mW is used for fair comparison. (6) Since it contains I and Q mixers using single-balanced topology, power consumption of 6.5 mW is still used in the FOM calculation.
(7) FOM is defined as follows:FOM = 10 log[(Gain 2 IIP3 2 f)=(P 2 (NF 0 1))], where f; P are calculated in Hz and mW, respectively.
IV. CONCLUSION
The resonator coupling technique for the MCG has been successfully employed to design a low-power and low-voltage 5.5-GHz receiver front-end fabricated in 0.18- m CMOS technology. The RCN achieves the MCG condition when the resonators are critically coupled to the LNA. The most important one is that the RCN can achieve the same MCG level as an ideal transformer does, but without the constraint of unity coupling coefficient and infinite inductance. This MCG in the RCN is only related to the ratio of the output resistance of the LNA and the input resistance of the mixer. Therefore, the RCN can utilize small and small to achieve the MCG so the chip area can be small to lower the cost. By using this resonator coupling technique, the receiver front-end only consumes 0.33 mW from a supply voltage of 0.6 V. The conversion gain, IIP3, and NF at IF frequency of 1 MHz are 17.4 dB, 1.5 dBm, and 7.8 dB, respectively. The proposed ultra-low power receiver front-end is very suitable for the applications of a wireless sensor network.
ACKNOWLEDGMENT
The authors would like to acknowledge the Chip Implementa-tion Center (CIC), Hsinchu, Taiwan, for circuit fabricaImplementa-tion sup-port, the ANSYS, Taipei, Taiwan, for design supsup-port, and T.-N. Yu, Sunplus Technology Corporation, Hsinchu, Taiwan, for chip measurement.
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Chun-Hsing Li (S’10) received the B.S. degree in electrophysics and M.S. degree in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2005 and 2007, respectively, and is currently working toward the Ph.D. degree at NCTU.
After one year of military service as a Second Lieu-tenant with the Marine Corps, he was a Research As-sistant with the RF System Integration Laboratory, NCTU, until June 2009. In Fall 2009, he joined the Department of Electrical Engineering, University of California at Los Angeles (UCLA). In Winter 2010, he was with the Department of Electrical and Computer Engineering, University of California at Santa Bar-bara. Since April 2010, he has been with NCTU. His current research is focused on the RF and terahertz circuit design.
Mr. Li was a corecipient of the Best Paper Award of the 13th IEEE Interna-tional Conference on Electronics, Circuits, and Systems, Nice, France, 2006.
Yen-Lin Liu received the B.S. degree (with honors) in electrophysics and M.S. degree in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2005 and 2007, respectively.
She is currently with the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan.
Chien-Nan Kuo (S’93–M’97) received the B.S. de-gree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1988, the M.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, and the Ph.D. degree in electrical engineering from the University of California at Los Angeles (UCLA), in 1997.
In 1997, he joined ADC Telecommunications, San Diego, CA, as a Member of Technical Staff with the Mobile System Division, where he was involved in wireless base-station design. In 1999, he joined Broadband Innovations Inc. In 2001, he joined the Microelectronics Division, IBM. He is currently an As-sociated Professor with the Department of Electronics Engineering, National Chiao Tung University. His research interests include reconfigurable RF cir-cuit and system integration design, low-power design for the application of wireless sensor networks, and development of circuit-package co-design in the system-in-package (SiP) technique.
Dr. Kuo has served as a Program Committee member of the IEEE Asian Solid-State Circuits Conference since 2005 and IEEE Silicon Monolithic Inte-grated Circuits in RF Systems since 2007. He was a recipient of the IEEE Grad-uate Fellowship Award in 1996. He was a corecipient of the 2006 Best Paper Award presented at the 13th IEEE International Conference on Electronics, Cir-cuits, and Systems.
