Introductory invited paper
Reliability of ultrathin gate oxides for ULSI devices
Chun-Yen Chang
a,*, Chi-Chun Chen
a, Horng-Chih Lin
b, Mong-Song Liang
c,
Chao-Hsin Chien
a, Tiao-Yuan Huang
a,baInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan bNational Nano Device Laboratories, Hsinchu, Taiwan
cTaiwan Semiconductor Manufacturing Co. Ltd., Hsinchu, Taiwan
Received 5 April 1999
Abstract
Ultrathin gate oxide, which is essential for low supply voltage and high driving capability, is indispensable for the continued scaling of ULSI technologies towards smaller and faster devices. Needless to say, the reliability of ultrathin oxide is of major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. This paper reviews the reliability issues regarding ultrathin gate oxide for present and future ULSI technologies. Issues including gate leakage current, time-dependent dielectric breakdown, poly-gate depletion, boron penetration, and plasma process-induced damage will be addressed. Several techniques such as nitrided oxide and alternative processes, which are proposed to improve gate oxide reliabilities, are also discussed. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction
To ensure the continued shrinkage of CMOS tech-nologies down to sub-quarter micron regime and beyond, ultrathin gate dielectric with low defect density and high reliability is indispensable. In general, high driving capability and well-controlled short channel characteristics require the use of ultrathin gate oxides. Since Momose et al. ®rst proposed the use of 1.5 nm direct-tunneling (DT) gate oxide for n-MOSFET with extremely high device performance in 1994 [1], many aggressive studies regarding direct tunneling gate oxide for sub-quarter micron devices have been carried out [2±10]. The application of DT gate oxide not only achieves high speed for logic circuits, but also essential for high-performance RF applications [8,9]. In
ad-dition, the use of thinner oxides is also critical to meet the demands of lower programming voltage for future nonvolatile memories [10,11].
However, the application of DT gate oxide to ULSI devices faces many challenges. Firstly, the presence of large quantum mechanical (QM) tunneling current is a serious scaling limitation in terms of standby power consumption [12]. Secondly, breakdown characteristics for ultrathin oxides become even more critical due to the dramatic increase in electric ®eld across the oxide during normal device operation. Whether oxide becomes inherently more robust or more vulnerable to electric stress as it thins down, therefore, plays a very crucial role for its applications to ULSI devices. Thirdly, poly-gate depletion eects (PDE) are known to get worse with oxide scaling. This is because the operating gate voltage normally does not scale propor-tionally to the oxide thickness, and therefore, the aver-age surface ®eld increases. The additional voltaver-age drop at the poly depletion layer results in undesirable drive
0026-2714/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(99)00037-2
* Corresponding author.
current degradation [13]. Since these eects worsen for thinner oxides, it could become a limiting factor for future device scaling.
Furthermore, as gate oxide thickness decreases, sev-eral process integration issues emerge as new chal-lenges. Boron penetration from the p+-poly-Si gate
into the thin gate oxide and the channel region in p-MOSFETs is one of the major concerns for dual-gate CMOS technologies. The penetration of boron into and through gate oxides results in threshold voltage instability, low-®eld mobility reduction, and gate oxide degradation [14±18]. The undesirable boron pen-etration eects are aggravated as gate oxide is scaled down. Finally, plasma-process-induced charging damage can result in severe degradation in oxide integ-rity as gate oxide thickness is scaled down [19±27]. The frequent use of plasma steps with high-density plasma reactor in advanced circuit manufacturing, coupled with the restriction that no high temperature anneal is allowed in back-end processing, aggravates the situ-ation. It is, therefore, very important to characterize the performance of plasma processes in production with scaled oxides.
In this work, we will review recent studies on issues relating to the reliabilities of ultrathin gate dielectrics for present and future ULSI technologies.
2. Gate leakage current
2.1. Quantum mechanical tunneling
Signi®cant leakage current that ¯ows through gate oxide due to QM tunneling may cause reliability pro-blems and limits device application. It is well known that as the gate oxide thickness is scaled down to 3 nm and below, the gate leakage current increases dramati-cally due to the occurrence of DT. This happens when oxide voltage is reduced to lower than 3.2 V, the tun-neling barrier for electron changes from triangular to trapezoidal. The current conduction mechanism is the so-called DT current [28]. Typical gate current charac-teristics of ultrathin oxides (2.5±4.2 nm) and the simu-lated Fowler±Nordheim (F±N) current ®tting curves are as shown in Fig. 1, while the simulated DT current for thinner oxides down to 1.5 nm are shown in Fig. 2. The F±N I±V ®tting method for extracting ultrathin oxide thickness has been widely adopted because of its accuracy and convenience as an on-wafer measurement method [29,30]. By taking PDE into account, the method is well suited for ultrathin oxide measure-ments. This is especially so, considering the fact that PDE has made the extraction of oxide thickness from the traditional C±V measurements dicult. However, this method is not suitable for measuring oxide thick-ness thinner than 2 nm because not enough F±N
cur-rent is available for extraction before oxide breakdown. Therefore, to ®nd an accurate and con-venient method to determine the exact oxide thickness in DT conduction region is important and urgent.
Fig. 2. Simulated current±voltage characteristics of direct tun-neling current for ultrathin oxides with thickness ranging from 1.5 to 2.5 nm. The dotted line at J 1 A/cm2 indicates
that the minimum thickness of silicon dioxide as gate dielec-tric will be around 1.85 nm.
Fig. 1. Typical current±voltage characteristics of ultrathin ox-ides and the F±N current ®tting curves. The stress polarity is under substrate injection mode with the poly-depletion eect taken into account.
2.2. Gate leakage current as a limitation of scaling As a general rule, logic circuits can tolerate higher leakage current than memory circuits. It has been shown that the DT current associated with 1.5 nm oxide is comparably small to the large drain current of 0.1 mm MOSFET. However, leakage current of such magnitude could still result in lower data retention time for DRAM, higher chip standby power and accel-erated device degradation. Thus, large DT current pre-sents a scaling limitation for future CMOS technologies. To avoid CMOS operation at high elec-tric ®eld with large standby power, the power supply voltage (Vdd) has to scale more aggressively. This,
however, defeats the purpose of scaling. To maintain device performance, it is projected that the oxide ®eld during normal operation will stay at around 5 MV/cm [11], and that the minimum supply voltage will be around 1 V (0.9 V for worst case). If one assumes that the total active gate area per chip is of the order of 0.1 cm2 for future generation technologies, the maximum
tolerable tunneling current will be about 1±10 A/cm2
[31]. As indicated in Fig. 2, the minimum thickness of silicon dioxide to meet this criterion as the gate dielec-tric will be around 1.85 nm.
2.3. Alternate gate dielectrics
To overcome the gate leakage current limitation for scaling of future CMOS technologies, many alternative materials with high dielectric constant (er eSiO2) to
serve as the gate dielectric were studied [32±44]. These `high-k' materials can provide the same equivalent elec-trical thickness by a physically thicker layer which is, therefore, more controllable and hopefully more manu-facturable. These ®lms prepared with various advanced technologies have been shown to eectively reduce gate leakage current, suppress boron penetration and have higher time-dependent dielectric breakdown (TDDB) lifetime as well. These ®lms fall into three main categories. The ®rst group is nitride-related ma-terials including oxynitride grown on nitrogen-implanted substrates [32], jet vapor deposited (JVD) nitride [33,34], and LPCVD nitride [35]. The second group belongs to metal oxides, such as Ta2O5 [41,43],
TiO2 [37,42,43], BaSrTiO3 (BST) [42], Al2O3 [44] etc.
The third group employs stack gate structures such as nitride/oxide [39,42], metal oxide/oxide [36,40] and metal oxide/nitride [39,42]. All three groups appear to be promising as potential replacement for the thermal-grown SiO2 dielectric. Nevertheless, process
optimiz-ation and detailed reliability data of these novel ma-terials need to be established before they can be con®dently accepted into mass production.
3. Breakdown characteristics
3.1. Occurrence of soft-breakdown
Breakdown characteristics of ultrathin gate oxides are discussed in this section. It was observed that when the oxide is thinner than 6 nm, an anomalous failure mode may be induced during high electric ®eld stres-sing [45,46]. Speci®cally, thin gate oxide sometimes exhibits a signi®cant leakage current increase accompa-nying a characteristic `noisy' or ¯uctuating leakage current [47,48]. In contrast to the conventional `hard breakdown' (HBD), this new breakdown phenomenon is named soft-breakdown (SBD), quasi-breakdown or partial-breakdown. Its occurrence complicates oxide reliability evaluation. Fig. 3 shows typical V±t curves during charge-to-breakdown (Qbd) measurements using
constant current stress, which is a well-known and widely accepted method for evaluating oxide reliability, for various gate oxide thickness. The abrupt drop in applied voltage after a certain period indicates the occurrence of oxide breakdown. It can be seen that the magnitude of post-breakdown voltage for SBD and HBD events is quite dierent. While the post-break-down voltage after HBD is around 1 V or less, the vol-tage after SBD can be more than 1 V of magnitude. Moreover, the SBD events depict the characteristic `noisy' behavior with ¯uctuating voltage, accompany-ing by an increase in non-switchaccompany-ing 1/f noise and ran-dom telegraph noise after soft-breakdown [49]. Such
Fig. 3. Typical voltage±time curves for constant-current stres-sing measurements. The oxide thickness ranges from 8.6 to 2.5 nm. Soft-breakdown occurs when Toxis scaled to 4.2 nm
behaviors could be ascribed to on/o switching events of one or more local conduction spots [48].
3.2. Oxide thickness dependence on Qbdcharacterization
The oxide breakdown characteristics show strong thickness dependence, as is evidenced from Fig. 3. For thicker oxides (e.g., 8.6 nm), only HBD is observed, while both SBD and HBD events are induced in oxide with intermediate thickness (e.g., 4 nm). For ultrathin oxide (e.g., 2.5 nm), SBD is found to dominate exclu-sively the breakdown events [50]. Moreover, for even thinner oxide (<2 nm), due to the extremely large DT current, the voltage drop after SBD is very small, and may not be noticeable. Therefore, it becomes very di-cult to detect oxide breakdown from the V±t curves [4]. Fig. 4 shows the 50% Qbd values, measured at
258C and 1808C, as a function of oxide thickness. At room temperature, it is found that Qbdof 2.6 nm-thick
oxide is about three orders of magnitude higher than that of thicker oxides. Such `turn-around' behavior in-dicates that oxides show higher tolerance to DT cur-rent since negligible energy is deposited inside the oxide layer, comparing to the F±N tunneling [47]. However, when temperature is raised to 1808C, Qbd of
2.6 nm-thick oxide is only about one order of magni-tude higher than that of thicker oxides. This implies a very signi®cant temperature acceleration eect for ultrathin oxide under DT stressing. This suggests that more attention should be paid to burn-in tests as well other wafer processing steps that encounter elevated
temperature in order not to jeopardize the gate oxide integrity (GOI) of ULSI devices employing ultrathin gate oxide [51].
The polarity dependence of Qbd, which is the Qbd
dierence between gate injection (Vg<0) and substrate
injection (Vg> 0) stressing, is shown in Fig. 5. The
stressing current density is ®xed at 1 A/cm2. It has
been well documented in previous reports that the po-larity dependence increases with decreasing oxide thickness (Tox) for oxides thicker than 4 nm. This is
ascribed to the dierent properties between the poly-Si/oxide and oxide/Si interfaces [52,53]. As shown in Fig. 5, as oxide is further scaled down, the polarity dependence becomes even more dramatic. This is mainly due to the rapid rise in Qbd under substrate
injection polarity as oxide is thinned down. Qbd under
gate injection polarity, however, remains relatively unchanged during F±N stressing.
3.3. Evaluation of ultrathin oxide reliability
As described above, the evaluation of ultrathin oxide reliability becomes much more complicated as oxide is scaled down. Recently, several studies have pointed out that oxide breakdown is a strong function of device geometry [54±56]. As such, the conventional use and its interpretation of Qbd for comparing
dier-ent MOS processes may lead to erroneous conclusion. For the same token, traditional use of large-area sample (i.e., capacitor) for evaluating oxide reliability
Fig. 4. 50% Qbdas a function of oxide thickness measured at
258C (solid circle) and 1808C (open circle) under gate injection polarity at a constant current of ÿ0.2 A/cm2. The area of the
capacitor is 4 10ÿ6 cm2. Insert shows typical V±t curves of
Qbdtests on 2.5 nm oxide at 258C and 1808C.
Fig. 5. 50% Qbd measured at 258C as a function of oxide
thickness, both under substrate injection (+1 A/cm2, solid
cir-cle) and gate injection (ÿ1 A/cm2, open circle). The area of
may also lead to erroneous conclusion for device level applications [56]. It is also reported that the oxide degradation by SBD may not signi®cantly aect tran-sistor's drain current characteristics but increase gate current and noise [4,47]. However, in more recent stu-dies, it is reported that device can still suer HBD fail-ure if the channel length of the device is suciently small (i.e., 0.2 mm) [55]. Therefore, evaluation of ultra-thin oxide reliability remains a critical concern for scaled oxides.
Since Qbd tests is no longer a valid tool to evaluate
ultrathin oxide reliability [56], the constant voltage stressing (CVS) method which represents a more realis-tic situation for pracrealis-tical applications may be more suitable for evaluating ultrathin oxide reliability [55]. Fig. 6 illustrates the TDDB characteristics for various oxide thicknesses (e.g., 4.2, 3.0 and 2.5 nm). Time-to-breakdown (Tbd) tests under dierent oxide voltages at
high ®eld stressing are often employed for predicting the oxide lifetime under normal operating ®eld (e.g. 5 MV/cm). As shown in Fig. 6, TDDB improves with decreasing oxide thickness. This can be ascribed to reduced trapped charges as well as smaller interface states generation after electrical stress as oxide is scaled to direct-tunneling regime. By extrapolating the data from Fig. 6, an electric ®eld of over 9 MV/cm at room temperature is projected for 10-year lifetime. It is worthy to note that oxide lifetime is strongly depen-dent on gate area [57]. While the total gate area on a chip is of the order of 0.1 A/cm2for future generation
technologies, the projected lifetime from Fig. 6,
there-fore, may be overestimated. Nonetheless, one can still conclude that TDDB performance is signi®cantly improved with scaled oxides.
Finally, hot-carrier induced oxide degradation has also received much attention for scaled oxides since
Fig. 6. Time-dependent dielectric breakdown (TDDB) charac-teristics vs. oxide electric ®eld for various oxide thicknesses. Extrapolation of the data is used to predict a 10-year lifetime under maximum operating oxide ®eld.
Fig. 7. Transconductance degradation after hot-carrier stres-sing for devices with 4.2 and 2.5 nm oxide. The hot-carrier stressing was performed under maximum substrate current condition.
Fig. 8. Threshold voltage (Vth) shift after hot-carrier stressing
for devices with 4.2 and 2.5 nm oxide. The hot-carrier stres-sing was performed under maximum substrate current con-dition.
hot-carrier generation becomes more signi®cant [58]. Figs. 7 and 8 depict hot carrier degradation results per-formed on 2.5 and 4.2 nm oxides. The hot carrier stress was performed with constant drain voltage of 3 V for 2.5 nm oxide and 4 V for 4.2 nm oxide, with appropriate gate bias to ensure maximum substrate current injection. These results con®rm that the degra-dation in transconductance (Fig. 7) and threshold vol-tage (Fig. 8) are much smaller for the thinner oxide, consistent with data proposed in [58] (Tox range: 1.5±
3.8 nm). Thus ultrathin gate oxide do exhibit higher hot-carrier resistance, despite the fact that it is biased under a higher electric ®eld stress due to a not propor-tionally scaled Vdd.
4. Poly-gate depletion eects
Poly depletion eects, caused by insucient active dopant concentration near the poly/SiO2 interface,
become non-negligible as the miniaturization of devices proceeds into deep sub-micrometer regime. A lower eective surface electric ®eld, due to additional voltage drop across the depletion layer, was reported to cause a signi®cant reduction in drive current [59], diculties in determining accurate oxide thickness [60], and over-estimation of dielectric lifetime [61].
Signi®cant degradation of inversion capacitance caused by poly-gate depletion was found to degrade device driving capability. The eect was more severe for devices with lower rapid thermal annealing (RTA) cycles and/or implant dose [59]. For n-MOS transistors with n+ poly-Si gate, the eect can be explained by
the physical model that As or P atoms tend to
segre-gate to grain boundaries and become inactive [61]. Since the depletion width from the poly/SiO2interface
increases if the oxide electric ®eld increases, the PDE worsens for ultrathin oxide, as the supply voltage usually does not scaled proportionally. Thus, improve-ment in device performance by oxide scaling can not be achieved without resolving this issue. Fig. 9 shows the calculated gate capacitance to oxide capacitance ratios for devices under inversion polarity as a function of eective ploy gate doping, without taking the QM eect into consideration. The gate oxide thickness ranges from 1.5 to 3.5 nm. We can see that for typical eective doping concentration of 1 1020 cmÿ3, gate
capacitance plunges to only 80% of oxide capacitance for 3.5 nm oxide (i.e., 20% degradation). The degra-dation increases to almost 35% for 1.5 nm oxide. This trend indicates that drain current gain from thinner oxide is partly compensated by poly depletion eect. A heuristic solution to this problem is to enhance the thermal budget and/or implant dose. This, however, will cause adverse side eects. Since for deep submi-cron technologies, a very steep channel dopant pro®le and ultra-shallow S/D junction are required to sup-press the so-called short-channel eects. Increasing thermal budget certainly jeopardizes the formation of steep doping pro®le. Furthermore, prolonged acti-vation cycle and higher dopant implantation bring about disastrous penetration eect for pMOS transis-tors with p+ gate. These factors reduce the available
process windows for optimal process integration as the technology is further scaled down.
Recently, several alternative process technologies were proposed to reduce or eliminate altogether poly depletion eects [62±69]. Poly-Si1ÿx Gexhas been
pro-posed as a very promising alternative gate material, since it suers from less poly depletion problem and is also less susceptible to boron penetration [62,63]. The suggested Ge content for optimum performance is about 20% [62]. In addition, refractory metals such as TiN or WNxhave also been proposed as alternate gate
materials due to its low gate resistance, and midgap work function [64±69]. Furthermore, being metallic, it is inherently immune to gate depletion problem. Nevertheless, more studies are needed regarding their process compatibility and impacts on device reliability before their acceptance by the ULSI industry.
5. Boron penetration
The eects of boron penetration into and through the gate oxides of p-channel devices are discussed in this section.
P+-polysilicon gate for p-channel device is
indispen-sable for deep-submicron CMOS technologies since it oers better short-channel behavior than conventional
Fig. 9. The calculated gate capacitance to oxide capacitance ratios as a function of eective ploy gate doping for devices under inversion polarity. No QM eect was taken into con-sideration.
buried-channel structure employing n+-polysilicon
gate. However, boron diusion from the p+-poly-Si
gate into the thin gate oxide and the underlying chan-nel region causes P-chanchan-nel devices to depict ¯atband voltage shift, threshold voltage instability, low ®eld mobility, drive current reduction, and gate oxide degradation [15,16], etc. The boron penetration eects may be modeled as the creation of a very thin sheet of negative charge at the Si/SiO2 interface, which can be
regarded as either a ®xed negative charge in the gate oxide or a shallow p-type dopant layer in the silicon substrate [14]. Previous studies have shown that boron penetration becomes more severe with increasing anneal temperature [15]. As oxide thickness scales to direct tunneling regime, the situation also worsens. Since the thermal budget must be sucient to achieve adequate gate dopant activation in order to avoid per-formance loss caused by gate depletion. These con¯ict-ing requirements make the process window between boron penetration and poly-gate depletion very strin-gent [70,71]. To resolve these issues, boron penetration eects and methods to minimize them have thus been widely studied.
Although it has been reported that ¯uorine can be used to improve gate oxide integrity for nMOS device, incorporation of ¯uorine from BF2 implantation is
known to exacerbate boron penetration [72,73]. It is also known that annealing in the presence of hydrogen will enhance boron diusion [74]. Thus it is crucial to keep the content of ¯uorine and hydrogen in the
pro-cess ¯ow as low as possible to minimize boron pen-etration. Several techniques have also been proposed for suppressing boron penetration, and they could be divided into two categories: the ®rst category is to lower the boron diusivity in the poly-silicon gate. A typical example is to employ gate structure such as a-Si or stacked poly-a-Si gates [75±77]. Another example is the use of poly-Si1ÿx Gex, which is shown to depict
reduced boron penetration [62,63]. The second cat-egory is to improve the immunity of gate dielectric to boron penetration. A typical example is to introduce nitrogen into gate oxide by various processes (e.g., nitridation or nitrogen implantation), therefore, eec-tively suppress boron penetration and improve gate oxide integrity [78].
Fig. 10 depicts threshold voltage versus various post-implantation annealing conditions for p-MOSFETs with either pure or N2O-nitrided oxides.
The source/drain implant was performed with either boron or BF2 implants. It is observed that N2
O-nitrided oxide exhibits excellent resistance to boron penetration except for samples under worst annealing condition (i.e. RTA@11008C, 20 s + FA@9008C, 1 h). This is attributed to diusion barrier enhancement by incorporation of nitrogen in gate oxide. In addition, it can be seen that using boron, instead of BF2, can
alleviate boron penetration by avoiding the so-called `¯uorine-enhanced' boron diusion. The eects of
Fig. 10. Threshold voltage (Vth) as a function of
post-implan-tation annealing condition for p-MOSFETs with pure oxides and N2O-nitrided oxides. The oxide thickness is 4.2 nm. Both
boron and BF2implants were activated for 20 s.
Fig. 11. Gate leakage current as a function of post-implan-tation annealing condition for p-MOSFETs with pure oxides and N2O-nitrided oxides. The oxide thickness is 4.2 nm. Both
boron and BF2implants were activated for 20 s. Gate leakage
current was measured at a gate voltage Vg ÿ2 V under
boron penetration on gate leakage current are shown in Fig. 11. Consistent with Fig. 10, severe boron pen-etration results in large leakage current. Samples with N2O-nitrided oxide and boron implant depict the
smal-lest leakage current, even under the worst annealing condition. By comparing Figs. 10 and 11, it appears that device performance (i.e., threshold voltage) is more sensitive to boron penetration than oxide leakage current for ultrathin gate oxides. To sum up, process optimization and the use of alternative materials for gate dielectrics or gate electrodes may be necessary for solving boron penetration problem encountered in future ultrathin gate oxide devices.
6. Plasma charging damage
Plasma charging eect, which may lead to severe oxide degradation and pro®le distortion during proces-sing, has become one of major reliability concerns in ULSI manufacturing since the late 80s [19±27]. This can be attributed to several reasons: (1) oxides become more susceptible to charging damage as Tox is scaled
below 10 nm. (2) The number of plasma steps employed in wafer fabrication increases dramatically as the chip functionality and complexity advance. (3) In order to improve the throughput or to meet the critical requirements of deep-submicron manufactur-ing, process tools with high-density plasma (HDP) reactors for etching and deposition steps are widely used. These process steps may potentially aggravate the extent of charging.
6.1. Causes for plasma charging damage
It is well known that plasma exposure may cause degradation of device performance and decrease device yield and reliability. In general, many processing steps including polysilicon etch [79±81], ion implantation [82], dielectric deposition, oxide contact and via etch [83], metal interconnect etch [84], and resist ashing [85] may each contribute to device damage. Damage could happen by the synergistic eect of ion bombardment [86], charging due to plasma non-uniformity [87±89], contamination [90], and ultraviolet radiation [91]. Here, we focus on charging damage. Charge imbalance is the main cause responsible for plasma charging damage. The local ion and electron ¯uxes are out of balance due to charge imbalance, and result in charge built-up. When voltage due to charge built-up is su-ciently large, F±N tunneling occurs. Current collected by the antenna structure is channeled through the thin gate oxide by F±N tunneling. Under such situations, electron current injected into the oxide may deposit energy in the oxide and lead to trap creation and inter-face state generation. Consequently, gate oxide
integ-rity is degraded. However, the damage depends on many factors from dierent process conditions and device applications.
Fig. 12 shows the Qbdresults as a function of device
location and antenna area ratio for oxides with thick-ness ranging from 8.7 to 2.5 nm. Charging damage is induced by a photoresist ashing step after wet metal pad de®nition. For devices with large antenna area ratio (AAR, e.g., 10K), signi®cant damage begins to appear at the wafer center as oxide thickness is scaled below 6 nm. For oxide thinner than 4 nm, oxide breakdown is induced at the wafer center. These results suggest that plasma charging damage is strongly dependent on thickness and device location.
Fig. 12. Position dependence of Qbd for various antenna
6.2. Evaluation of plasma charging damage
When entering sub-quarter micron era (i.e., Tox<6
nm), the dependence of plasma charging damage on oxide thickness presents an important and controver-sial topic. Park and Hu studied the damage induced in oxides (2.2 nm<Tox<7:7 nm) during metal and contact
etching processes, and concluded that thinner oxide has superior immunity [21]. Alavi et al. showed that, as oxide is thinned down, the damage increases up to a point (04 nm), and then decreases due to directing tunneling [22]. Similar trends were also reported by Noguchi et al. in investigating the electron shading eects [23]. On the other hand, the results of Bayoumi et al. ([24], Tox range: 8±4 nm), Krishinan et al. ([25],
Toxrange: 6±3:5 nm) and Chien et al. ([92], Toxrange:
8±4 nm) showed that the susceptibility to damage increases with decreasing oxide thickness. More recently, Krishnan et al. further indicated that severe damage could be induced in gate oxide as thin as 2.1 nm under certain inductively coupled plasma (ICP) metal etching conditions [93]. These dierent ®ndings are understandable since process conditions and equip-ment con®gurations can be very dierent from one study to another. Besides, oxide degradation character-istics under high ®eld stressing may change signi®-cantly as Tox is thinned down. Thus dierent
indicators (e.g., Qbd, breakdown ®eld, threshold
vol-tage (Vth), etc.) that are used to characterize the
damage by dierent investigators may lead to dierent outcomes.
Many test vehicles have been traditionally used in
evaluating plasma-induced antenna eects, including Qbd [94], initial-electron-trapping-rate (IETR) [95],
relative linear transconductance reduction [96], hot-car-rier-injection (HCI) [97±100], stress-induced leakage current (SILC) [101,102], and charge pumping (CP) [103,104], etc. However, as oxide is scaled into direct tunneling regime, some traditional measurements may become insensitive in detecting the charging damage. Fig. 13 depicts threshold voltage, subthreshold swing and transconductance of transistors as a function of cell location. We can see that, even with a large AAR value, these parameters vary only slightly across the wafer. In addition, no signi®cant dierence in transis-tor characteristics is found among transistransis-tors with var-ious AAR values. Based on these results, one would tend to conclude that the plasma damage is negligible. However, signi®cant damage is actually identi®ed by the Qbd measurements, as illustrated in Fig. 14. The
insensitivity of transistor parameters to charging damage could be explained by the negligible surface state generation and bulk trapping after plasma pro-cess, which is intrinsic to ultrathin oxides. Therefore, one would have to conclude that some traditional methods are no longer sensitive for detecting charging damage for ultrathin oxides. Other methods, such as charge-to-breakdown, gate leakage current and noise measurement, are more sensitive and, therefore, more suitable for characterizing the plasma charging eects. In fact, for deep submicron devices, the situation may probably become more complicated. Thus, evaluation of plasma charging damage of ultrathin oxide device should be carefully examined.
Fig. 13. Threshold voltage (Vth), subthreshold swing, and
transconductance as a function of cell position. Antenna area ratio of the devices is 20K. Oxide thickness is 2.5 nm. No
sig-ni®cant position dependence is observed across the wafer. Fig. 14. Charge-to-breakdown (Qcell position. Channel length and width of the measured tran-bd) values as a function of sistors are 1.2 and 10 mm, respectively.
6.3. Methods to improve plasma charging immunity Since plasma charging damage could cause serious device degradation, several approaches are employed to alleviate it. These approaches include using protec-tion diode [105,106], setting tight design rules for cir-cuit, and introducing robust gate dielectrics [107]. Protection diode may be the most eective method to eliminate charging damage. However, additional lay-out/process and loss of integrity are its main draw-backs. The resort to design rule, on the other hand, limits the circuit layout ¯exibility. Finally, N2
O-nitrided oxide can be employed to eectively suppress the charging damage. In contrast with pure oxide, the leakage current characteristics of antenna devices with nitrided oxide are signi®cantly improved, as shown in Fig. 15. Only slight increase in gate leakage current is observed on antenna devices with nitrided oxide. These improvements can be attributed to the formation of strong Si±N bonds replacing strained Si±O bonds and weak Si±H bonds [107]. The enhanced interface
hard-ness of nitrided oxide results in improved gate oxide integrity. Therefore, N2O-nitrided oxide is an
extre-mely eective approach to improve the immunity to plasma damage in ultrathin oxides.
7. Conclusion
The continued scaling of ULSI technologies has demanded immediate attention to reliability issues of ultrathin oxides. In this work, we have reviewed recent status on the issues relating specially to the reliabilities of ultrathin gate dielectrics for present and future ULSI technologies. Several challenges facing the appli-cation of ultrathin gate oxides are discussed and can be summarized as followed:
1. The quantum mechanical tunneling current will eventually become a scaling limitation for the con-tinued brute-force scaling of thermal silicon dioxide as gate dielectric. Alternative gate dielectrics with lower leakage current and comparable performance have to be introduced before the thermal oxide eventually becomes the show-stopper.
2. Ultrathin gate oxides exhibit superior TDDB characteristics. However, its increased dependence on temperature and polarity should be carefully taken into consideration in process integration, es-pecially for processing steps that require high tem-perature.
3. Better understanding of breakdown mechanism of ultrathin oxide is essential for device lifetime predic-tion under normal operapredic-tion condipredic-tion, and for choosing proper reliability evaluation indicators. 4. The con¯icting requirements in thermal cycle for
poly depletion eect and boron penetration will severely restrict the process window. Alternative gate dielectrics and electrode materials may be inevi-table in order to resolve this issue.
5. Plasma charging damage remains a major concern for ultrathin oxide reliability. More eorts need to be made to understand and minimize the charging damage.
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