國 立 交 通 大 學
電子工程學系 電子研究所碩士班
碩 士 論 文
高壓元件 LDMOS 可靠度分析
與 SPICE 模型建立
Investigation of Spice Modeling and Reliability
Issues in High Voltage LDMOS
研 究 生 ：杜冠潔
指導教授 ：汪大暉 博士
中華民國 九十五 年 六 月
高壓元件 LDMOS 之特性分析與 SPICE 模型建立
Investigation of Spice Modeling and Reliability
Issues in High Voltage LDMOS
研 究 生 : 杜冠潔 Student : Kuan-Chieh Tu
指導教授 : 汪大暉 博士 Advisor : Dr. Tahui Wang
國立交通大學
電子工程學系 電子研究所碩士班
碩士論文
A Thesis
Submitted to Department of Electronics Engineering & Institute
of Electronics
College of Electrical Engineering and Computer Science
National Chiao Tung University
in Partial Fulfillment of the Requirements
for the Degree of Master
in
Electronic Engineering
June 2006
高壓元件 LDMOS 可靠度分析與 SPICE 模型建立
學生：杜冠潔
指導教授：汪大暉 博士
國立交通大學 電子工程學系 電子研究所
摘要
隨著半導體產業的發展，高功率元件經常被應用在許多電力電子方面。 LDMOS(平面二次擴散之金氧半場效電晶體)通常在高壓積體電路中作為驅動元 件。本論文內容探討 LDMOS 的基本特性，並建立 SPICE 模型，最後作可靠性分 析。 由於結構與傳統 MOSFET 有所不同，故在應用上缺少內建的高壓元件模型， 本論文中，利用子電路（sub-circuit）的模擬方法來建立 LDMOS 電流-電壓 SPICE 模型。此子電路中主要部分包含了一個傳統 MOSFET 與一個受閘極與汲極控制 的可變電阻。首先，先以一個 MOS 模型描述邊際效應(Fringe effect)所產生的邊 際電流(fringe current) ; 再利用 LDMOS 在低閘極電壓與高閘極電壓有著不同特 性的現象，從低閘極電壓區域萃取出 MOS 模型，再藉由此 MOS 模型反算出外掛 電阻模型，最後以自我熱效應公式修正模擬值，即完成一單一尺寸 LDMOS 模型。 並考慮不同尺寸與操作環境的應用，將四個邊界尺寸模型做箱化，以期最後可適 用於各種尺寸與操作模式的元件。在 LDMOS 可靠性研究上，我們使用電荷幫浦的實驗方法(Charge Pumping Technique)探討不同的加壓條件下，不同的區域各有何不同的損害產生。
模型，而不需要 MESDRIFT 結構(多了一個接觸點佈值); 並可以對尺寸做模型箱 化，成功的使模型可以準確模擬不同尺寸與環境的 LDMOS。而在可靠度的研究 上也發現，在有最大閘極漏電流的加壓條件下，LDMOS 的熱載子退化現象最為 明顯。
Investigation of Spice Modeling and Reliability
Issues in High Voltage LDMOS
Student: Kuan-Chieh Tu Advisor: Dr. Tahui Wang
Department of Electronics Engineering &
Institute of Electronics
National Chiao Tung University
Abstract.
Power metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely applied to power electronics owing to great semiconductor industry. LDMOS (lateral Double-Diffused MOSFET) is usually the driver component in high voltage integrated circuits. In our study, we will engage in the characteristics of LDMOS including of SPICE macro model and the reliability issues.
Because the architecture of a LDMOS is different from it of a MOSFET, there is still a lack of SPICE model for LDMOS. In our study, we use the sub-circuit method to model a LDMOS device. The method mainly consists of an intrinsic MOS model and a gate and drain voltage controlled resistance. In addition, we model the extra fringe currents by giving a fringe MOS model. After deducing the influence of the fringe effect, we extract the MOS
model from I-V measured data in low-Vg stage region and reverse calculate the external resistance in high-Vg stage region using the MOS model. Finally, the model is amended by correcting function of self-heating. Not only achieving a single size device, we also consider the application of LDMOS scaling problems and various operation modes. Therefore, we used the binning technique to bin the models from four corner size models to generate a universal SPICE macro model suitable for various devices of different sizes and operation conditions.
Another part of our study is the investigation of the reliability issue of various hot-carrier degradation modes. We identify the properties of trap types and locations of oxide damage under different hot-carrier stress modes by using a novel three-region charge pumping technique.
According to our study, we can conclude that: We don’t need MESDRIFT devices and can extract a SPICE macro model from LDMOS. And the research about reliability of LDMOS shows that there is most serious hot-carrier degradation under max. Ig stress condition.
致謝
謝謝曾經協助我論文的每個人。這段旅程的完結開啟了下一段冒
險的序幕。
Contents
Chinese Abstract
i
English
Abstract
iii
Acknowledgements
I v
Contents
vi
Figure
&Table
Captions
viii
Chapter 1 Introduction
1
Chapter 2 Analysis of LDMOS Characteristics
4
2.1
Introduction
4
2.2
Basic Structure and I-V Curve Discussions of LDMOS
4
2.2.1 LDMOS Basic Structure and I-V Curve Discussion
4
2.2.2 Quasi-saturation effect
5
2.3 Special Issues of LDMOS
9
2.3.1
Fringe
Effect
9
2.3.2
Self-Heating
Effect
9
2.3.3 Hot-Carrier Effect
10
Chapter 3 Spice Model of LDMOS 15
3.1
Introduction
15
3.2 Two Stages Model
17
3.2.1 Motivation and Extraction Flow of Two Stages Model
17
3.2.2 Physical Concepts of Two Stages Model
22
3.2.3 Single size Modeling Result
27
3.2.4 Universal Modeling Results
29
3.3
Fringe
Effect
Model
of
LDMOS
31
Chapter 4 Characterization of Various Hot-Carrier
Degradation Modes 45
4.1
Introduction
45
4.2 Three-Region Charge Pumping Technique
47
4.3 Various Hot-Carrier Degradation Modes
47
4.3.1
Max.
Ib
Stress
(Mode
A)
47
4.3.2
Vg~Vd/2
Stress
(Mode
B)
47
4.3.3 Max. Ig Stress (Mode C)
48
4.3.4 Results and Discussion
48
Chapter
5
Conclusion
and
Future
Work
59
Reference
60
Figure & Table Captions
Fig. 1.1 Applications for power semiconductor devices provided as a function of system operating frequency and power handling capability.
Fig. 1.2 Applications for power devices in relation to their voltage and current ratings. Fig. 2.1 Schematic cross section of NLDMOS device used in our study.
Fig. 2.2(a) Measured Id-Vg characteristics at Vd=0.1 of NLDMOS (W=20µ , m L=1.7µ ). m
Fig. 2.2(b) Measured Id-Vd characteristics at Vg=2, 0.5, 17, 24.5, 32V of NLDMOS (W=20µ , L=1.7m µ ). m
Fig. 2.3 The schematic top view and side view pictures of LDMOS. Fig. 2.4 Measured normalized Id (by width)-Vg of NLDMOS
Fig. 2.5 ΔI of measured normalized Id (by width of 5µ ) subtracting Normalized Id m (by width of 20µ )-Vg of NLDMOS m
Fig. 2.6 Measured I-V characteristics of NLDMOS (W=3µ , L=20m µ )with m Self-Heating effect.
Fig. 3.1 Spice Macro Model Extraction Flow. Fig. 3.2 Illustration of sub-circuit model concept.
Fig. 3.3 Measured Id-Vd Curve of a LDMOS illustrates concepts of two stages. Fig. 3.4 Schematic cross section of LDMOS which is with K contact.
Fig. 3.5 I-V comparison between KPC and LDMOS devices.
Fig. 3.6 Illustration of different controlling components in HV and LV stages. Fig. 3.7(a) Macro model extraction flow.
Fig. 3.7(b) Illustration of sub-circuit model concept.
Fig. 3.8 Illustration of different ways of modeling I-V characteristics of LDMOS. Fig. 3.9 Vc-Vg curve of LDMOS.
Table.3.1 Three physical concepts of Vcsat.
Table.3.2 Modeling dependence related to parameters. Fig. 3.10(a) Illustration of the concept of early saturation. Fig. 3.10(b) Illustration of the concept of drain resistance. Fig. 3.10(c) Illustration of the concept of velocity saturation.
Fig. 3.11(a) Comparison between measured and simulated Id-Vg (in linear region) curve. (W/L=20/20µ )m
Fig. 3.11(b) Comparison between measured and simulated Id-Vd curve. (W/L=20/20µ ) m Fig. 3.11(c) Comparison between measured and simulated Id-Vg (in saturation region)
curve. (W/L=20/20µ ) m
Fig. 3.12 Comparison between measured and simulated I-V data.
(W=3μm/L=1.7μm)
Fig. 3.13(a) Comparison between simulated and measured Idlin-Vg & Idsat-Vg.(W=20μm/L=20μm)
Fig. 3.13(b) Comparison between simulated and measured Idlin-Vg & Idsat-Vg.(W=3μm/L=1.7μm)
Fig. 3.14(a) Comparison between simulated and measured Idsat-T. (W=20μm/L=20μm)
Fig. 3.14(b) Comparison between simulated and measured Idsat-T. (W=3μm/L=1.7μm)
Fig. 3.15 The diagram of whole sizes of LDMOS devices in our work. Fig. 3.16 Binning strategy of a universal macro model of LDMOS
Fig. 3.17(a) Comparison between measured and simulated Id-Vg (in linear region) curve. (W/L=3/5µ )m
Fig. 3.17(b) Comparison between measured and simulated Id-Vd curve. (W/L=3/5µ ) m Fig. 3.17(c) Comparison between measured and simulated Id-Vg (in saturation region)
curve. (W/L=3/5µ ) m
Fig. 3.18 Comparison of measured and simulated Idsat versus length.
Fig. 3.19 Comparison of measured and simulated Idsat versus T. (W=3μm). Fig. 3.20 The schematic picture of the fringe currents..
Fig. 3.21 I-V characteristics of fringe MOS.
Fig. 3.22 Comparison of measured and simulated Id-Vg (at Vd=0.1V) curve. Fig. 3.23 Illustration of the way of modeling the self-heating effect.
Fig. 3.24 Comparison of measured and simulated Id-Vd curve with self-heating effect. Table. 4.1 Summary of trap property and device performance degradations in various
stress modes
Fig. 4.1 Gate current/bulk current versus gate voltage in a LDMOS. Fig. 4.2 Basic experimental set-up for charge pumping measurements.
Fig. 4.3 Different energy regions associated with the four components of the charge pumping currents.
Fig. 4.4 (a) Cross-section of a N-LDMOS and flat-band voltage distribution in each region. Three different regions are indicated by Lchan
(channel region), Lacc(accumulation region), and Lfox(field oxide
region). (b)Illustration of the charge pumping measurement waveform. The Vgh is fixed and Vgl is variable.
Fig. 4.5 Typical CP current in a N-LDMOS. The three stages of the CP current correspond to the three different regions of device and each stage has their flat-band voltage which is indicated in the Fig. The measurement frequency of CP is fixed at 200KHz for following experiments.
Fig. 4.6 Charge pumping result before and after 1400 sec. mode A stress. The
increase of Icp2 indicated the Nit generation in accumulation region. No trap creation is observed in channel region ((∆Icp1=0).
flat-band voltage implied the increase of oxide charge in accumulation region. Fig. 4.8 (a) Region(II) oxide trapped charge density (average Qox2) versus stress time in stress mode B. (b) Linear drain current degradation (Idlin) rate measured at Vg/Vd=40V/o.1V in stress mode B.
Fig. 4.9 (a) Charge pumping result before and after 1000 sec. mode C stress. Upward shift in region (I) indicated the interface trap generation in channel region and rightward shift in region (II) implied the oxide charge creation in
accumulation region. (b) Simulation of impact ionization generation (IIG) distribution in stress mode C. Two IIG regions are found.
Fig. 4.10 Subthreshold characteristics before and after mode C stress. The swing degradation was due to interface trap generation in channel region. Fig. 4.11 The linear drain current before and after mode C stress. The drain current
degradation is mode significant at a larger Vg and is due to oxide charge creation in accumulation region.
Fig. 4.12 Region (I) interface trap density (average Nit1) versus stress time in stress
mode C.
Fig. 4.13 Region (II) oxide charge density (average Qox2) versus stress time in stress
mode C.
Fig. 4.14 Idlin degradation versus stress time in stress mode C. The degradation is due to oxide charge creation in accumulation region.
