DOI 10.1007/s00170-003-2031-1 O R I G I N A L A R T I C L E
Muh-Cherng Wu · C.S. Chien · K.S. Lu
Downgrade decision for control/dummy wafers in a fab
Received: 22 August 2003 / Accepted: 10 November 2003 / Published online: 1 December 2004 ©Springer-Verlag London Limited 2004
Abstract Control and dummy (C/D) wafers are indispensable materials used in a semiconductor fab. C/D wafers stored in a high-grade buffer can be downgraded to several low-grade buffers. The downgrade decision is to determine the amount to downgrade for each of these low-grade buffers. Previous liter-ature solves the downgrade decision by considering only the instantaneous WIP information, which is a short-term approach and may not yield the optimum solution in the long run. This paper presents an LP model to solve the downgrade decision problem, which aims to minimize the long-term daily usage of brand-new C/D wafers in a fab. The formulated problem assumes that the storage cost of C/D wafers is much less than the usage cost. This assumption has been justified by analyzing the cost structure of C/D wafers in a typical fab site.
Keywords Control wafers · Downgrade decision · Dummy wafers· Monitor wafers · Semiconductor fab · Test wafers
Notation
Designation and sets
ci: Designation of C/D buffer i; 0ir+1, c0is the releas-ing buffer; cris the reclaiming buffer, cr+1is the scrapping buffer, and ci(1ir− 1) is a working buffer.
P(i ): The set of ancestor buffers of ciin diagraph G, excluding c0; i.e., c0 /∈ P(i )
S(i ): The set of descendant buffers for ciin diagraph G Parameters
Di: Average daily demand of C/D wafers in ci, 1ir− 1
m(i ): Maximum number of cleaning recycle in ci, 1ir− 1 r[k]i : The yield of the kth cleaning recycle in ci, 1km(i ) M.-C. Wu (u) · C.S. Chien · K.S. Lu
Department of Industrial Engineering and Management, National Chiao Tung University,
Hsin-Chu, Taiwan, R.O.C. E-mail: mcwu@cc.nctu.edu.tw Tel.: +886-35-731913 Fax: +886-35-720610
n: Maximum number of grinding reclaim in cr
h[k]: The yield of the kth grinding reclaim in cr, 1kn
Variables
Oij: Daily quantity of C/D wafers downgraded from cito cjin diagraph G
Ni: Daily quantity of brand-new C/D wafers downgraded to ci from c0
N: Daily quantity of brand-new C/D wafers downgraded from c0; N=ri=1−1Ni
Yi: Daily quantity of reclaimed C/D wafers downgraded to ci from c0
Z[k]: Daily quantity of C/D wafers, with k times of reclaim, sent to c0from cr
Z: Daily quantity of reclaimed C/D wafers sent to c0from cr,
Z=nk=1Z[k]
X[k]i : Daily quantity of C/D wafers in ci with kth cleaning recycle
1 Introduction
In semiconductor manufacturing, control wafers and dummy wafers are indispensable materials, used in ensuring the pro-duction quality. Control wafers, also called test wafers or mon-itor wafers, are used to monmon-itor the wellness of tools and pro-cesses. To validate a tool/process, control wafers may be run before or concurrently with product wafers. Output parameters are then taken from control wafers to make adjustments on the tool/process, if necessary. Control wafers are often categorized into two types: particle wafers and thickness wafers. Particle wafers are for measuring the particle number to know the cleanli-ness of a tool. Thickcleanli-ness wafers are for measuring the deposition rate, etching rate or grinding rate of a particular process. Dummy wafers, generally lower in grade than control wafers, are often used in tools such as oxidation furnaces to provide a uniform temperature environment for better quality. In this paper, C/D wafers refer to either control or dummy wafers.
A semiconductor fab keeps many types of C/D wafers with different specifications. C/D wafers of a particular specification are stored in a dedicated buffer, which supplies the C/D wafers to one or many tools. A C/D wafer, after being used in a tool, is sent to a cleaning recycle process within the fab for possible reuse. The recycled C/D wafers, if they meet the original specification, are kept in the present buffer. Those becoming lower in grade are downgraded to some other buffers. C/D wafers in a buffer can be repeatedly recycled up to a limited number of times. A buffer therefore stores various categories of C/D wafers, featuring in having received different times of recycles.
The process flow of using C/D wafers typically involves the following five steps: preprocessing, in-use, cleaning recycle, downgrade, and grinding reclaim. A thickness wafer for measur-ing the etchmeasur-ing rate of a process is used to explain each step. The preprocessing step is to deposit a film on the control wafer. The in-use step measures the thickness of the film before and after the etching process to monitor the process quality. The clean-ing recycle step, as mentioned, is an “in-house” operation, used to remove the film and clean the control wafer for reuse. The downgrade step is to deliver the C/D wafer to buffers that require lower grade. The grinding reclaim, often carried out by ven-dors, is to grind off some 20–30 um silicon materials from the C/D wafer. A reclaimed C/D wafer, becoming higher in grade, is functionally like a brand-new C/D wafer. The number of grind-ing reclaims for a C/D wafer is limited.
For a downgrade procedure, the buffer that delivers C/D wafers is called an ancestor buffer, and that which receives is called its descendant buffer. The C/D wafers in an ancestor buffer always have higher grade than those of its descendant buffers. The downgrade relationship among the C/D buffers is a directed graph as shown in Fig. 1. A buffer may have several descendant buffers. Taking C1 as an example, C2, C3, C4, C5and C6are its
descendant buffers.
Much literature on C/D wafers has been published. Wong and Hood [1] study the impact on cycle time and throughput caused by increasing the number of process monitoring, which conse-quently increases the demand of C/D wafers. Wu [2] studied the dispatching policy of C/D wafers in the preprocessing stage, where C/D wafers share the tool capacity with product wafers. Popovich et al. [3] developed an automated ordering process to maximize the reuse of test wafers. Chu [4] investigated the pol-icy for setting safety stock level in each C/D buffer. Watanabe et al. [5] studied how to increase the use ratio of reclaimed C/D wafers to reduce the cost.
Some others addressed the problem of downgrading C/D wafers, that is, how many C/D wafers should be delivered to each of its descendant buffers from a particular buffer? Foster et al. [6] established a discrete event simulation program for justifying the effects of various downgrading decisions. Chen and Lee [7] proposed a real-time downgrading policy, called the “push ap-proach”. That is, as soon as a particular amount of C/D wafers in a buffer are available for downgrading, they are immediately sent to the descendant buffer, which is heuristically justified as the most needed. Some linear programming models for downgrading C/D wafers, where the desicions are made periodically (e.g., per
Fig. 1. Downgrade relationships among C/D buffers
day), have been developed [8, 9]. In these studies, the developed models consider only the instantaneous WIP level of each buffer at the decision time point, therefore, the obtained solutions may not be optimum in the long run.
By analyzing the cost structure of C/D wafers of several fab sites, the WIP cost only accounts for about 2.4% of the usage cost. Therefore, we assume that the safety stock of C/D wafers at each buffer can be sufficiently prepared in order to absorb the impacts of time-varying properties and unexpected events. Based on this assumption, the downgrade decision problem is simplified. That is, the average daily demand and average daily recycle yield of each buffer are used to characterize the problem. An LP model is accordingly formulated to make the downgrade decision.
The remainder of this paper is organized as follows. Section 2 analyzes the cost structure of C/D wafers and discusses the ef-fects of preparing sufficient safety stocks. Section 3 describes the LP model. An example of the LP model is explained in Sect. 4 and some concluding remarks are stated in Sect. 5.
2 Cost structure of C/D wafers
The cost of C/D wafers in a fab involves three major items: (1) the cost of machine idleness due to lack of C/D wafers, (2) the usage cost of C/D wafers, and (3) the storage cost of C/D wafer (WIP) in shop floor. To analyze the impacts of these three cost items, we interviewed several 8 in fab sites in industry. The rel-evant cost data of a typical 8 in fab is discussed below.
The throughput of the 8 in fab is 30 000 wafers/month. The C/D wafers released to the fab, which includes both brand-new and reclaimed ones, is about 21 000 wafers/month. The average
WIP of C/D wafers is about 50 000 wafers. The cost of a brand-new C/D wafer is about $ 70/wafer. The reclaimed cost is about $ 10/wafer. A C/D wafer in average receives two times the grind-ing reclaim, that is, a brand new C/D wafer would generate two reclaimed C/D wafers. The brand new C/D wafers released to the fab is therefore 21 000× (1/3) = 7000 wafers/month. The reclaimed C/D wafers released to the fab is 21 000× (2/3) = 14 000 wafers/month. The monthly usage cost of C/D wafers is thus(7000 × $ 70) + (14 000 × $ 10) = $ 630 000/month.
For the WIP, the ratio between brand-new and reclaimed C/D wafers is 1: 2. Therefore the average cost per C/D wafer WIP is ($ 70 ×1+$ 10 ×2)/3 = $ 30. Suppose the monthly interest rate is 1%. The monthly storage cost of C/D wafer WIP is($ 30) × (50 000) × (1%) = $ 15 000/month, which is about 2.4% of the usage cost.
The cost of machine idleness, due to lack of C/D wafers, is quite high. Therefore, a typical fab requests that the safety stock level of C/D wafers be so high that the machine would not become idle. Taking thickness C/D wafers as an example, the preprocessing for depositing a film takes about 5 h. In the worst case, the lack of thickness C/D wafers would cause an etching machine to be idle for 5 h. The hourly depreciation cost of an etching machine is about $ 30. Suppose the etching machine is idle for 5 h per month, the idle cost is about $ 150/month. Yet, the monthly storage cost of keeping a lot (25 pieces) of prepro-cessed C/D wafers per month is only about $ 7.5 = $ 30/wafer × 25 wafers× (1%). The cost of machine idle is therefore much higher than the WIP cost of C/D wafers.
From the above analysis, we can reasonably assume that the safety stock level of C/D wafers should be so high that the WIP in buffers can always fulfill the time varying demand. Fig-ure 2 shows the profile of a time-varying demand of a C/D buffer, D(t) = D + e(t), where D(t) denotes the demand in day
t, D=tD(t)/tdenotes the average daily demand and
e(t) denotes the daily variation from mean. The safety stock
level, denoted by s, can then be so prepared, s= Maxt{e(t)} to
avoid the machine being idle due to lack of C/D wafers. Based on such a safety stock preparation, we can consider the down-grade decision as a static decision problem. That is, the input and output daily flow rates of each C/D buffer are constants and should be balanced.
Fig. 2. Time-varying demand and safety stock of a C/D buffer
3 Problem formulation and modeling
3.1 Problem description
In a typical fab, the downgrade relationship among all buffers is a directed graph (Fig. 1). The directed graph involves four types of C/D buffers. Working buffers (c1− c6) directly supply C/D
wafers to tools. The releasing buffer (c0) releases brand-new or
reclaimed C/D wafers to working buffers. The reclaiming buffer (c7) reclaims C/D wafers, and sent them to either the releasing
buffer or the scrapping buffer. The scrapping buffer (c8) stores
the C/D wafers that cannot be reclaimed further and needs to be scrapped. Working buffers are many in number, while each other type involves only one.
A working buffer stores m categories of C/D wafers, where
m denotes the maximum number of cleaning recycles. Category i (1im) represents C/D wafers that have received i times
of cleaning recycle. A C/D wafer in category i, after receiv-ing one more cleanreceiv-ing recycle, becomes one in category i+ 1. Any C/D wafer in a particular working buffer, whatever cate-gory it belongs to, is regarded as functionally identical or the same in specification. Notice that each cleaning recycle in a cer-tain buffer has a distinct yield rate; the out-of-specification C/D wafers should be forcedly downgraded. Figure 3 shows the vari-ous categories of C/D wafers in each working buffer of Fig. 1.
Each working buffer stores C/D wafers with different speci-fication. C/D wafers higher in specification can be downgraded to buffers with lower specification. Downgrade relationships among the working buffers therefore can be established by ex-amining their specifications. The releasing buffer, the highest in specification, can downgrade wafers to any working buffer. The reclaiming buffer, next to the lowest in specification, can receive downgraded wafers from any working buffer. The scrap-ping buffer, the lowest in specification, only accepts C/D wafers from the reclaiming buffer. A C/D wafer can receive at most
n times of grinding reclaim, with a distinct yield rate in each
reclaim. Out-of-specification C/D wafers as well as those that cannot be reclaimed further are sent to the scrapping buffer.
Reclaimed C/D wafers, if within specification, are sent back to the releasing buffer. These wafers are regarded as
function-Fig. 3. A working C/D buffer stores several categories of C/D wafers
ally identical to the brand-new buffers. Let the downgrade path between the reclaiming buffer and the releasing buffer be called the feedback path. By eliminating the feedback path, the directed graph becomes one without loop.
The graph without a loop can be denoted by G= (V, E), con-sisting of a finite set of nodes V= {c0, c1, . . ., cr, cr+1} and a set
of arcs E. Herein, a node represents a buffer. An arc represents an ordered pair of two nodes. We denote an arc from ci to cj
by ci→ cj; ci is the predecessor of cj and cj is a successor of ci. A path from ci to cj exists if one can traverse from ci to cj
through passing k arcs(k1). If there is a path from node cito
node cj, then ci is said to be an “ancestor” of cj, and cj is said
to be a “descendant” of ci. The diagraph without loop means that
any two nodes cannot be ancestor of each other. Node c0
repre-sents the releasing buffer, cr the reclaiming buffer, and cr+1the scrapping buffer. Node ci(1ir− 1) is a working buffer.
Note that the aforementioned diagraph G does not include the feedback path (cr→ c0). As a result, the downgrade
relation-ships among all the buffers can be denoted by a diagraph with loop, S= (G, f), where G is the graph without loop and f is the arc cr→ c0.
Referring to the diagraph S= (G, f), the downgrade deci-sion problem is to determine the daily flow rate of C/D wafers to
be downgraded among buffers so that the brand-new C/D buffers released to the fab is minimized.
3.2 Model
The linear program for the downgrading decision problem can be formulated below: Min r−1 i=1 Ni s.t. N+ Z = r−1 j=1 Nj+ r−1 j=1 Yj (1) Nj+ Yj+ i∈P( j ) Oij= X[0]j 1jr− 1 (2) X[k]j = r[k]j · X[k−1]j 1jr− 1 (3) m( j ) k=0 X[k]j = Dj 1jr− 1 (4) j∈s(i ) Oij= X[0]j 1jr− 1 (5) j∈P(r) Ojr= n k=1 Z[k]+ Or,r+1 1jr− 1 (6) Z[1]= h[1]· N (7) Z[k]= h[k]· Z[k−1] (8) Or,r+1= N (9) N= r−1 i=1 Ni (10) Z= r−1 i=1 Zi (11) Ni0; Zi0; Yi0; Oij 0.
In the aforementioned LP model, the decision problem is modeled as a static system. The flow in each buffer or in the fab should be balanced. That is, the input flow rate should equal the output flow rate. Otherwise, the WIP of C/D wafers in the fab will finally increase to infinity or decrease to zero.
The objective function is to minimize the daily usage of brand-new wafers. Constraint Eq. 1 denotes the flow balance re-lationship in the releasing buffer c0. The definition of N and Z
is given in Eqs. 10 and 11. Constraints Eq. 2 indicate the inputs to a working buffer. Constraints Eq. 3 describe the yield rela-tionship of a cleaning recycle in a working buffer. Constraints Eq. 4 denote that the demand of C/D wafers in a working buffer
ci is supplied by several categories of C/D wafers, with a
of a working buffer. The left-hand side describes where the out-put C/D wafers are downgraded. The right-hand side denotes the sources of the output, which is X[0]j by considering the flow bal-ance relationship of buffer ci.
Constraint Eq. 6 denotes the flow balance relationship of the reclaiming buffer cr. The inputs of cr are from all working
buffers, represented in the left-hand side. The output involves two types of reclaimed C/D wafers, either within specification for reuse or out-of-specification for scrapping. Constraints Eqs. 7 and 8 represent the yield relationships of grinding reclaim. Con-straint Eq. 9 denotes that flow balance of the whole fab, that is, all brand-new buffers finally have to go to the scrapping buffer cr+1.
3.3 Model refinement
The aforementioned model can be refined as follows, by reduc-ing the number of constraints.
Min r−1 i=1 Ni s.t. N= r−1 j=1 Nj (12) n k=1 k i=1 h[i] · N = r−1 j=1 Yj (13) Nj+ Yj+ i∈P( j ) Oij= Dj 1+mk=1( j ) ki=1r[i]j 1jr− 1 (14) j∈s(i ) Oij= Dj 1+mk=1( j ) ki=1r[i]j 1jr− 1 (15) j∈P(r) Ojr= n k=1 k i=1 h[i]+ 1 · N 1jr− 1 (16) Or,r+1= N . (17)
Considering constraints Eqs. 7 and 8, we can derive Z[K]=
k
i=1h[i]· N and then Z = n
k=1 k
i=1h[i]· N. Constraint Eq. 1
can therefore be decomposed into constraints Eqs. 10 and 11, which respectively models the brand-new wafers and reclaimed wafers released from c0.
Likewise, by considering constraints Eqs. 3 and 4, we can de-rive X[k]i = ki=1r[i]j · X[0]j , subsequently
1+mk=1( j ) ki=1r[i]j · X[0]j = Dj, and finally X[0]i = Dj 1+m( j ) k=1 ki=1r[i]j . Constraint Eq. 2 can then be replaced by constraints Eq. 14, and constraint Eq. 5 by Eq. 15. Notice that the right-hand side of constraint Eq. 5 equals X[0]i , due to the flow balance relationship. Con-straint Eq. 6 can be replaced by conCon-straint Eq. 16 by considering constraint Eq. 9 as well as Z=nk=1 ki=1h[i]· N.
4 Example
The refined LP model is explained by the example as shown in Fig. 1, which involves nine buffers, one releasing buffer (c0),
six working buffers (c1–c6), one reclaiming buffer (c7), and one
scrapping buffer (c8). The daily demand and the yield of recycle
of each working buffer are shown in Table 1. The yield informa-tion of the reclaiming buffer is n= 2, h[1]= 0.9, and h[2]= 0.8.
The LP model of the example is described below.
Min N1+ N2+ N3+ N4+ N5+ N6 N− N1− N2− N3− N4− N5− N6= 0 (0.9 + 0.9 × 0.8)N − Y1− Y2− Y3− Y4− Y5− Y6= 0 N1+ Y1= 65/(1 + 0.9) N2+ Y2+ O12= 38/(1 + 0.9 + 0.9 × 0.8) N3+ Y3+ O13= 26/(1 + 0.9 + 0.9 × 0.8) N4+ Y4+ O14= 36/(1 + 0.9) N5+ Y5+ O15+ O25 = 110/(1 + 0.9 + 0.9 × 0.8 + 0.9 × 0.8 × 0.7 + 0.9 × 0.8 × 0.7 × 0.6) N6+ Y6+ O16+ O26+ O36+ O46+ O56 = 48/(1 + 0.9 + 0.9 × 0.8) O12+ O13+ O14+ O15+ O16+ O17= 65/(1 + 0.9) O25+ O26+ O27= 38/(1 + 0.9 + 0.9 × 0.8) O36+ O37= 26/(1 + 0.9 + 0.9 × 0.8) O46+ O47= 36/(1 + 0.9) O56+ O57= 110/(1 + 0.9 + 0.9 × 0.8 + 0.9 × 0.8 × 0.7 + 0.9 × 0.8 × 0.7 × 0.6) O67= 48/(1 + 0.9 + 0.9 × 0.8) O17+ O27+ O37+ O47+ O57+ O67= (1 + 0.9 + 0.9 × 0.8)N O78= N Nj0, Yj0, Oij0
We use software package CPLEX to solve the problem. The optimum solution of the LP model is multiple. The minimum daily flow rate of C/D wafers (N) is 23.3 wafers/d. Table 2 presents one of the optimum solutions, which is provided by CPLEX.
Table 1. Demand and yield of recycle at working buffer cj
Buffer c1 c2 c3 c4 c5 c6 Dj 65 38 26 36 110 48 m( j ) 1 2 2 1 4 2 r[1]i 90% 90% 90% 90% 90% 90% r[2]i – 80% 80% – 80% 80% r[3]i – – – – 70% – r[4]i – – – – 60% –
Table 2. Downgrade decision of an optimum solution To C1 C2 C3 C4 C5 C6 C7 From C0 100% C1 42.4% 29% 28.6% C2 100% C3 100% C4 100% C5 57% 43% C6 100% C7 29% 24.3% 46.7%
Table 2 shows that the releasing buffer c0 downgrades the
C/D wafers only to c1. Buffer c1downgrades a certain
percent-age of C/D wafers to c2 (42.4%), c3 (29%) and c4 (28.6%) but
downgrades nothing to c5, c6 and c7. Notice that the last row in
Table 2 indicates the output flow of reclaimed wafers (Yi) from
buffer c0, which is also the output from the reclaiming buffer c7.
The fab can use the downgrade percentage of each buffer, pro-vided by the obtained solution, to control the daily flow of C/D wafers to minimize the long-term usage of C/D wafers.
5 Concluding remarks
An LP model for the decision of downgrading C/D wafers is proposed. The model assumes that the safety stock is so highly prepared that the decision becomes a static flow balance prob-lem. The system addressed in the decision problem is a diagraph, where each node represents a buffer. For each buffer, the input flow rate should-use-dialog-box-p equal the output flow rate. The assumption of sufficient safety stocks has been reasonably
jus-tified by analyzing the cost structure of C/D wafers through the interview of several fab sites in industry.
The LP model may provide multiple optimum solutions, which are infinite in number and can be characterized by a solu-tion space. Future work of this research involves identifying the best one from the solution space, by additionally considering the safety stock costs, transportation costs, and fab space constraints. Acknowledgement The authors would like to thank the Taiwan Semicon-ductor Manufacturing Corp. for characterizing this research problem.
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