250 IEEE ELECTRON DEVICE LETTERS, VOL. 16, NO. 6 , JUNE 1995
Novel Tunneling Dielectric Prepared by
Oxidation
of
Ultrathin Rugged Poly silicon
for
5-V-Only Nonvolatile Memories
H. P. Su,
H. W . Liu, P. W.Wang,
K. L.
Cheng, I. M.Jen,
G.Hong,
and H. C. Cheng, Member, IEEEAbstract- A novel dielectric fabricated by thermal oxidation of ultrathin rugged polysilicon film is proposed for nonvolatile memories. Different roughness degrees for the top and bottom interfaces of this dielectric are detected by the atomic-force- microscopy (AFM) and high resolution transmission electron microscopy (HRTEM). Due to the microtips formed at the bottom interface of the dielectric, significant improvements in the high conduction efficiency, low trapping rate, good uniformity, and high reliability under positive gate-bias are obtained for the dielectric. Therefore, rugged polyoxide is promising for future 5-V-only floating-gate applications.
ELIABLE thin dielectric films are urgently required for
R
scaled 5-V-only floating-gate memories, such as ad- vanced EPROM's, EEPROM's, and flash EEPROM's. Many researchers have claimed meeting the requirements for EEP- ROM manufacturing by using NzO oxides or silicon rich oxides [l], [2], but many obstacles are necessary to be solved.Wu et al. [3] have also reported that the dielectnc formed
by oxidizing thin polysilicon will increase the tunneling ef- ficiency. However, the time-dependent dielectric breakdown (TDDB) characteristic of this dielectric needs to be improved. Recently, the nature of rugged polysilicon has been extensively studied [4]. In this letter, a novel tunneling dielectrics grown on rugged polysilicon, which possesses a high electron con- duction efficiency, a low electron trapping rate, stable interface states, and excellent reliability, is proposed for future 5-V-only nonvolatile memories.
(100) oriented, 2.5-3.5 R-cm, both p-type and n-type Si wafers were used. After RCA cleaning, a very thin rugged polysilicon film was then deposited using SiH4 at 59OOC for 40 sec in LPCVD system. The structural change to the rngged shape has been confirmed to occur around 590°C by the AFM images of these Si films deposited at various temper- atures. The deposition and deposition pressure of the rugged polysilicon were controlled at about 60 &min and 100 mTorr, respectively. The deposition rate was roughly estimated by that the thickness of a quite-thick poly-Si film divided by
Manuscript received December 19, 1994, revised February 23, 1995 This research was mpported in part by the Republic of China National Science Council under contract NSC-83-0404-E009-050
H. P Su, H. W. Liu, P W Wong, K. L Cheng, I M Jen, and H C Cheng are with the Department of Electronics Engineering and Institute of
Electronics, National Chiao Tung University, Hsinchu, Taiwan, ROC G Hong IS with United Microelectronics Corporation, Hsinchu, Taiwan, ROC.
IEEE Log Number 9411762
0741-3 106/95$04
(A)As-deposiled Ngged polpsi
CI v a 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 Distance
(A)
Fig 1 croscopy (AFM)Height profiles of various interfaces obtained by atomic force mi-
the deposition time. Subsequently, the wafers were oxidized at 900"C, which is below the viscous flow temperature of 950'C to quench the morphology of the as-deposited poly-Si, in pure 0 2 ambient. Some bare silicon wafers were oxidized
simultaneously and the resultant oxide thickness is 75 8, (TEM observation). After a 2500 A-thick LPCVD poly-Si was deposited and subsequently POCLj-diffused at 850°C for 30 min, the MOS capacitors were patterned to extract electrical characteristics. To avoid the charge depletion effect, positive (+Vg) and negative (-Vg) gate-bias measurements were conducted on n-type and p-type substrates, respectively. Fig. 1 shows the height profiles of various interfaces ob- tained by AFM. The surface of the ultra-thin rugged poly- Si before oxidation exhibits a hemispherical-grain (HSG)-
like surface from the 3-dimensional AFM photographs (not shown) and the curve A of Fig. 1. After oxidation, the rugged polyoxide is obtained because of the coarse surface of the silicon wafer. Obviously, the bottom interface of the rugged polyoxide is much rougher than the top interface, as shown in curve B and C of Fig. 1. This phenomenon is reconfirmed by the HRTEM photograph, as shown in Fig. 2. For the top
interface of the rugged polyoxide, the topography changes mildly. However, for the bottom interface, the intermittent microtips are observed though the gross topography changes corresponding to the top interface. From Fig. 2, the oxide
thickness above the asperity is about 65
A.
SU el al.: NOVEL TUNNELING DIELECTRIC PREPARED BY OXIDATION 25 I
3 . 0 ,
0 . 4
Fig. 2. High resolution TEM photograph of the rugged polyoxide.
-Substrate InJecllon - - - G a t e InJectlon wn I " 0 2 4 6 8 1 0 Gate Voltage Vg (V) Fig. 3.
at positive and negative gate-bias for n- and p-type wafers, respectively. I-V characteristics of the rugged polyoxide and pure oxide measured
Fig. 3 shows the I-V curves of the rugged polyoxides and pure oxides. It is observed that the rugged polyoxides exhibit a
much higher electron conduction efficiency than the pure oxide in both injection polarities. This high electron conduction will cause a significantly reduced voltage during writing/erasing cycles and make the 5-V-only application available. It is interesting that the electron injection from the bottom interface is much more efficient than that from the top interface. The reason is that the roughness of the bottom interface is much larger than that of the top interface, as shown in Figs. 1 and
2. This asymmetry of the leakage current is beneficial for the device operation. The spread in the voltage at a given current is f 0 . 1 V for the rugged polyoxides and f0.06 V for the pure oxides, across a 3-inch wafer.
Fig. 4 shows the curves of the gate voltage shift versus the stressing time for the rugged polyoxides under a constant current stressing of + I mA/cm2. The pure oxide exhibits a
positive and then negative charge trapping rate, but the rugged polyoxide demonstrates only a small electron trapping rate. It implies that the rugged polyoxide has a better immunity to the
c. 0 . 0
3
0 . 2 -f
d
o r -5 . 2 . 0 1 0 1 0 1a,
Cbsrne-to-Breakdown lCoiUem 1b
-
0.1-
8 Rugged Polyoxlje,.
...-
_...
.
...O."" Pure Oxide&'"
..'
I I I I
0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0
Stressing Time (sec)
Fig. 4. The curves of the gate voltage shift versus stressing time of the rugged polyoxides under a constant current stressing of +1 mAlcm2. The insert is the Weihull plots of the TDDB data at the constant stressing of +lo0 mA/cm2 for the rugged polyoxides and pure oxides. The area of the capacitors is 3.14 x cm2. 1 . o 0 . 8
$
0 . 6 0 . 4 0 . 2I
-
Before Stresslng...
Y sec CO?: -U Rugged Polyoxide - 3 . 2 . I 0 1 2 v g (V) Fig. 5 .oxide before and after a constant current of 10 mA/cm2 stressing for 100 s. The quasi-static CV characteristics of the rugged polyoxide and pure
of Fig. 4 is the Weibull plots of the TDDB data at the constant stressing of +IO0 mA/cm2 for the rugged polyoxides and pure oxides. Evidently, the rugged polyoxides exhibit about
an order of magnitude higher reliability than the pure oxides under +Vg stressing. As shown in Fig. 2, because the field enhancement of the microtips, most electrons flow via the microtips, where the oxide thickness is thinner, to the anode during the stressing. Furthermore, it has been reported [5] that the trapping rate is reduced as well as the TDDB characteristics is improved when the oxide thickness decreases. Therefore, injection on the small effective area with small oxide thickness that will cause a lower bulk field are the main factor to improve the charge trapping properties. Fig. 5 shows the quasi-static CV (QSCV) characteristics of the rugged polyoxides and pure oxides before and after a constant stressing of +10 mA/cm2 for 100s. The initial midgap interface state densities (Ditm) is 3.9
x eV-l cm- for the rugged polyoxide and analogous
to that of the N?O-oxynitride. For the rugged polyoxides, no
252 IEEE ELECTRON DEVICE LETTERS, VOL. 16, NO, 6, JUNE 1995
significant degradation is observed in the QSCV curves after the stressing. In contrast, for -Vg stressing, because the field enhancement through the local very-thin oxide doesn’t exist, the behavior of charge trapping and reliability is similar to that of the polyoxide [ 6 ] , [7]. The details should be further studied.
Because the microtips at the bottom interface are formed after the oxidation of the thin rugged polysilicon, the dielectric proposed in this letter possesses a IOW electron trapping rate, high conduction efficiency, and excellent reliability.
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