Mechanism of Schottky barrier height modulation by thin dielectric insertion on n-type
germanium
Bing-Yue Tsui and Ming-Hong Kao
Citation: Applied Physics Letters 103, 032104 (2013); doi: 10.1063/1.4813834 View online: http://dx.doi.org/10.1063/1.4813834
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/103/3?ver=pdfcov Published by the AIP Publishing
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Mechanism of Schottky barrier height modulation by thin dielectric insertion
on n-type germanium
Bing-Yue Tsuia)and Ming-Hong Kao
Department of Electronics Engineering, National Chiao Tung University, ED641, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan
(Received 15 May 2013; accepted 28 June 2013; published online 16 July 2013)
Although high channel electron mobility has been reported after some passivation techniques, the performance of n-channel Ge metal-oxide-semiconductor field-effect transistor is still limited by the high Schottky barrier height at the metal/n-Ge contact interface, which comes from the Fermi level pinning effect. Recent experiments demonstrated that the Schottky barrier height can be reduced by inserting a thin dielectric layer between metal and Ge. However, the mechanism has not been well clarified. In this paper, the metal induced gap state model, the dipole layer model, and the fixed charge model are verified by varying contact metals, dielectric thicknesses, as well as the annealing temperatures. The pinning factor is improved slightly by dielectric insertion but its value is independent of the dielectric thickness and is still much lower than the ideal value of the non-pinning case. This pinning effect is consistent with the Fermi level pinning at the metal/TiO2interface. After thermal process, no interfacial layer forms at the TiO2/Ge interface and the TiO2 crystallizes gradually after annealing but the Schottky barrier height increases. Since the amount of fixed charges in the thin dielectric layer estimated from a metal-insulator-semiconductor structure is about 2 1011cm2and is insufficient to produce the observed 0.5 eV Schottky barrier height reduction, it is thus recommended that the main mechanism comes from the change of interface dipoles and the annealing effect is attributed to the short-range ordering of the TiO2 layer. Furthermore, dielectric with low conduction band offset which has good thermal stability should be explored.
VC 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4813834]
Improving the performance of Si-based metal-oxide-semiconductor field-effect transistor (MOSFET) devices by scaling down has encountered many limitations. Because Ge has higher electron (3900 vs 1400 cm2/Vs) and hole (1900 vs 500 cm2/Vs) bulk mobility than Si, it becomes one of the potential candidates to replace Si as the channel material in the future.1 Although high channel electron mobility has been measured after some passivation techniques, the driving current of n-channel Ge MOSFET is still poor than that of Si MOSFET due to the high contact resistance between metal and nþGe source/drain region.2–5To reduce contact resist-ance, high doping concentration and low Schottky barrier height are the most critical factors. Unfortunately, the low solid-state solubility of n-type dopants in Ge causes incom-plete activation.6–8 Furthermore, the specific contact resist-ance at the metal/nþ Ge contact is high due to the high Schottky barrier height at the metal/n-Ge interface, which comes from the Fermi level pinning (FLP) effect.9,10
Recent experiments demonstrated that the Schottky bar-rier height can be reduced by inserting a thin dielectric layer between metal and Ge as a tunneling barrier. Several dielec-trics have been employed. They are Si3N4,
12–15 Ge3N4, 16 MgO,17–19 Al2O3, 15,19–25 GeOx, 23 and TiO2. 23–25 Schottky barrier height as low as 65 meV has been reported on the Al/ TiO2/Ge structure.
24
Three possible mechanisms have been proposed. Originally, it was proposed that the inserted dielectric layer can block the electron wave function from metal to semiconductor and therefore decrease the number
of metal induced gap states (MIGS).11,14,17,18,23 Latter researches suggest that the dipole formed at the metal/semi-conductor interface would cause potential drop to modulate the Schottky barrier height.13,15,21,22,26–29Huet al. proposed that the fixed charges in the non-ideal dielectric layers would also cause an extra potential drop across the dielectric layer.29 In this work, sequential experiments were designed to clarify which mechanism dominates the Schottky barrier height modulation on Ge. The thickness effect and the post deposition annealing effect on the Schottky barrier height are also investigated.
N-type Sb doped (100)-oriented Ge wafer with resistiv-ity of 0.01 X-cm was used. Samples were dipped in diluted HF solution (H2O:HF¼ 20:1) and DI-water for 1 min circu-larly by three times to clean the surfaces. Then samples were loaded to an atomic layer deposition (ALD) system to de-posit thin TiO2layer immediately. The TiO2layer was de-posited using Tetrakis(dimethylamino) titanium (TDMAT) and H2O as precursors at 250C. The thicknesses of 1 nm and 7 nm are grown by 22 and 154 cycles, respectively. Some samples were then in-situ deposited by a 5-nm-thick TiN layer in the same ALD system using TDMAT as precur-sor and N2 plasma. After ALD deposition, samples were annealed in vacuum furnace at 300C, 400C, and 600C for 30 min. Then a 300-nm-thick Al was deposited on these samples by a thermal coater and was patterned by a typical lithography process and reactive ion etching process. The samples without TiN contact metal were deposited with dif-ferent metals, including Pt by a sputtering system, and Ni and Co by an e-gun system. The contact metal was patterned by lift-off process. The other processes were identical to a)Author to whom correspondence should be addressed. Electronic mail:
those of the samples using TiN as contact metal. Finally, af-ter removing the native oxide on the sample backside by buf-fered oxide etchant (BOE), backside contact was completed with a 300-nm-thick Al deposition by a thermal coater. The electrode area is 4.9 104cm2for all metals.
The work functions of Pt, Ni, Co, and TiN are 5.65 eV, 5.15 eV, 5 eV, and 4.5 eV, respectively.30,31Metal with fur-ther lower work function was not used in this experiment because the Schottky barrier height on the 7-nm-thick TiO2 contact would be very low (about 0.04 eV for TiN) so that we cannot extract the Schottky barrier height accurately. Figs.1(a)and1(b)show the I-V characteristics of the 1-nm-thick and 7-nm-1-nm-thick TiO2 contacts, respectively. With higher work function metal, the current densities are lower, which indicates that Schottky barrier height increases with the work function.
Fig. 2shows the extracted Schottky barrier height of the 1-nm-thick and 7-nm-thick TiO2contacts with different con-tact metals. The Schottky barrier height of the pure metal/Ge contact is also shown in the figure. These Schottky barrier height values were extracted by the thermionic emission model at reverse bias at temperatures from 25C to 100C.20 The inset shows an example of the TiN/TiO2(7 nm)/Ge con-tacts. The slopes of the linear regression lines give the pinning
factors S. The pinning factor is about 0.052 for the pure Ge junction which is consistent with that reported in litera-tures.9,10For the contacts with TiO2insertion layer, the pin-ning factor is 0.144 for the contacts with 1-nm-thick TiO2and 0.126 for the contact with 7-nm-thick TiO2. These values are larger than that of the pure Ge junction which means that the FLP effect is mitigated by the TiO2 insertion layer. The improvement of pinning factor compared with pure Ge may come from the alleviating of MIGS effect. However, it should be noticed that the pinning factors of the contacts with both TiO2thicknesses are about the same, which indicates that the depinning effect of the 7-nm-thick TiO2is not better than that of the 1-nm-thick TiO2. In the case of complete depinning, the pinning factor should approach to 1; the small pinning factors indicate that the FLP effect is not solved completely by the TiO2insertion layer. According to the MIGS model, the pin-ning factor S can be estimated asS¼ 1
1þ0:1ðe11Þ2, where e1is the electronic component of dielectric constant.32 Applying this model at the metal/TiO2interface, the pinning factor S is estimated to be 0.153 as e1(TiO2)¼ 8.427.
33
Since the calcu-lated pinning factor is close to the experimental pinning fac-tor, it is possible that the FLP with TiO2insertion is due to the FLP at the metal/TiO2interface.
Since the lower Schottky barrier height of the 7-nm-thick TiO2 contact than the 1-nm-thick contact cannot be explained by the more effective suppression of the MIGS effect by the thicker dielectric, but because the pinning posi-tion is changed more for thicker TiO2layer. The change of pinning position may result from two factors, fixed oxide charges or dipoles formed at metal/TiO2 interface and/or TiO2/Ge interface; both can introduce an additional potential drop in the current conduction path and results in the reduc-tion of the Schottky barrier height.29
Either dipoles or fixed charges may be changed after thermal process, which in turn changes the effective Schottky barrier height. Fig. 3 shows the Schottky barrier heights of the contacts with 1-nm-thick and 7-nm-thick TiO2 insertion layer before and after annealing in vacuum at 300C, 400C, and 600C for 30 min. As the annealing temperature increases, the Schottky barrier height increases,
FIG. 1. Current-voltage characteristics of the Schottky contacts with differ-ent contact metals. The contact structure is (a) metal/TiO2(1 nm)/Ge and (b)
metal/TiO2(7 nm)/Ge.
FIG. 2. Extracted effective Schottky barrier height of the contacts without TiO2insertion layer, with 1-nm-thick TiO2insertion layer, and with
7-nm-thick TiO2insertion layer. The inset shows the extraction of the Schottky
barrier height of the TiN/TiO2(7 nm)/Ge contacts as an example.
too. It is noticed that the increments of the Schottky barrier height of the 1-nm-thick and the 7-nm-thick TiO2contacts are similar, and the Schottky barrier heights of the 7-nm-thick TiO2 contact are still lower than those of the 1-nm-thick TiO2 contact after annealing. To observe if there is a new interfacial layer formed after annealing, the cross-sectional structure of the 600C annealed TiN/TiO2/Ge con-tact was inspected by the high-resolution transmission-elec-tron-microscope (TEM) and the micrograph is inserted in Fig.3. It is clearly that there is no interfacial layer formed at the TiO2/Ge interface and the TiN/TiO2interface. This result suggests that the Schottky barrier height increment is not due to new layer formation after annealing. If the Schottky bar-rier height modulation mechanism of the TiO2-inserted con-tacts mainly results from the fixed charges in TiO2and these charges are reduced by the annealing process, the Schottky barrier height of the 7-nm-thick TiO2contact should be close to that of the 1-nm-thick TiO2contact. However, this predic-tion conflicts with the experimental results. It could be esti-mated that if the Schottky barrier height modulation comes from the fixed charges, the charge density should be as high as 3 1013cm2to produce a 0.5 eV Schottky barrier height reduction assuming the relative dielectric constant of TiO2is 80.34Lee has studied the C-V characteristics of the TiO2/Ge and TiO2/SiO2/Ge structures.
35
Although the TiO2/Ge sam-ple showed distorted C-V curve due to its high leakage cur-rent, the difference in total charge between the two samples is only 2 1011 cm2, which is much lower than that required to produce a 0.5 eV Schottky barrier height reduc-tion. Therefore, it is recommended that the Schottky barrier height modulation of the TiO2-inserted contact is mainly caused by the interface dipoles.
Fig. 4shows the XRD spectra of the 7-nm-thick TiO2-inserted junction after annealing at 300C, 400C, and 600C for 30 min, respectively. The TiO2 and TiN layers remain in amorphous state after 400C annealing. The (110)-oriented rutile phase of TiO2is detected on the 600C annealed sample. However, Raman analysis suggested short-range ordering in the amorphous TiO2 phase at annealing temperatures of 200 – 400C.36 Thus, it is postulated that with the increase in annealing temperature, the TiO2layer is gradual crystallized and the interface dipoles change
simultaneously. The change of dipoles affects the stability of the Schottky barrier height modulation.
In summary, we examined the three possible mechanisms, MIGS model, dipole model, and fixed charge model, of the dielectric insertion induced Schottky barrier height modulation of the metal/TiO2/n-type Ge contact. The main cause is not the release of FLP effect but the shift of pinning position. Interface dipole plays more significant role than the fixed charge. Thermal annealing in vacuum at temperature as low as 300C changes the interface dipole due to the short-range ordering of the TiO2layer so that the Schottky barrier height changes. The Schottky barrier height of the Al/TiO2(7 nm)/Ge contact increases from 0.03 to 0.11 eV after 400C annealing. Beyond 400C, the Schottky barrier height would be too high to maintain good contact property.
The authors would like to thank the Nano Facility Center of National Chiao-Tung University for providing the experimental facilities. This work was supported in part by the Ministry of Education in Taiwan under ATU Program, and was supported in part by the National Science Council, Taiwan, R.O.C. under the contract No. NSC 100-2221-E-009-010-MY2.
1
H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Ieong,IBM J. Res. Dev.50, 377 (2006).
2D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H. S. P.
Wong, and K. C. Saraswat, Tech. Dig. - Int. Electron Devices Meet. 453 (2009).
3L. Hutin, C. L. Royer, J.-F. Damlencourt, J. M. Hartmann, H. Grampeix,
V. Mazzocchi, C. Tabone, B. Previtali, A. Pouydebasque, M. Vinet, and O. Faynot,IEEE Electron Dev. Lett.31, 234 (2010).
4
R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, IEEE Transactions on Electron Devices59, 335 (2012).
5R. Zhang, P. C. Huang, J. C. Lin, N. Taoka, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices60, 927 (2013).
6
C. T. Chung, C. W. Chen, J. C. Lin, C. C. Wu, C. H. Chien, and G. L. Luo, Tech. Dig. - Int. Electron Devices Meet. 383 (2012).
7D. P. Brunco, B. De Jaeger, G. Eneman, J. Mitard, and G. Hellings, J. Electrochem. Soc.155, H552 (2008).
8
C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat,Appl. Phys. Lett.87, 091909 (2005).
9S. Brotzmann and H. Bracht,J. Appl. Phys.
103, 033508 (2008).
10
A. Dimoulas, P. Tsipas, A. Sotiropoulos, and E. K. Evangelou, Appl. Phys. Lett.89, 252110 (2006).
11T. Nishimura, K. Kita, and A. Toriumi,Appl. Phys. Lett.91, 123123 (2007). 12M. Kobayashi, A. Kinoshita, K. C. Saraswat, H.-S. P. Wong, and Y. Nishi,
J. Appl. Phys.105, 023702 (2009).
FIG. 4. X-ray diffraction spectra of the contacts with 7-nm-thick TiO2
inser-tion layer after annealing at 300, 400, and 600C. FIG. 3. Extracted effective Schottky barrier height of the contacts after
ther-mal annealing. The inset is the cross-sectional TEM micrograph of the con-tact with 7-nm-thick TiO2insertion layer after 600C annealing.
13J. F. Wager and J. Robertson,J. Appl. Phys.
109, 094501 (2011).
14
M. Kobayashi, A. Kinoshita, K. C. Saraswat, H. S. Wong, and Y. Nishi, IEEE Symp. VLSI Technol. 54 (2008).
15L. Lin, J. Robertson, and S. J. Clark, Microelectron. Eng. 88, 1461
(2011).
16
R. R. Lieten, S. Degroote, M. Kuijk, and G. Borghs,Appl. Phys. Lett.92, 022106 (2008).
17D. Lee, S. Raghunathan, R. J. Wilson, D. E. Nikonov, K. C. Saraswat, and
S. X. Wang,Appl. Phys. Lett.96, 052514 (2010).
18
Y. Zhou, W. Han, Y. Wang, F. Xiu, J. Zou, R. K. Kawakami, and K. L. Wang,Appl. Phys. Lett.96, 102103 (2010).
19Y. Zhou, M. Ogawa, M. Bao, W. Han, R. K. Kawakami, and K. L. Wang, Appl. Phys. Lett.94, 242104 (2009).
20
Y. Zhou, M. Ogawa, X. Han, and K. L. Wang, Appl. Phys. Lett. 93, 202105 (2008).
21A. M. Roy, J. Y. J. Lin, and K. C. Saraswat,IEEE Electron Device Lett.
31, 1077 (2010).
22
B. E. Coss, C. Smith, W.-Y. Loh, P. Majhi, R. M. Wallace, J. Kim, and R. Jammy,IEEE Electron Device Lett.32, 862 (2011).
23T. Nishimura, K. Kita, and A. Toriumi,Appl. Phys. Express1, 051406
(2008).
24
B. E. Coss, C. Smith, W.-Y. Loh, P. Majhi, R. M. Wallace, J. Kim, and R. Jammy,IEEE Electron Device Lett.32, 862 (2011).
25J.-Y. Jason Lin, A. M. Roy, A. Nainani, Y. Sun, and K. C. Saraswat,Appl. Phys. Lett.98, 092113 (2011).
26
B. E. Coss, P. Sivasubramani, B. Brennan, P. Majhi, R. M. Wallace, and J. Kima,J. Vac. Sci. Technol. B31, 021202 (2013).
27J. Hu, K. C. Saraswat, and H.-S. P. Wong,J. Appl. Phys.
107, 063712 (2010).
28
B. E. Coss, W.-Y. Loh, R. M. Wallace, J. Kim, P. Majhi, and R. Jammy,
Appl. Phys. Lett.95, 222105 (2009).
29
J. Hu, A. Nainani, Y. Sun, K. C. Saraswat, and H.-S. Philip Wong,Appl. Phys. Lett.99, 252104 (2011).
30
H. B. Michaelson,J. Appl. Phys.48, 4729 (1977).
31A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, K. Matsuo, T. Shibata, Y.
Tsunashima, K. Suguro, and T. Arikado,IEEE Trans. Electron Devices
48, 1604 (2001).
32
Y. C. Yeo, T. J. King, and C. Hu,J. Appl. Phys.92, 7266 (2002).
33J. G. Traylor, H. G. Smith, R. M. Nicklow, and M. K. Wilkinson,Phys. Rev. B3, 3457 (1971).
34
S. K. Kim, W.-D. Kim, K.-M. Kim, C. S. Hwanga, and J. Jeong,Appl. Phys. Lett.85, 4112 (2004).
35S. Y. Lee, W. Lee, H.-S. Jung, H. K. Kim, and C. S. Hwang, in ALD 2011
(poster), Cambridge, 26–29 June 2011.
36
A. F. Khan, M. Mehmood, M. Aslam, and S. I. Shah,J. Colloid Interface Sci.343, 271 (2010).
