Caleb Yu-Sheng Cho, Member, IEEE, Ming-Jer Chen, Senior Member, IEEE, Chiou-Feng Chen, Prateep Tuntasood,
Der-Tsyr Fan, and Tseng-Yi Liu
Abstract—A self-aligned sidewall split-gate Flash memory cell
is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of12 7 2( is the feature size), formed in a 32-MbNOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to105confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experi-ment at 250 C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are exam-ined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on theNANDarchitecture application.
Index Terms—Flash memory, MOSFETs, NAND, NOR, over-erase, poly over-erase, sidewall, source-side injection, split-gate.
I. INTRODUCTION
S
PLIT-GATE Flash memories with a sidewall poly 3 gate [1], [2] have recently received significant attention due to promising advantages of low power consumption, high injec-tion efficiency, less susceptibility to short-channel effects (drain turn-on and punch-through), and overerase immunity. Here, the overerase immunity is due to the built-in select-gate transistor, which can effectively get rid of the on-chip erase procedures traditionally used to resolve the overerase problems in stacked gate cell. On the other hand, the unit cell area is considered to be competitive ( [2]; is the feature size) relative to that of stacked gate cell (typical ).In this paper, the sidewall corner of the floating-gate (FG) in a sidewall split-gate Flash memory cell is deliberately rounded [3], as experimentally carried out in a 32-MbNORFlash memory with a unit cell size of . The rounded shape can effec-tively release the field lines at the FG corner during poly-to-poly
Manuscript received April 19, 2005; revised December 2, 2005. This work was supported by the National Science Council, Taiwan, R.O.C., under Con-tract NSC 90-2218-E-009-043. The review of this paper was arranged by Editor R. Shrivastava.
C. Y.-S. Cho, D.-T. Fan, and T.-Y. Liu are with Actrans System Inc., Hsinchu 300, Taiwan, R.O.C.
M.-J. Chen is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: chenmj@ faculty.nctu.edu.tw).
C.-F. Chen and P. Tuntasood are with Actrans System Inc., Santa Clara, CA 95054 USA.
Digital Object Identifier 10.1109/TED.2005.863764
Fig. 1. Schematic cross-sectional view of the novel cell along cell channel direction.
erase and as a result, the damage to interpoly oxide is mini-mized. Such improvement leads to excellent endurance charac-teristics, as verified in comparison with the conventional source-side erase scheme. At the same time, the acceptable erase speed is achieved. The retention bake test is addressed before and after P/E cycling. Disturb effects are examined in detail and the op-erating conditions for disturbs inhibition are determined. Also elaborated are the differences relative to existing source-side in-jection and/or split-gate structures, as well as the potential ap-plication in theNANDarchitecture.
II. EXPERIMENTAL
A self-aligned sidewall split-gate 32-MbNORFlash memory is fabricated in 0.15- m technologies with shallow trench isolation. Some key processes are described as follows. Like the conventional procedures in stacked-gate device, the floating gate (poly 1 layer) in this paper is self-aligned and then etched by using the control gate (CG; poly 2 layer) as a hard mask. The CG and subsequent deposited dielectric film together serve as another mask to facilitate the formation of a self-aligned select gate (SG) while undergoing anisotropic dry etching on poly 3 layer. To enhance the potential coupling toward the FG during the programming, the remaining poly 3 over the source area is metal-connected to the underlying source diffusion. Actually, this kind of contact connection is implemented over several cells along wordline (W/L) for suppression of the area overhead. Fig. 1 schematically shows the cross section of this novel cell along the cell channel direction. Here, the “split point” divides the cell into a stacked-gate cell and a select-gate transistor; and the W/L and bitline (B/L) are defined by the select gate (SG) and drain (D), respectively. The overerase immunity is realized with the built-in select-gate transistor. The floating-gate sidewall corner next to the interpoly oxide is deliberately rounded. Fig. 2 shows the corresponding transmis-sion electron microscopy (TEM) image along the cell channel direction. Some of the important cell dimensional parameters
are listed in Table I. The additional select gate for the purpose of overerase immunity increases the unit cell size to , but still being competitive to that (e.g., ) of stacked gate cell.
The array size is divided into page and block with 32 K cells and 16 pages, respectively. In the selected page, CG and source are in common potential throughout the whole page; and cells can be either selected or deselected by both W/L and B/L. Fig. 3(a) depicts the page configuration of the array architecture, which is arranged in the row organization with common B/Ls shared by all pages. According to the coded address, individual page is selected through both control-gate decoder and source switch; and memory cells in the selected page are selected by activating the W/L and B/L decoders. On the other hand, deselected pages are all biased at grounded , and , which can greatly alleviate those disturbs from cycled program/erase operations [4]. In addition, since the drain voltage used in this work is small, the traditional overhead penalty due to extra local B/L decoders is eliminated.
III. CELLOPERATIONS
Programming is performed by means of source-side channel-hot-electron injection: applying typical 10 V to the CG, 3.3 V to the source (S), 0 V to the drain (D), and 1.5 V to the select gate (SG). Under these conditions, the floating-gate voltage ( ) is capacitively coupled to a high level enough to strongly turn on a conductive channel beneath, which in turn gives rise to an inver-sion layer electrically connecting the source voltage ( ) to the proximity of the split point as depicted in Fig. 1. As mentioned in the Experimental section, on the other hand, the poly 3 over the source area is metal-connected to the source diffusion and thereby the potential coupling is enhanced toward FG during programming. Operating voltages for selected page are given in Fig. 3(b) that displays eight 4-Kb W/Ls (poly 3) and eight CG lines (poly 2). The cell C2 is selected for programming. For other cells C1 and C3 in selected W/L ( V), program is inhibited by applying 1 V on corresponding B/Ls, and cells in the deselected W/Ls, e.g., C4, C5, and C6, are all inhibited by V. Note that in the deselected pages, , and are all grounded under programming. This type of special configuration greatly alleviates propagation of program disturb among pages, indicating that each page can be electrically iso-lated from other pages.
Fig. 3. (a) NOR Flash memory array architecture used in the study. The array is arranged in the row organization with B/Ls commonly shared by all pages. Page is selected or deselected by CG and source switch. Note that not all pages are depicted here. (b) Operating voltages in selected page during programming in NOR architecture. C2 is the selected cell. A single page is made up of 8 W/Ls, 4096 B/Ls, and common CG and source in this page.
Poly-to-poly Fowler–Nordheim (FN) electron tunneling (i.e., 11 V on SG and 0 V on CG) from the floating gate toward the neighboring select gate (W/L) is employed for erasing. The erasing size is quite flexible, ranging from a smallest size of 4 Kbits (one W/L) to the whole chip size (32 Mbits). Memory cells of selected block (512 Kbits, 16 pages) can be over-erased to negative threshold voltage ( ) in 20 ms, without use of extra on-chip erase verify procedures due to built-in overerase immunity. The deselected pages are biased in grounded ,
, and , and open to ensure erase inhibition.
For an over-erased cell in deselected W/L ( V), the undesirable leakage current is eliminated as experimentally evi-denced in Fig. 4. Finally, the cell is read out by applying 4 V on SG, 1.5 V on drain, and 0 V on CG. The typical read-out current
Fig. 4. Read-out characteristics of an over-erased memory cell (V = 03:75 V) for selected and deselected cases. The deselected case (V = 0) yields good overerase immunity under read-out operation.
TABLE II
TYPICALOPERATINGVOLTAGES ANDPULSEDURATIONS INSELECTEDPAGE. THE“SEL” AND“DESEL”DENOTESELECTED ANDDESELECTED,
RESPECTIVELY. NOTETHATCGANDSOURCEARECOMMON INONEPAGEBUTNOTCOMMON FOR THEWHOLEARRAY
is A for over-erased cells. The pulse voltages and du-rations used here for selected (denoted as “Sel”) and deselected cells (denoted as “DeSel”) are listed in Table II.
IV. CHARACTERISTICS OF THENOVELCELL
Fig. 5 shows the gate and source current measured versus select-gate voltage in a dummy transistor, which is the memory cell with shorted CG and FG. The maximum gate cur-rent reaches at V for source voltage V. Considering the process variations cell by cell while actually accounting for the dependence of on gate current (that is, a smaller gate current variation to the right of the peak
V in Fig. 5), the of 1.5 V was exploited in this paper. The corresponding source current is merely 10 A, which is highly favorable for programming of several words.
Fig. 6 shows the measured programming characteristics with CG voltage as a parameter. It can be seen that for the specific V, initially the threshold voltage rapidly increases until entering certain transition region and subsequently the crease rate of threshold voltage is lowered. The physical in-terpretation is that in the beginning of programming time, FG is highly positively coupled from the source via the extended channel underneath FG; consequently, FG channel is operated in linear region. As more electrons are injected onto FG, becomes more negative and the depletion region is gradually formed near source side; that is, FG channel enters into satura-tion region of operasatura-tion [5]. Obviously, to maintain FG channel in linear region during the programming period, the target pro-grammed is appropriately set at 2 V for V. The
Fig. 5. Gate (I ) and source (I ) current measured versus select-gate voltage in a dummy transistor. For programming,V = 1:5 V is chosen by accounting for the process variations cell by cell as well as theV -dependence of I on V .
Fig. 6. Programming characteristics of the novel cell in the 0.15-m technologies. To meet the target value,V = 10 V, V = 3:3 V, and V = 0 V with 10-s duration are chosen throughout this paper.
corresponding programming time is 10 s, which appears to fall within the threshold voltage rapidly increasing region.
Fig. 7 shows the measured erase characteristics for various select-gate voltages. Although the rounded FG sidewall consid-erably lowers the field strength at FG corner during poly-to-poly erase, the erase characteristics of the cell in Fig. 7 reveal that an erase time of 10 ms for the target value of V is quite accept-able. To further cover cell erase behaviors in block or even the whole chip, a longer time should be expected to avoid possible erase failure. Erase speed of 20 ms for a block size (512 Kb, 16 pages) in this paper is still competitive.
V. RELIABILITYISSUES
Reliability issues such as endurance characteristics, retention bake, and disturb effects are addressed in this section. The en-durance characteristics focus on the threshold voltage shift with increasing program/erase (P/E) cycles. Retention bake experi-ment is to record the FG-charge variation occurring in the ab-sence of external voltages. The disturb effects encountered in
Fig. 7. Erase characteristics of the novel cell in the 0.15-m technologies. To meet target value, V = 11 V with 10 ms duration are chosen in poly-to-poly erase operation.
Fig. 8. Endurance characteristics measured on the novel cell. The logic discrimination between two states can be seen.
the program and read-out operations are examined extensively, from which the suitable voltages are determined.
A. Endurance Characteristics
Fig. 8 shows the measured endurance characteristics in terms of high threshold level and low threshold level until P/E cycles of . It can be seen that (i) the downward shift is 0.35 V for the high threshold state; and (ii) the upward shift in the low threshold state is strikingly small, i.e., 0.7 V. Such small threshold closure in low state manifests the potential of the rounded FG sidewall. The threshold shifts in Fig. 8 can be explained by the mechanism of trapped electrons in cell gate oxide near hot-electron injection point (i.e., the split point in Fig. 1) during programming and in interpoly oxide during poly-to-poly erasing [6]. It is also noteworthy that owing to the weak dependence of channel current on for source-side injection device [5], the low closure does not affect the logic discrimination of sense amplification too much.
1) Endurance Behavior at : The
en-durance characteristics at a higher of 5 V in source-side in-jection (SSI) show different behavior from that at V,
Fig. 9. Endurance characteristics of highV for two source voltages of 3.3 and 5 V.
Fig. 10. Endurance characteristics of the novel cell in two erase schemes. The source-side injection programming is applied to both cases. The inset shows the bias configuration for source-side erase.
as demonstrated in Fig. 9. This figure is obtained by adjusting the duration of 5-V program pulse in such a way to produce comparable threshold voltages in the initial P/E cycles. Indeed, Fig. 9 reveals anomalous characteristics not reported elsewhere: for P/E cycles starting from about 2 , the high threshold voltage state for V dramatically decreases with in-creasing P/E cycles whereas it relatively remains constant for higher of 5 V. One plausible explanation, which can be found in [6], for the former is that electron trapping in the oxide near the injection point increases with increasing P/E cycle, which in turn lowers the amount of hot electron injection onto the floating gate. The decline rate of hot electron injection exceeds the accu-mulation rate of electron trapping, resulting in a net decrease in threshold voltage with increasing P/E cycles. The similar argu-ment essentially can apply to the data of V in Fig. 9 but in this case the decline rate of hot electron injection is almost equal to the accumulation rate of electron trapping.
2) Source-Side Erase Versus Poly-to-Poly Erase: Fig. 10
shows the measured endurance characteristics from the poly-to-poly erase and source-side erase. The source-side
Fig. 11. Distributions of over-erased and programmed cells in terms ofI andV before and after 3210 P/E cycles in 32-Kb arrays, respectively.
injection programming is used for both cases. As expected, the source-side erase scheme results in a worse closure with increasing P/E cycles than poly-to-poly erase. The origin of such large difference is that the source junction is not particu-larly graded to accommodate source-side erase, as originally cited in [7]. There are two principal reasons for favoring poly-to-poly erase in this work. The first reason is the smaller unit cell size. Because the source implant in poly-to-poly erase is not doped for source-side erase, a smaller unit cell size (and thereby the higher cell densities) is expected. The second reason is that the number of on-chip charge pumps as adopted in source-side erase case is more than that in poly-to-poly erase. Due to negative CG bias used in source-side erase, two positive charge pumps (CG and S) and one negative charge pump (CG) are needed during programming and erasing, respectively. However, only two positive charge pumps are demanded in poly-to-poly erase, making possible realization of smaller die size. Therefore, the poly-to-poly erase method is exploited through this paper.
Fig. 11 displays the distributions of threshold voltage and read-out current respectively from programmed and erased cells in a 32-Kb array (one page) before and after 3 P/E cycles. It is noteworthy that the whole page pro-gramming is accomplished by 10- s propro-gramming byte by byte, but with a 20-ms erasure in the whole page. The longer erase pulse duration is needed due to consideration of process variations. Two interesting statistical properties concerning the read-out current can be drawn. First, after P/E cycles the distri-bution shape of read current remains intact, except a slight shift of about 5 A toward the decreasing read current direction. Second, the smallest read-out current after P/E cycles is around 20 A, which is still large enough for logic discrimination. Also noticed in Fig. 11 is the excellent statistical distribution of post-P/E threshold voltage relative to that of fresh devices. Again, Fig. 11 corroborates the fabricated cells to be statisti-cally highly reliable.
B. Retention Bake
First of all, a 24-h retention bake at 250 C [8], [9] is per-formed on the programmed cells in 4-Mb array and the erased cells in 8-Mb array. The resulting retention characteristics are given in Fig. 12(a). This figure exhibits not only a small shift
Fig. 12. (a) Retention characteristics before and after 250 C, 24-hour bake for over-erased and programmed cells in 4- and 8-Mb arrays in terms ofI andV , respectively; and (b) retention characteristics for ERS and PGM cells in 8- and 32-Kb arrays, respectively, created from 1) fresh case, 2) post-10 P/E cycling cells with no bake, and 3) post-10 P/E cycling cells undergoing 24-hr, 250 C bake.
in both and but also the insignificant change in the distribution after the retention bake. Therefore, it is claimed that the underlying device is free of extrinsic defects or equivalently the oxide thinning in the manufacturing process [10]. The rea-sons are that if the oxide thinning were not absent, then the in-trinsic oxide traps created in the programmed or erased cells would sum up to form a localized critical leakage path in the oxide part having extrinsic defects, which would in turn produce a noticeable change in retention distributions before and after programming or erasing. Furthermore, another 24-h, 250 C bake experiment is carried out on programmed cells in 32-Kb array and erased cells in 8-Kb array both undergoing P/E cycling. The resulting retention bake statistical distributions are plotted in Fig. 12(b). Also given in this figure are those with no bake for comparison. Evidently, it can be drawn that 1) the post-P/E cycling curve with no bake is slightly shifted relative to the fresh array; and 2) again a slight shift appears in post-cy-cling bake curve as compared to that after cypost-cy-cling but without bake. Therefore, it is argued that the retention characteristics are fairly excellent.
Fig. 13. Measured soft-write characteristic for the over-erased cells in the selected SG line during programming under worst-case conditions.t is the time to aV shift of 500 mV. The disturb time for byte programming is 5.12 ms, which validates soft-write disturb inhibition atV = 1 V in this paper.
C. Disturb Effects
As mentioned in the Experimental section, the specific page arrangement can isolate disturbs from the other pages through CG and source switch; that is, an individual page is unlikely to be affected when other pages undergo P/E cycles. However, this is not the case at the cell level within single page, as explained below.
1) Program Inhibition: During programming, soft-write
ef-fect might occur when the B/L voltage fails to prevent the in-hibited cells in selected W/L [e.g., C1 and C3 in Fig. 3(b)] from being programmed. Fig. 13 shows measured soft-write characteristic for over-erased cells under the worst-case con-ditions. The in Fig. 13 is the time to a 500-mV shift. Considering byte programming with a programming time of 10 s in a 4-Kb W/L, the worst case disturb time of 5.12 ms ( s ) is drawn as labeled in Fig. 13. It can be seen that even for the cell erased to V, a drain voltage of 1 V can effectively inhibit the undesired programming. This argument holds for the test samples in the work. At the mass production level, however, to compensate for possible variation in threshold voltage and channel length of SG devices, a larger must be considered.
2) Program Disturbs: For deselected over-erased cells in
the same B/L where there is a selected cell undergoing pro-gramming [e.g., C5 in Fig. 3(b)], the W/L voltage ( ) and B/L voltage ( ) both are biased at 0 V and an insignificant channel current should be expected to prevent unwanted pro-gramming in these cells. However, due to select-gate channel length reduction or threshold voltage shift caused by process variations, the exponentially increased channel subthreshold current may erroneously induce electron injection from the split point onto floating gate (namely, the subthreshold source-side injection, [11]). Meanwhile, there may be another mech-anism occurring, the reverse tunneling of electrons, from SG through interpoly oxide to FG. This is due to the over-erased state and the coupling of source voltage, making FG potential highly positive with respect to SG. On the other hand, one may
Fig. 14. Measured MB disturb characteristics as a function ofV for cells before and after10 P/E cycles. t is the time for aV shift of 500 mV. The disturb time is 70s, which validates MB disturb immunity for the case of V = 3:3 V.
Fig. 15. Measured MB and RT disturb characteristics in terms of threshold voltage variation forV = 3:3 V and 5 V. Use of V = 3:3 V leads to MB and RT disturb immunity.
consider the possible injection of electrons due to avalanche or impact generation at the split point in the presence of an inversion layer formed beneath floating gate. However, as will be explained later, we must rule out the possibility of avalanche or impact generation. Therefore, the so-called “mirror-bit (MB) disturb” as conducted at V may involve subthreshold SSI ( ) and/or reverse tunneling (RT). Fig. 14 depicts the MB disturb data, in terms of the time to a 500-mV threshold voltage shift versus the reciprocal of , measured from the over-erased cells before and after P/E cycles. The physical origin of the data in this figure will be addressed in detail later. For a selected page under programming, each over-erased cells can only tolerate at most seven pulses of MB disturb from the selected cells in the same B/L. Thus, in the byte programming mode, the worst case MB disturb time is calculated to be 70 s ( s), indicating the MB disturb immunity for the involved of 3.3 or even 5 V as can be validated in Fig. 14.
It is interesting to further examine the case of V. To suppress subthreshold SSI, an inhibition voltage V is applied. The results are shown in Fig. 15 along with those from V for comparison. It can be seen that the threshold
Fig. 16. Time derivative of threshold voltage versus reciprocal of floating gate voltage, transformed from RT data ofV = 5 V and the data of V = 3:3 V in Fig. 15. A straight line fitting the RT data ofV = 5 V is extended to enter into theV = 3:3 V regime.
voltage slightly increases with increasing disturb time, regard-less of or V. The physical origin is that the ki-netic energy of hot electrons near the split point is not suffi-ciently large as compared with the SiO /Si barrier height of around 3.2 eV. Therefore, the reverse tunneling seems to prevail in this case. On the other hand, a higher inhibition voltage of 2.7 V for effective suppression of subthreshold SSI is done for V. The measurement results are again plotted in Fig. 15 along with those from V. Obviously, both subthreshold SSI and reverse tunneling exist in the MB disturb measurement ( V) but with the former as the dominant factor. Further insights can be obtained by differentiating the threshold voltage of interest in Fig. 15 with respect to the disturb time [12]. The results are shown in Fig. 16 against floating gate voltage. Here the FG voltage is calculated by using a conversion formula [13]: , where the ’s, and are the coupling ratio of each terminal, the floating-gate charge, and the total capacitance, respectively. It is noteworthy that in the present cell structure, the importance of the fringing capacitive coupling from the source should not be absent, as detailed elsewhere [13]. In other words, in the pres-ence of this fringing component, the source coupling in inver-sion conditions appears to be larger than CG coupling. It can be seen from Fig. 16 that the data of V fall on or close to a straight line that fits the RT data of V. This reasonably determines reverse tunneling dominating in the case.
The aforementioned analysis dedicated to and V can be readily applied to elucidate measured data in Fig. 14 in a wide range of . First of all, the values of in Fig. 14 can essentially produce injected electrons with kinetic energy larger than SiO /Si barrier height of around 3.2 eV. It there-fore is expected that an increase in can produce a large (i.e., exponential) change in the amount of injected electrons via sub-threshold SSI. At the same time, the floating gate voltage is in-creased via both inversion-layer coupling and fringing capac-itive coupling, which in turn produces exponential increase in reverse tunneling. All of these two are consistent with experi-mental data in Fig. 14: a small increase in gives rise to an
ex-Fig. 17. Measured soft-erase characteristics under worst-case conditions during read-out operation before and after10 P/E cycles. t is the time to aV shift of 100 mV.
ponential decrease in time to critical threshold voltage shift. On the other hand, we have found that for the range involved in Fig. 14, the substrate current is limited by the background noise ( ), reasonably removing the possibility of avalanche or impact generation.
Note that to highlight the disturb mechanisms, both Figs. 14 and 15 use the same initial (in the deep over-erased state). Since the reverse tunneling takes place in the cells with in-hibited and zero in selected page [e.g., C4 and C6 in Fig. 3(b)], the worst case time is calculated to be 35.83 ms ( s ) for byte programming. Again returning back to Fig. 15, the cells experiencing disturbs are judged to have good tolerance.
3) Soft Erase: Soft erase may occur after repeated read-out
operation on the programmed cell [6]. Such effect is significant in the case of electron loss through interpoly oxide [14]. Fig. 17 shows the worst case soft-erase characteristics measured on se-lected programmed cell during read-out operation, plotted be-fore and after P/E cycles. It can be seen that the projected of the cycled cell at the ten-year limit is higher than that of fresh cell. This indicates the presence of the trapped electrons in interpoly oxide after P/E cycles. A select-gate voltage of 4 V is therefore determined while meeting high read-out current and soft-erase immunity of more than ten years.
VI. FURTHERDISCUSSION
Since its appearance in 1980s, there have been a large number of articles dedicated to the split-gate Flash device using source-side hot-electron injection [1]–[3], [5], [6], [15]–[19]. Specifi-cally, the latest sidewall split-gateNORFlash as presented in this paper can be traced back to the triple-poly sidewall split-gate Flash memory in 1989 [2]. It is well recognized that due to ex-tremely complicated triple-poly processes at that time, little in-formation was heard afterwards about the mass production of the triple-poly sidewall split-gate Flash memory. Only with the significant progress in the manufacturing technology in the re-cent years can it become possible for realization of the triple-poly sidewall split-gate Flash memory in a CMOS compatible manufacturing line.
two-poly process [21], [22] for the purposes of self-alignment and poly-injector fabrication.
The proposed cell structure can find other potential appli-cations in the NAND architecture. One of the examples is the 512-Mb sidewall split-gateNANDFlash memory in the 0.12- m process [23]. In thisNANDarchitecture, a fast and low-voltage ( V) source-side hot-electron injection is employed for programming in size of pages because of high-injection effi-ciency of split-gate. Moreover, the same cell structure has again proved itself in the realization of the multilevel concept in the
NANDarchitecture [24].
VII. CONCLUSION
A new sidewall split-gate 32-Mb Flash memory with the rounded FG sidewall corner has been fabricated in the NOR
architecture. The endurance test has manifested the potential of the rounded FG sidewall. The program and read disturbs have been examined and the operating conditions for disturbs inhi-bition have readily been determined. We have also elaborated on the differences between the proposed cell structure and the existing ones, as well as on theNANDarchitecture application.
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[23] C.-Y. Hsu, C.-W. Hung, D. Sung, C.-S. Wu, S. C. Chen, H. H. Kuo, J. Y. Pan, C. L. Chen, I. C. Chuang, V. Huang, C. C. Hsue, D.-T. Fan, J.-C. Lu, C. Y.-S. Cho, K. Tseng, A. Hsu, B. Sheen, P. Tuntasood, and C.-F. Chen, “Split-gate NAND Flash memory at 120 nm technology node featuring fast programming and erase,” in Symp. VLSI Tech. Dig., 2004, pp. 78–79. [24] H.-H. Kuo, J.-Y. Pan, C.-L. Chen, I.-C. Chuang, S.-C. Chen, C.-Y. Hsu, D. Sung, C.-W. Hung, V. Huang, C.-C. Cho, C.-C. Hsue, D.-T. Fan, J.-C. Lu, K. Tseng, J. Pabustan, S. Wang, A. Hsu, B. Sheen, P. Tuntasood, and C.-F. Chen, “Multi-level split gate NAND memory with fast program and erase in 120 nm,” in Proc. 2004 NVSMW, pp. 37–39.
Caleb Yu-Sheng Cho (S’04-M’05) received the B.S.
degree in electrical engineering from National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C., the M.S. degree in electronics engineering from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., and the Ph.D. degree in electronics engineering from National Chiao-Tung University, Hsinchu, in 1996, 1999, and 2004, respectively.
In 2004, he joined Actrans System, Inc., Hsinchu. His research interests are Flash memory device physics, coupling ratio extraction, novel Flash memory structure development, and Flash memory circuit design.
University (NCTU), Hsinchu, Taiwan, R.O.C., in 1977 and 1985, respectively.
In 1985, he joined the faculty of the Department of Electronics Engineering, NCTU, where he became Full Professor in 1993. From 1987 to 1992, he served as a Consultant for the Taiwan Semiconductor Man-ufacturing Company (TSMC), Hsinchu, where he led a team from NCTU and Electronics Research and Service Organization (ERSO/ITRI) to build up a se-ries of process windows and design rules. He has been granted six U.S. patents and six Taiwanese patents covering the high-precision analog capacitors, 1-T SRAM cell, dynamic threshold MOS, and ESD protection. From 2000 to 2001, he was a Visiting Professor at the Department of Electrical Engineering and the Center for Integrated Systems, Stanford University, Stanford, CA. His research interests have long been focused on the technology reliability physics and cur-rently on nanoscale electronics. He has graduated 12 Ph.D. students and more than 80 Master’s students.
Dr. Chen is a member of Phi Tau Phi.
Chiou-Feng Chen received the B.S. degree in
elec-trical engineering from National Chen-Kung Univer-sity, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.
He has been working in the nonvolatile memory industry for 15 years. He is now with Actrans System, Inc., Santa Clara, CA.
respectively.
He is currently a Senior Member of the Technical Team, Flash Memory Development Group, Actrans System, Inc., Santa Clara, CA. Before joining Actrans System, Inc., he has been working at several semiconductor companies, including NexFlash Technologies, Inc.
Der-Tsyr Fan received the B.S. degree in chemistry
from National Tsing-Hua University, Hsinchu, Taiwan, R.O.C., and the Ph.D. degree in materials science and engineering from Lehigh University, Bethlehem, PA, in 1981 and 1991, respectively.
Since then, he has been working in the areas of compound semiconductor and VLSI processing. He joined Actrans System, Inc., Hsinchu, Taiwan, R.O.C., in 2000 focusing on Flash memory tech-nology integration. He is currently Vice President of technology.
Tseng-Yi Liu received the B.S. degree in electrical
engineering from Tamkang University, Taipei, Taiwan, R.O.C. in 1994, and the M.S. degree in electronics engineering from Yuan Ze Univer-sity, Taoyuan, Taiwan, R.O.C. in 1994 and 1996, respectively.
From 1998, he worked for Macronix, Hsinchu, Taiwan, R.O.C. as a Flash Memory Design Engineer. He participated in the circuit design of stacked-gate NORand NBit Flash memories as a Project Manager. He is currently the Design Manager and the Leader for split-gate Flash memory design in Actrans System, Inc., Hsinchu.
