閘極直接穿隧及邊緣直接穿隧實驗施於有縱向及橫向應力N-型通道金氧半場效電晶體

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國立交通大學

電子工程學系電子研究所

碩士論文

閘極直接穿隧及邊緣直接穿隧實驗施於有縱向及橫向應力 N-型通道

金氧半場效電晶體

Gate Direct Tunneling and Edge Direct Tunneling Experiment in

n-MOSFETs under Longitudinal and Transverse Stress

研究生：梁惕華 Ti-Hua Liang

指導教授：陳明哲 Prof. Ming-Jer Chen

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閘極直接穿隧及邊緣直接穿隧實驗施於有縱向及橫向應力 N-型通道

金氧半場效電晶體

Gate Direct Tunneling and Edge Direct Tunneling Experiment in

n-MOSFETs under Longitudinal and Transverse Stress

研究生：梁惕華 Ti-Hua Liang

指導教授：陳明哲 Prof. Ming-Jer Chen

國立交通大學

電子工程學系電子研究所碩士班

碩士論文

A Thesis

Submitted to Department of Electronics Engineering &

Institute of Electronics

College of Electrical and Computer Engineering

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of

Master of Science

In

Electronics Engineering

July 2008

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I Student: Ti-Hua Liang Advisor: Ming-Jer Chen

Department of Electronics Engineering Institute of Electronics

National Chiao Tung University

Abstract

This thesis investigates the conduction-band electron direct tunneling current through the 1.1 nm gate oxide of n-MOSFETs transistors that undergo transverse and longitudinal stress via a layout technique. By means of the triangular potential based quantum simulator (TRP), with known process parameters and published deformation potential constants as input, fitting of measured direct tunneling current versus gate voltage leads to the quantity of the channel stress. To examine the accuracy of the method, a link with the mobility measurement on the same device is conducted. The extracted stress is in good agreement with that of the direct tunneling, and therefore the experimental data are further utilized to extract the source/drain series resistance. Relating this external resistance to the dopant diffusivity under various stress conditions can lead to the activation energy per strain.

To reconfirm the validity of the above approach, the TRP simulator is again modified to deal with the edge direct tunneling counterpart. The resulting measurement data in the accumulation region furnishes the quantified gate-to-source/drain-extension overlap length. A retarded dopant diffusion phenomenon is straightforwardly observed. The corresponding strain-induced activation energy is then determined and is shown to be in good agreement with the extracted value obtained earlier. A physically oriented analytical model is therefore reached concerning the strain altered dopant diffusion.

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II 研究生：梁惕華指導教授：陳明哲博士國立交通大學電子工程學系電子研究所

摘要

本文研究電子自一個閘極氧化層厚度 1.1 奈米之 N-型通道金氧半場效電晶體，因為電路佈局而產生橫向及縱向應力之下之穿隧效應。藉由三角位能井模擬器 (TRP Simulator)，並由已刊出文獻取得重要的應力物理參數，可將實驗測得之穿隧效應電流和對應閘極電壓之間萃取出橫向及縱向應力。為了檢驗上述方法之精確度，元件的載子遷移率被同時量測，並依此萃取得到和前述方法相一致之應力。接著，本文將不同應力下之源極、汲極電阻值的變化，與擴散係數做聯結，得到單位應變之活化能。為了再證實本文之萃取方法之可靠度，藉由些微修正三角位能井模擬器，可以模擬由閘極穿隧至源極及汲極之邊緣電流 (EDT)，並可以藉此萃取出閘極與源極或汲極間之疊合處長度，觀察到掺雜載子擴散遲延的效應。最後，單位應變之活化能再次被萃取，並和先前的萃取數值吻合，再次驗證了本文方法之可靠度。一個以物理為導向之可解析模擬器也在此被提出。

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III

致謝

首先要感謝謝博的幫忙，提供了許多靈感與觸發，才能夠讓我有機會能夠完成這一篇論文；也謝謝林以唐親自編寫的三角位能井模擬器，沒有這個模擬器，許多的實驗萃取的物理量都得不到有力可靠的支持，也無法有機會進一步修正成 EDT 來進行其他模擬，同時，感謝實驗室裡的其他成員，他們的友善以及幽默每每讓實驗室充滿了溫暖與歡笑。尤其是湯侑穎，義不容辭地承擔了許多實驗室的外務，讓碩二的同學在這段時間內可以專心地研究以及寫論文。接著，還要感謝我的指導教授，陳明哲博士，在研究過程中的教導及不斷地提供有效地建議，讓我除了能自我發揮以外，還能有一個遵循的方向，紮實實驗的理論與分析的基礎，並增強物理的能力以及解決問題敏銳度。最後，感謝交大六年來的栽培，希望往後能有機會為交大發光發熱，回饋母校。研究生梁惕華

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IV

Abstract (English)

………...I

Abstract (Chinese)

………...II

Acknowledgement

………....III

………..… IV

Figure Captions

...V

Chapter 1 Introduction

………...1

Chapter 2 Stress Extraction

Section2.1 Device Under Study……….. .3

Section2.2 The TRP Simulator………...5

Section2.3 Stress Extraction via TRP Simulator………..…9

Section 2.4 Confirmative Evidence for the Extracted Stress………..…10

Chapter 3 Extraction of Activation Energy

Section 3.1 Stain Induced dopant diffusion………14

Section 3.2Extraction of Activation Energy………..….15

Chapter 4 Confirmative Evidence for Edge Direct Tunneling

Section 4.1 Edge Direct Tunneling ………..…..18

Section 4.2 Extraction of Activation Energy………...18

Chapter 5 Conclusion

………..…22

References

………...23

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V

Figure Captions

Fig.1 Schematic diagram of the relative position of the longitudinal stress and transverse stress acting on the silicon lattice.

………28

Fig.2 Schematic illustration of transverse and longitudinal stress components acting on the silicon lattice.

………29

Fig.3 Schematic diagram of the mathematical approach to derive the normal and shear stress.

………29

Fig.4 Corresponding stress tensor component in the n-MOSFET channel.

………30

Fig.5 Schematic diagram of the electron direct tunneling process and subband splitting for n-MOSFET.

………30

Fig.6(a) Schematic diagram of the conduction band structure of silicon in the unstressed case.

………31

Fig.6(b) Schematic diagram of conduction band structure of silicon in compressive stressed condition.

………31

Fig.7 Energy levels drawn along n+ poly-gate/SiO2/diffusion extension with no stress

applied.

………32

Fig.8 Energy levels drawn along n+ poly-gate/SiO2/diffusion extension with compressive

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VI

………33

Fig.9 Flow chart of the electron direct tunneling model.

………34

Fig.10 Calculated electron direct tunneling current change versus longitudinal stress under various transverse stress conditions.

………..………35

Fig.11 Measured electron direct tunneling change versus gate to STI spacing.

………..36

Fig.12 Measured mobility change versus gate to STI spacing with and without S/D series resistance.

………..………...…………37

Fig.13 Extracted longitudinal stress versus gate to STI spacing with and without S/D series resistance.

………..………...…………38

Fig.14 Extracted parasitic source/drain series resistance versus gate to STI spacing.

………39

Fig.15 Flowchart of the electron edge direct tunneling model.

………40

Fig.16 Band diagram drawn along n+

Fig.19 Energy level of the lowest two subbands and Fermi energy level under various gate poly-gate/SiO2/diffusion extension.

………41

Fig.17 Edge direct tunneling current change versus longitudinal stress.

………42

Fig.18 Edge direct tunneling current contributed by different subbands with gate voltage varying from to -0 to -1.4 V.

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VII biases.

………44

Fig.20 Energy level of the lowest two subbands and Fermi energy level under various stress conditions.

………45

Fig.21 Simulated edge direct tunneling current contributed by each of the subband for different compressive stress.

………46

Fig.22 Comparison of calculated experimental direct tunneling current versus gate voltage.

………47

Fig.23 Calculated gate-to-source/drain versus edge direct tunneling current with transverse stress as parameter.

………48

Fig.24 Extracted of gate-to-source/drain overlap length by means of comparing the calculated edge direct tunneling with the experimental data.

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1

Chapter 1 Introduction

Due to the aggressive downscaling of CMOS technology, shallow trench isolation (STI) induced mechanical stress can significantly alter many electrical properties such as hot carrier immunity [1], mobility [2-10], and gate direct tunneling current [5,10,11,15,17]. As a result, the capability of quantitatively determining the magnitude of the underlying mechanical stress as well as its status (compressive or tensile) is crucial. Three fundamentally different methods have been introduced in this direction: 1) wafer bending jig [18]; 2) sophisticated stress simulation [24]; and 3) the Raman spectroscopy [25]. Obviously, the electrical approach to mechanical stress determination was lacking to date. However, it is noteworthy that the gate direct tunneling current has been well studied under externally applied mechanical stress [15]. Therefore, with the well known deformation potential constants, it is plausible to measure mechanical stress by means of the gate direct tunneling current. Both experiment work and numerical stimulations have been conducted to extract the magnitude of the STI stress and to confirm our results by further extracting the dopant diffusion activation energy per strain.

In this thesis, we consider stresses acting in parallel and perpendicular to the channel direction, different from most studies primarily focusing on uniaxial and biaxial stress MOSFET devices [4]. Moreover, the ability to trace the electrical measurements on the formed device back to the stress-related dopant diffusion in the manufacturing process is also essential. Traditionally, this was done with the aid of the TCAD method [20],[26]. In this thesis, we also present the electrical approach to find the local mechanical stress around the source/drain extension of longitudinal and

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2 transverse stress n-MOSFETs. Straightforwardly, the underlying lateral diffusion can be determined, following by the confirmative evidence through the extra extraction of the activation energy.

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3

Chapter 2 Stress Extraction

Section 2.1 Device Under Study

The n+ poly-silicon gate n-MOSFETs were fabricated in a state-of-the-art manufacturing process. Three key process parameters obtained by the capacitance-voltage (C-V) fitting are as follows: n+

3 19

10 5× cm−

poly-silicon doping concentration = , gate oxide thickness = 1.1 nm, and substrate doping concentration =

3 17

10

3× cm . A layout technique was utilized to produce a variety of stress in terms of −

the gate edge to STI sidewall spacing, designated as a , with three values of 10, 2.4, and 0.21µ . m

In this thesis, different devices were characterized, for gate length L of 1µ and m

0.08µ , and gate width W of 10m µ and 1m µ . One of the device, with a gate edge m

to STI spacing of 10µ , is chosen as the reference due to the large values of both m

the gate edge to STI spacing and the gate width, indicating that the transverse and longitudinal stresses on the silicon lattice are negligible. For other devices , with the comparable gate width and gate length and gate to STI spacing of 10, 2.4, and 0.21µ , the transverse (m 110 ) and longitudinal stress ( 110 ) induced by the shallow trench isolation (STI) are nonnegligible. Table.I. lists the dimensions of the these devices along with the components of the stresses that must be considered. The cross symbol means that the stress component is negligible, whereas for the circle symbol the stress component needs to be taken into account.

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4 by the STI is depicted in Fig. 1, with transverse stress applied normal to the channel length direction and the longitudinal stress parallel to the channel length direction. Considering the transverse and longitudinal stress individually, we are able to further decompose the underlying stress into different components acting on each of the surface of the silicon lattice, as shown in Fig. 2.

In this thesis, the transverse and longitudinal stress are applied along the diagonal of the lattice structure, causing a change of 45 degree angle between the applied stress direction and the silicon lattice plane. At the mechanical equilibrium, we can subsequently construct a set of stress tensor component, by means of dividing the silicon lattice into four parts and hence analyze the stress components acting on each of the silicon lattice plane independently.

A mathematical approach to constructing the stress tensors are introduced in Fig. 3 and Fig. 4. The result can be written as follows:

(

)

(

)

(

)

                   − + + =                     − +                     =                     2 0 0 0 2 2 2 0 0 0 2 2 2 0 0 0 2 2 tran long tran long tran long tran tran tran long long long xy zx yz zz yy xx σ σ σ σ σ σ σ σ σ σ σ σ τ τ τ σ σ σ (1)

whereσxx,σyy,andσzz are the normal stress components acting on the faces perpendicular to the x, y and z direction respectively, and τxy,τyz,andτzxare the shear stress components oriented on the y, z, and x direction with normal to the x, y and z direction, respectively. σ_long andσ_trsn are the applied longitudinal and

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5 transverse stress, respectively.

Section 2.2 The TRP Simulator

The TRP simulator was constructed to quantify the direct tunneling current density on the basis of the triangular potential approximation in the channel, taking into account the poly-silicon depletion [12]. A good starting point to understand the band splitting induced by strain or stress is from the aspect of broken symmetry. Due to the commutation between operations and crystal Hamiltonian , symmetry plays a vital role in determining the band structure. The longitudinal and transverse compressive stress breaks the symmetry on the x-y plane where the channel lies such that the x-y plane is only symmetrical with respect to the two 110 diagonals.

The conduction band shifts are well defined in the literature[10-13] , and by means of a slight modification, the conduction energy shift for silicon under longitudinal stress σlong and transverse stress σtran in the reciprocal space along

[ ]

100,

[ ]

100,

[ ]

010,and

[ ]

010 directions can be written as:

(S S )

(

)

S S

(

)

(

)

( )eV

EC d σlong σtran u σlong +σtran = × σlong +σtran

     + Ξ + + + Ξ = ∆ 11 12 −11 12 11 2.922 10 2 2 (2) and

(

S S

)

(

)

( )

S

(

)

(

)

( )

eV

EC =Ξd + σlong+σtran +Ξu σlong+σtran =− × σlong+σtran

∆ −11

12 12

11 2 1.576 10 ₍₃₎

for

[ ]

001 and

[ ]

001 directions.

Therefore, we can show that strain alters the subband levels in the 2D confinement region by the following expressions [10-13]:

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6

(

)

(

)

(

)

(

long tran

)

u tran long u d eff S S S S m hqE E σ σ  − σ +σ      Ξ + + +      _Ξ ₊Ξ +         = ∆ ∆ ∆ 11 12 12 11 3 2 * 2 2 , 2 3 2 3 2 16 9 (4)

(

)

(

)

(

)

(

long tran

)

u tran long u d eff S S S S m hqE E σ σ  − σ +σ      Ξ − + +      _Ξ ₊Ξ +         = ∆ ∆ ∆ 11 12 12 11 3 2 * 4 4 , 4 6 2 3 2 16 9 (5) whereE_∆₂andE_∆₄denote the energy levels for the∆ and₂ ∆ valley ewspectively, the ₄ quantization effective masses are m*_∆₂ =0.92m_o and m_∆*₄ =0.19m_o, and the elastic compliance constants areS₁₁ =7.68×10−12

(

m2 N

)

andS₁₂ =−2.14×10−12

(

m2 N

)

. The hydrostatic and shear deformation potential constantsΞd =1.13eV andΞu =9.16eV , which are close to those in [15], were cited here. A qualitative schematic of the electron direct tunneling process and subband splitting for n-MOSFET is shown in Fig. 5.

Compressive stress from both the longitudinal and transverse direction causes the repopulation of the electrons, decreasing the electron density and Si/ SiO₂barrier height in the∆ valley, while increasing the electron density and ₂ Si/ SiO₂barrier height in the∆ valley [7]. Note from the expression listed above that the change in ₄ the conduction band energy may cause the strain altered gate leakage.

Sketched in Fig.6 (a) and (b) is the band structure for silicon, which are ellipsoids of constant electron energy in reciprocal space, each corresponding to one of the degenerate conduction band valleys. In this thesis, quantum confinement and stress both enhance the degeneracy between the four in-plane valleys(∆ ) and the two ₄ out-of- plane valleys (∆ ) owing to energy splitting. Compressive stress decreases the ₂ electron population in the ∆ valley due to a higher out-of-plane mass and a ₂ significantly longer lifetime compared to the∆ valley, resulting in an increased ₄

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7 electron tunneling current [5].

The electron direct tunneling current density can be modeled by the TRP simulator. First of all, the potential drop due to poly depletion is determined through the following expression [10]:Vpoly =ε_ox2F_ox2 2qε_siN_poly , and the substrate band bending

can be written as V_s = V_G −V_FB −V_poly −V_ox , where V_G is the applied gate voltage,V_FBthe flat band voltage , V the oxide potential drop, andox Vpoly the

potential drop in the n+

4

∆

poly-silicon region. The reference point of this model is the conduction band edge of the subband. Therefore , the tunneling barrier at the cathode-side interface and the relative positions of the∆ and₂ ∆ subbands can be ₄ defined as [14]: 4 BC BC(stressed)=φ (unstressed)−Ed φ (6) 4 2 2 2(stressed) E (unstressed) Ed Ed E_∆ = _∆ + − (7) ) ( ) ( ₄ 4 stressed E unstressed E_∆ = _∆ (8) where 3.15eV ) ( BC unstressed = φ (9)

(

)

(

)

(

)

(

long tran

)

u tran long u d d S S S S E σ σ  − σ +σ      Ξ + + +       Ξ + Ξ = ₁₁ ₁₂ ₁₂ ₁₁ 2 3 2 3 (10)

(

)

(

)

(

)

(

long tran

)

u tran long u d d S S S S E σ σ  − σ +σ      Ξ − + +       Ξ + Ξ = ₁₁ ₁₂ ₁₂ ₁₁ 4 6 2 3 (11)

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8

(

)

g( ) V1 d4

g stress E unstress E E

E = +∆ +∆ (12)

Fig. 7 presents the band diagram when the cathode side is stressed, whereas no stress is applied on the cathode-side. Taking into consideration that the n+

(

)

(

)

Z su m cath E cath 2 V_Si = poly-silicon region is also stressed, as depicted in Fig. 8, the electron group velocity normal to the interface in the anode-side should also be modified. By modeling the energy band as parabolic one, we can compare the relative energy shifts on both sides of the silicon oxide to derive electron group velocity normal to the interface on both the anode and cathode sides. The modifications in the following expressions alter the correction factors in our TRP simulator and thus change the transmission probability [14].

The normal component of electron group velocity on both the anode and cathode sides are listed below:

,

( )

Z su m An E An 2 V_Si = (13) where E_si

(

Cath

)

=

(

E_∆₂(unstressed)−

(

∆E_d₂ −∆E_d₄

)

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( )

(

d d

)

d d ox si An E unstressed E E  E E +qV ′ ∆ − ∆ + ∆ − ∆ − = _∆2( ) 2 4 2 2 E (15) 0 91 . 0 m mZ = for ∆ valley (16) 2

(

) (

( )

)

E_si Cath = E_∆₄ unstressed (17)

( ) (

)

d d ox si An E unstressed  E E +qV ′ ∆ − ∆ + = _∆4( ) 4 4 E (18) 0 19 . 0 m mZ = for ∆ valley (19) 4

the primed and unprimed symbols represent the energy shift in the n+ poly-silicon region and the underlying substrate region, respectively.

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9 It is now a straightforward task to calculate the electron direct tunneling current density. If all the subband energy levels are determined, then the inversion-layer carrier density per unit area can be expressed as [10-11],[13-15]

(

)

(

)

(

E E K T

)

m g T K N B _i _di _f _i _B i  + −      = ₂ ln1 exp 

π , where the subscript

i denotes∆ and2 ∆ ,4 KBT is the thermal energy,g is the degeneracy of the valley, and i di

m is the density of state effect mass. Then, by relating the boundary conditions

between the oxide and silicon surface, the charge conservation relationship

(

NS Ndepl

)

oxFox

q + ≈ε [10],[12] can be established. From now on, it is the TRP simulator that employs an iteration procedure to select the appropriate oxide field value to meet the above expression. The flowchart of the TRP simulator is drawn in Fig. 9.

Section 2.3 Stress Extraction via TRP simulator

After determining the relative positions on each of the two subbands and the Fermi level, the inversion-layer carrier density per unit area can be calculated. The Wentzel-Kramers-Brillouin tunneling probability, taking into account the corrections for reflections from the potential discontinuity is conducted [14]. Note that the electron dispersion relationship is used with m_ox =0.61m_o for the tunneling electrons in the oxide in the context of the Franz-type dispersion. Consequently, the electron direct tunneling current density can be calculated as a function of stress [10],[15].

(

)

₍

(

₎

)

₍

(

₎

)

tran long tran long tran long tran long tran long g qN qN J σ σ τ σ σ σ σ τ σ σ σ σ , , , , , 4 4 2 2 ∆ ∆ ∆ ∆ ₊ = (20)

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10 where σ is a fixed value in our experiment, thetran τ∆2andτ∆4 are the tunneling

lifetime for∆ and₂ ∆ valley , respectively. ₄

The gate direct tunneling current was measured in inversion conditions, with the source, drain, and substrate all tied to the ground. The simultaneously measured valance-band electron tunneling counterpart or equivalently the substrate hole current was found to be unchanged, regardless of stress [10]. This indicates that the gate oxide thickness under study remains constant. And the change of the conduction- band electron direct tunneling at VG =1V, all with respect to W=10µ , L=1m µ , m and a=10µ is then measured. m

With the above method, the transverse stress can be extracted by comparing W=10µ , L=1m µ , and a=10m µ with W=1m µ , L=0.08m µ , and a=10m µ . The m

longitudinal stress for the device W=1µ , L=0.08m µ can also be extracted . Fig. 10 m

shows the corresponding electron direct tunneling current change versus longitudinal stress under various transverse stress conditions.

The resulting gate current change versus the extracted channel stress is plotted in Fig. 11 for gate voltage of 1V. It is noteworthy that the magnitude of the gate current increases with the applied longitudinal stress. This phenomenon reveals the fact that as the source/drain diffusion length decreases, the STI approaches closer to the MOSFET core region and thus increases the magnitude of compressive stress.

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11 The mobility reduction under compressive stress mainly comes from the citation [5],[7]: Firstly, conductivity mass (the effective mass along 110 ) increases due to electrons repopulation from∆ to₂ ∆ valleys. The electron mobility partly decreases ₄ via a enhanced out of plane mass due to the unfavorable mass of the ∆ valley, ₂ which results in fewer electrons with the in-plane transverse effective mass and out-of- plane longitudinal mass. Secondly, intrinsic scattering is enhanced due to the splitting-induced DOS increase. Finally, conductivity mass (unstressed:

o l

o

t m m m

m =0.19 , =0.98 ) increases due to changes of the energy versus k-space curvature, named the band warping.

To furnish the confirmative evidence for our extracted longitudinal stress, numerous tasks must to be done. The most effective approach is to evaluate strain-altered mobility through the empirically determined piezoresistance coefficient, which has the benefit of capturing mobility reduction or enhancement on the basis of the changes in conductivity mass. To date , bulk piezoresistance coefficients have significantly been favored although essentially piezoresistance of MOSFETs from inversion-layer quantization should be used [5].

The mechanical stress effect on mobility is expressed as follows[5],[8],[18]:

⊥ ⊥

+ ≈

∆µ µ π//σ// π σ , where ∆µ µ is the fraction change in mobility, σ// andσ_⊥ are the longitudinal and transverse stress, respectively.

⊥

π

π// and are the longitudinal and transverse piezoresistance coefficients expressed

in −1

Pa , respectively.

S.Suthram , et al. [18] has shown that the piezoresistance coefficient for short devices only remains constant when a correction of the parasitic source/drain series

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12 resistance(Rsd)has been taken into consideration. Therefore, a constant-mobility method to enable MOSFET series-resistance extraction was applied. D. W. Lin , et al. [19] demonstrated that when different back- bias conditions are used on the same MOSFET device, the inversion carrier mobility converges to single curve when the effective silicon vertical electrical field is sufficiently high. In consequence, comparing the same device operating in linear region with two different back biases,

V V

and V

V_B =0 _B =−0.4 ,we are able to extract the parasitic source/drain series resistance. The mobility was then modified by using the following expression:

(

ds d

)

ds V Rsd W I V ) ( ) ( − = ′ µ µ (21) whereµ′denotes the modified mobility.

The modified mobility change versus extracted stress is shown in Fig. 12, with the piezoresistance coefficients of 、 2 1 12 // 31.6 10 dyn cm − × − = π 12 1 2 10 6 . 17 dyn−cm ⊥ =− × π .

With the transverse stress fixed to value of -300MPa (Section 2.3), we can further extract another set of longitudinal stress for gate to STI spacing values. Illustrated in Fig. 13 is the comparison of our two stress extraction approaches, one from the stress induced electron direct tunneling current change and the other from the piezoresistance coefficient extraction.

With the above method , the transverse stress extracted by comparing W=10µ ,L=1m µ , and a=10m µ with W=1m µ ,L=0.08m µ , and a=10m µ is around m

-300MPa. The longitudinal stress for the device W=1µ and L=0.08m µ is around 0, m

-50MPa, and -310Mpa for a gate-to-STI spacing of 10µ ,2.4m µ , and 0.21m µ , m

(22)

13 validity of our methodology has been corroborated.

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14

Chapter 3 Extraction of Activation Energy

Section 3.1 Strain Induced Dopant Diffusion

In the present paper [20] , dopant impurities introduced to form n-MOSFETs are boron, indium, arsenic and phosphorus. Extraction of parasitic source/drain series resistance implies that stress may alter the doping profiles. Specifically, most of the impur ities are retarded by compressive stress.

We then seek relations between the dopant diffusivity and the activation energy per unit strain. An approach dealing with dopant diffusion dependencies on strain is briefly depicted in the following procedure. The general concept of our approach is to express dopant diffusion under mechanical stress. In the case of compressively strained silicon, the dopant diffusion dependence follows the Arrhenius form [20]:

     − = KT QV D D_S _I exp (22) whereD is the dopant diffusivity under strain,S D is the dopant diffusivity without I strain, V is strain volume change ratio due to stress, Q is the activation energy per volume change depending on dopant species, andTis the temperature. In our case, when the stress is small, by converting our developed stress tensor into strain tensor, the resulting matrix is shown below:

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(

)

(

)

(

)

(

)

                                    +       +       + +       + + =                         + + =                     ⇒                         =                     4 0 0 2 2 2 4 0 0 2 2 2 0 0 0 2 2 44 12 12 11 12 11 44 12 12 11 12 11 tran long tran long tran long tran long xy zx yz zz yy xx xy zz yz zz yy xx S S S S S S S S S S S S σ σ σ σ σ σ σ σ σ σ σ σ ε ε ε ε ε ε σ σ σ τ τ τ σ σ σ

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15 Then, we divide our studies into two categories:

yy xx V Case1: ≈ε +ε ZZ yy xx V Case2: ≈ε +ε +ε

Both cases neglect the volume change caused by shear stress components, assuming that all volume change is due to normal stress components. Moreover, the first case further neglects the volume change in the z direction.

Section 3.2 Extraction of Activation Energy

The general form of the diffusivity for a dopant A is:

(

)

(

)

(

)

2 0 _i AX i AX i AX AX A D D P n D n n D n n D = + + + − + = (24)

Where each diffusion component has a pre-exponential factor and activation energy of diffusion such as D_AX0 =D0exp

(

−E0 KT

)

. The diffusivity of phosphorous and

arsenic is shown in the following:

(

)

(

)(

i

)

As KT KT n n D =8×exp4.05 +12.8×exp 4.05 (25)

(

)

(

)(

)

(

)(

)

2 37 . 4 exp 2 . 44 4 exp 44 . 4 66 . 3 exp 84 . 3 _i _i p KT KT n n KT n n D = × + × + × (26)

Value s for the diffusivity of phosphorous comes from Fair [21] , values for arsenic comes from Chin and Barbuscia [21]. The expressions for arsenic agree reasonably well with experiment, while the value for phosphorous is not as reliable due to anomalies [21]. The diffusivity of phosphorus is explained as a vacancy dominated diffusion, and in high concentration region the extrinsic diffusivity of phosphorus is given by:

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16 2 0       + = = i P P P n n D D D (27) whereD is the neutral vacancy,_P0 D is the doubly negatively charged vacancy, and _P=

i

n is the intrinsic carrier concentration. Note that in extrinsic diffusion region, such as

the MOSFETs’ source/drain region, the assumption is made that the diffusivity of phosphorus is essentially proportional to the square of the dopant concentration. Arsenic, another type of impur ity as mostly used in MOSFET, is believed to diffuse primarily through a vacancy mechanism with an interstitialcy component. Above approximately 1000 C0 _{, diffusion is dominated by vacancy pairs} + −

V s A with = + V

As being relatively rare to the small binding energy. The diffusivity of arsenic can be written as:       + = − i AS AS AS n n D D D 0 (28)

where D_AS− is the negatively charged vacancy. And in extrinsic diffusion region. The assumption is also made that the diffusivity of phosphorus is essentially proportional to the dopant concentration.

Then, given that the parasitic source/drain series resistance is inversely proportional to electron mobility and the dopant impurity concentration, we are able to relate the dopant diffusivity to the source/drain series resistance. By examining the experimental data, we found that the change in mobility is less than the change of source/drain series resistance, which implies that the stress acting on the silicon lattice not only alters the electron population in the subbands, but alters the doping profile, showing dopant diffusion retardation phenomenon. The result can be shown in Fig. 14.

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17 Finally, the activation energy per strain is obtained. For case one, which neglects the strain in the z direction, by comparing the differences in diffusivity under different stress conditions, an analytical model can be obtained the following formula.

(

)

(

)

(

)

(

)

(

)

( )

(

₍

₎

)

(

)

_      ×       ′ ′ − = ⇒ ′ ′ =       × − =      − ′      − + ′ = ′ ′ σ σ σ σ σ σ σ σ σ ε ε ε ε ε ε 9 9 10 180 , 0 , ln , 0 , 10 180 exp exp exp , 0 , KT D D Q D D KT Q KT Q KT Q D D (29)

whereεandε′denotes the strain induced by the longitudinal stress and transverse stress. Subsequently, case two can also be derived:

(

)

(

)

(

)

(

)

(

)

( )

(

₍

₎

)

            × − ×       ′ ′ − = ⇒ ′ ′ =             × − × − =      − ′      − + ′ = ′ ′ 9 9 9 9 10 467 10 180 , 0 , ln , 0 , 10 467 1 10 180 1 exp exp exp , 0 , σ σ σ σ σ σ σ σ σ σ ε ε ε ε ε ε KT D D Q D D KT Q KT Q KT Q D D (30)

Here, a typical temperature of 1300Kfor the manufacturing process is used. The activation energy can hence be determined.

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18

Chapter 4 Confirmative Evidence for Edge Direct Tunneling

Section 4.1 Edge Direct Tunneling

Direct tunneling current from the gate overlap region into the underlying source/drain extension region (also identified in current literature as edge direct tunneling or EDT) has been identified as the principal source of offstate power dissipation in state-of-the-art VLSI chips. Yang, et al. [22]. has also shown that this component of gate leakage exceeds even band-to-band tunneling (BTBT) and gate induced drain leakage (GIDL) for ultrathin gate oxide n-MOSFETs. When the gate electrode is biased negatively, the gate overlap region over the source/drain extension region immediately goes into accumulation given the fact that the flat band voltage between the heavily doped n+ poly-Si region and the source/drain extension region is almost zero. However, the poly gate region over the p-type substrate remains in depletion until Vg=Vfb

The electron direct tunneling from the accumulated poly-silicon surface down to the underlying silicon was measured. To determine the underlying gate-to-source/drain extension overlap length where the EDT prevails, the TRP

(for the poly gate and p-type substrate).Here the flat band voltage is approximately −1.0 V. These accumulated electrons in the gate overlap region tunnel into the source/drain extension region, giving rise to the edge direct tunneling.

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19 simulator has been modified to meet our requirements. Fig. 15 shows the flow chart of the TRP simulator in case of EDT current. And the band diagram drawn along n+ poly-gate/SiO2 DE 2 2 DE 2 V =ε_oxF_ox qε_siN

/diffusion extension is shown in Fig. 16.

First of all, the potential drop due to poly depletion is determined through the following expression [22-23]: , where N_DEandV are the _DE dopant concentration and potential drop in the source/drain extension respectively. The poly gate band bending can be described asVDG −VFB =Vpoly +Vox +VDE , whereVDGis the applied gate voltage,V the flat band voltage, andFB V the oxide ox potential drop. The reference point remains the same: the conduction band edge of the

4

∆ subband. The stress in the source/drain region is also considered. In the modeling processes, including the determination of the subband energy shift caused by the applied stress, the calculated inversion-layer carrier density per unit area follows that of modeling electron direct tunneling current, except that the charge conservation relationship should be rewritten asq

( )

NS ≈εoxFox. The poly-silicon gate is now operating at accumulation region, with no depletion charge existing. Another difference is that the flat band voltage is nearly zeroV_FB ≈ (compared with 0

(

)(

)

[

Eg q+ KT q Nsub NV

]

=

-V_FB for modeling electron direct tunneling current ) and the Fermi level becomesE_F =q

(

V_poly +V_FB

)

(compared with EF =q

(

V_s +V_FB

)

for modeling electron direct tunneling current).

As a result, the gate-to-source/drain overlapL_TNcan be directly extracted [22]:

(

)

₍

(

₎

)

₍

(

₎

)

tran long tran long TN tran long tran long TN tran long qN WL qN WL I σ σ τ σ σ σ σ τ σ σ σ σ , , , , , 4 4 2 2 EDT ∆ ∆ ∆ ∆ + = (31)

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20 whereWis the channel width, andN_∆₂andN_∆₄ are the available charge in∆ and₂ ∆ ₄ valley for tunneling process, respecticely. The tunneling lifetime in the following equations can be connected with the transmission probability:

(

) (

)

(

σlong σtran σlong σtran

)

π

τ_∆₂ =  T_∆₂ , E_∆₂ , (32)

(

) (

)

(

σlong σtran σlong σtran

)

π

τ_∆₄ =  T_∆₄ , E_∆₄ , (33)

It is worthy to notice that with our modified TRP simulator , the retarded dopant diffusion phenomenon caused by STI stress can be systematically treated . The tunneling current density change under different stress conditions only reflects the change in the available charge for tunneling and the tunneling lifetime. However, by examining the differences between the modeling result and the experiment data, it is a straightforward task to extract the gate-to-source/drain overlapL_TN.

J J J J J ∆ = − 2 2 1 (34)

The above equation represents the tunneling current density change for different stress conditions 1 and 2, as shown in Fig.17. If the retarded dopant diffusion was applied, the change in tunneling current is rewritten as:

J J L L J J J J J L L L J J WL J WL J WL J WL J WL J WL J WL J WL J TN TN TN TN TN TN TN TN TN TN TN TN TN ∆ + ∆      ∆ ₊ = − +         ₋ ′ = ′ − + − ′ = − ′ 1 2 2 1 2 1 2 2 1 1 1 2 2 1 (35) where J J ∆

can be derived by the TRP stimulator, whereas

TN TN TN WL J WL J WL J 2 2 1 − ′ can be subsequently obtained by comparing experimental data.

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21 subbands with gate voltage varying from -0 to -1.4 V. Fig. 19 reveals the energy level of the lowest two subbands and Fermi energy level under various gate biases. The energy level of the lowest two subbands and Fermi energy level under various stress conditions is shown in Fig. 20, which indicates a narrow in energy- level spacing between the lowest two subbands as applied stress increases. Fig.21 shows simulation results of the edge direct tunneling current contributed by each of the subband operating under different compressive stresses. Finally, the extracted gate-to-source/drain overlapL_TNspans a range of, 6.5nm, 6.35nm, and6.25nm for a=10µ , 2.4m µ , and 0.21m µ , respectively. Other extractions results are shown in m

Fig. 22, 23 , and24.

To reconfirm our results, given that the gate-to-source/drain overlap L_TN is proportional to Dt ,then the diffusivity change under different stress condition

Dt Dt ∆ =

∆ LL is calculated. Then applying the expressions listed in section 3.1, the activation energyQ

( )

σ can be reproduced. Table 2. lists of the value of the activation energy extracted by the two approaches. Approach one mainly focuses on the series-resistance change under applied stress in order to obtain the diffusivity difference, whereas approaches two aims at the gate-to-source/drain overlap difference caused by stress for the extract ion of the diffusivity change. Note that our results from the parasitic source/drain series resistance are quantitatively consistent with the gate direct tunneling mode , especially in case 2. This indicates that both the longitudinal and transverse in-plane stress to cause considerable deformation in the Z direction.

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22

Chapter 5 Conclusion

With the known process parameters and published deformation potential constants as input, fitting of the gate tunneling current versus gate voltage data has led to the value of the underlying channel stress. By utilizing the constant mobility method, the parasitic source/drain series resistances are extracted. The increase in series resistances under high in-plane stress has revealed a dopant retarded diffusion. Moreover, the method to calculate activation energy has been illustrated. To further confirm our results, the edge direct tunneling technique has been applied, thus extracted the actual gate-to-source/drain overlapL_TNas well as magnitude under different stress conditions. Consequently, the activation energy has again been obtained and has matched well with that of source/drain series resistance as well as the process simulation.

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23

Reference

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[9] Ken Uchida, Tejas Krishnamohan, Krishna C. Saraswat, and Yoshio Nishi, “Physical Mechanisms of Electrons Mobility Enhancement in Uniaxial Stressed MOSFETs and Impact of Uniaxial Stress Engineering in Ballistic Regime, IEEE, 2005.

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[11] I. Balslev, “Influence of uniaxial stress on the indirect absorption edge in silicon and germanium”, Phy s. Rev., Vol. 143, No. 2, March. 1966.

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25 [12] H. Hartmut Mueller and Max J. Schulz, “Simplified Method to Calculate the Band Bending and the Subband Energies in MOS Capacitors.”, IEEE Tran. Electron

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27 [24] R.A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, "Accurate modeling of trench isolation induced mechanical stress on MOSFET electrical performance "in

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28

Table. I

(38)

29

Fig.2

(39)

30

(40)

31

Fig.5

(41)

32

(42)

33

(43)

34

(44)

35

(45)

36

Fig.11

0

2

4

6

8

10

0

2

4

6

8

10

12

14 (∆

I

g

/I

g

) @V

g

=

1 V

(

%)

Gate to STI Spacing (

µm)

(46)

37

(47)

38

(48)

39

(49)

40

(50)

41

(51)

42 -5 -4 -3 -2 -1 0 x 108 0 5 10 15 20 25 Longitudinal stress(Pa) del taJ ED T /J ED T (% )

Fig.17

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43 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5x 10 6 -Vg(V) J ED T (A/ m 2 ) J total J delta 2 J delta 4

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