A Broadband and Scalable Lossy Substrate Model
for RF Noise Simulation and Analysis in Nanoscale
MOSFETs With Various Pad Structures
Jyh-Chyurn Guo, Senior Member, IEEE, and Yi-Hsiu Tsai
Abstract—An enhanced lossy substrate model is developed with
important features of broadband accuracy and scalability. The broadband accuracy is justified by a good match with open pad -parameters measured up to 110 GHz and MOSFETs’ - and -parameters over 40 GHz. The proven model can accurately simulate four noise parameters (NFmin, , Re( opt), and
Im( opt)) and power spectral density of current noises ( and
). The scalability has been validated over nanoscale MOS-FETs with different finger numbers and adopting various pad structures (lossy, normal, and small pads). This scalable lossy substrate model attributed to two substrate RLC networks under the pads and transmission lines (TMLs) can consistently predict the abnormally strong finger number dependence and nonlinear frequency dependence of noise figure(NFmin) revealed in devices with lossy pads. The enhanced model is useful in guiding pad and TML layouts for effective reduction of extrinsic noises and low noise design. Using a normal pad structure, the NFmin can be effectively suppressed to approach the intrinsic performance, which is nearly independent of finger numbers.
Index Terms—Broadband, lossy substrate, nanoscale MOSFET,
pad, RF noise, scalable.
I. INTRODUCTION
C
OMPACT MOSFET model with broadband accuracy and scalability is a critical engine driving the success of RF CMOS circuit design [1]–[7]. To meet the increasing demands on low power and low noise in wireless communication using advanced CMOS technology, an accurate scalable noise model able to predict the lossy substrate noise is strongly required [7]–[9]. However, a reliable noise deembedding method for an accurate extraction of intrinsic noise remains a difficult sub-ject and is particularly challenging for nanoscale devices on a lossy substrate. The fundamental challenge is how to measure and simulate the extrinsic noise in miniaturized devices, which are generally complicated by high-frequency coupling through the pads and transmission lines (TMLs) to the lossy substrate. A noise correlation matrix method [10] was frequently appliedManuscript received July 03, 2008; revised October 14, 2008. First published January 06, 2009; current version published February 06, 2009. This work was supported in part by the National Science Council under Grant NSC 96-2221-E009-186 and Grant NSC 97-2221-E009-175.
The authors are with the Institute of Electronics Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (e-mail: [email protected]. edu.tw; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2008.2009903
for noise deembedding, but the sophisticated matrices calcula-tion sometimes suffers an abnormal fluctuacalcula-tion at lower noise levels and undesired deviation in frequency dependence [11], [12]. Actually, noise correlation matrix method limits itself to discrete data available from measurement and is vulnerable to data fluctuations over frequencies, which cannot be avoided in noise and -parameter measurement. These limitations make it not applicable to noise simulation and prediction for RF circuit design.
A lossy substrate model was first developed in our pre-vious work for simulating measured noise parameters. A lossy substrate deembedding can then be easily performed through circuit simulation for a reliable extraction of the intrinsic noises [13]–[15]. The accuracy has been checked in RF MOSFETs with various finger numbers and operation under varying fre-quencies. A comparison with noise correlation matrix method can justify the advantages of lossy substrate deembedding method in terms of accuracy, reliability, and compatibility with circuit simulation.
Restricted bandwidth is a common problem for conventional substrate models assuming a simple resistive network or an RC network. The simplified model may be valid in sufficiently low frequency ( 10 GHz), but is no longer accurate to fit the high-frequency domain up to tens of gigahertz. The limitations of a simple RC model have been investigated through a serious com-parison between electroquasi-static (EQS) and electrodynamic (ED) models [16]. The results reveal an inductive like character-istics in noise propagation through the substrate and suggest that ED model is indispensable to an accurate simulation in high fre-quency over several tens of gigahertz. Unfortunately, the elec-tromagnetic (EM) analysis requires complicated computation and extensive memory, and is not suitable for circuit simula-tions. Thus, an enhanced lossy substrate model is developed in the form of a lumped element circuit to be fully compatible with circuit simulators in terms of easy implementation and compu-tation efficiency. The circuit schematics incorporating two sub-strate RLC networks in series with pads and TML coupling ca-pacitances ( and ) can accurately simulate substrate losses through the pads and TML, respectively. A character-istic frequency responsible for the minimum of [or ] in pad -parameter over 110 GHz represents the resonance of substrate RLC network and justifies the substrate inductance introduced in our lossy substrate model. The adoption of is a key feature, which differentiates the hanced lossy substrate model from conventional ones and en-ables a broadband accuracy.
Beside the broadband accuracy, a scalable lossy substrate model is strongly required to predict high-frequency perfor-mance of on-chip devices and circuits with diversified options in pad and TML layouts, as well as metal topologies. To meet this demand, an improved lossy substrate model was initiated in our recent study [17] and demonstrated an apparent scaling trend corresponding to pad structures. However, a scalable model with mathematic expressions for a quantitative analysis and prediction is not yet available. In this paper, the enhanced lossy substrate model can provide a promisingly good solution in this aspect. All the model parameters are scalable and can be predicted by an explicit function depending on . In this manner, the enhanced model can help explore the pad structure effect on high-frequency noises in nanoscale devices and guide an optimal layout in pads and TML for an effective reduction of extrinsic noise and low noise design. Note that the substrate resonance frequency strongly depends on as well, and can be predicted according to the scalable model parameters.
II. DEVICETECHNOLOGY ANDCHARACTERIZATION n-MOSFETs with 100-nm gate length were fabricated in a p-well enclosed by a deep n-well, a so-called triple well process for substrate noise isolation. Note that triple well isolation against noise is limited to a few gigaahert and is no longer valid in very high frequencies up to several tens of gigahertz [18]. A multifinger structure with a fixed finger width of and various finger numbers of
and were designed to investigate the impact on high-fre-quency noise, as well as the model scalability over device geometries. Ground–signal–ground (GSG) pads for RF mea-surement were fabricated by Cu/fluorinated silicated glass (FSG) back-end-of-line (BEOL) process with eight layers of Cu and FSG as inter-metal dielectric (IMD). To study lossy substrate effect on high-frequency noise and the extrinsic noise introduced through the pad and TML, three pad structures (lossy, normal, and small) were created. All three share the same ground pad (G-pad) layout and structure, but different signal pads with variation in topology and dimension.
Two-port -parameters were measured by an Agilent vector network analyzer up to 40 GHz for full structures with devices-under-test (DUTs) and GSG pads together. An ultra-wideband measurement to 110 GHz was done on dummy open pads for broadband model development and validation. - and -parameters can be derived from -parameters for extraction of gate capacitances and cutoff frequency . Noise parameters ( , , , or ) were measured by ATN-NP5B to its limitation at 18 GHz under a fixed gate
bias V A two-step deembedding
procedure assisted by open and short dummy pads was carried out to extract the parallel and series parasitic RLC elements. For high-frequency and noise simulation, the incorporation of accurately extracted resistances and inductances associated with MOSFET’s termi-nals is crucial to improve the accuracy. Gate resistance dominates the input characteristics ( and ), noise figure
, and current noises ( and ), whereas the bulk parameters , , and primarily influence the output
Fig. 1. 3-D configuration of GSG pads. (a) Lossy pad scheme:S-pads with stacked metals from M2 to M8. (b) Normal pad:S-pads with top metal (M8) only. (c) Equivalent circuit schematics of an enhanced lossy substrate model applicable to lossy, normal, and small pad schemes. After [17].
characteristics ( and ), noise resistance and its frequency dependence.
III. BROADBAND ANDSCALABLELOSSYSUBSTRATEMODEL FORVARIOUSPADSTRUCTURES
In this paper, an enhanced lossy substrate model is developed to attain two ultimate goals, namely, broadband accuracy and scalability. The scalability will be extensively verified over var-ious pad structures and their effect on high-frequency -param-eters and noises in nanoscale devices.
A. Pad Structures and Enhanced Lossy Substrate Model
Three GSG pad structures defined as lossy, normal, and small pads with different metal topologies or pad dimensions were fabricated in Cu/FSG BEOL process to investigate the resulting lossy substrate effect. Fig. 1(a) and (b) illustrates the 3-D configuration of lossy and normal pads in which the G-pads were constructed with stacked metals from bottom (M1) to top (M8), while the -pads were built with two different schemes. For lossy pad scheme in Fig. 1(a), the -pads are composed of stacked metals from M2 to M8, whereas for the normal pad scheme in Fig. 1(b), they are consisted of top metal (M8) only and excluding all lower metals. As for the small pad scheme, its -pads just follow that of normal pad scheme but with a smaller size of 50 m 35 m with respect to 50 m 50 m for normal and lossy ones. All three pad structures adopt exactly the same G-pad topology.
Fig. 1(c) depicts the equivalent circuit schematics of the en-hanced lossy substrate model to cope with various pad struc-tures. The primary improvement over the original model is the adoption of underneath substrate RLC network associated with TML, which represents the coupling capacitance between
Fig. 2. Equivalent circuit analysis and topology conversion for lossy substrate model parameter extraction.
TML and substrate. As a result, the enhanced model is com-posed of two substrate RLC networks under the pad and TML in which the substrate loss is coupled through the pad and TML via and , respectively.
B. Improved Parameter Extraction Method and Broadband Accuracy
An improved parameter extraction method is developed for the enhance lossy substrate model based on the equiv-alent circuit in Fig. 1(c) and broadband -parameter mea-sured to 110 GHz for open pads with various structures in Fig. 1(a) and (b). Through a comprehensive circuit analysis and an appropriate circuit topology conversion illustrated in Fig. 2(a)–(c). The extraction flow was established with corre-sponding formulas as follows.
At the first step, the original equivalent circuit consisting of two branches of RLC networks with physical RLC elements at each port form a two- scheme, as shown in Fig. 2(a). Trough a simple circuit analysis, the two- scheme was then converted to a single- topology with a single RC network at each port, il-lustrated in Fig. 2(b). Note that all RLC in Fig. 2(a) are physical elements independent of frequency, whereas and in Fig. 2(b) incorporate the original RLC and frequency depen-dence. Eventually, the single- topology in Fig. 2(b) was con-verted to an equivalent circuit scheme in Fig. 2(c) in which ,
, and can be directly determined from measured , , and according to (1)–(3) as follows:
(1) (2) (3) The capacitive elements can then be extracted at very low frequency when the resistance and inductance introduced im-pedances are negligibly small. The port-to-port coupling capac-itance was determined from in (4). , , , and in substrate RLC networks were extracted from
TABLE I
COMPARISON OFC ANDC BETWEEN1-D PLANARCAPACITORMODEL, 3-D RAPHAELSIMULATION,ANDOPTIMIZEDMODEL
and [see Fig. 2(c)] in (5) and (6) and relevant approxima-tions for lossy, normal, and small pads in (7) and (8) as follows: (4)
(5)
(6)
For lossy pad
(7)
For normal and small pads
(8) Note that and are known with the initial values calculated by 3-D RLC simulation (Raphael) following layout and process parameters (metal thicknesses, IMD thicknesses, and dielectric constants) instead of extraction. Table I summa-rizes the comparison between 1-D planar capacitor model, 3-D Raphael simulation, and the optimized ones through a best fit-ting to measured -parameters. The results reveal a significant underestimation using 1-D planar model, whereas a very close match with the optimized values when adopting 3-D Raphael simulation. It suggests that the approximation by a simplified 1-D planar capacitor model is no longer valid due to inappro-priate neglect of the fringing capacitances in a 3-D topology. are kept at a similar value for different pad structures due to the same metal layout and topology for TML from the pads to intrinsic device. On the other hand, present a significant difference among the three pad structures in which the scaling factors of around 3.9 for the lossy versus normal pads and near 0.75 for the small versus normal pads just approach the theoret-ical values predicted by 3-D Raphael simulation. The substan-tially larger for lossy pad compared to normal and small pads, whereas very similar in three different pads present a result consistent with layout and metal topology.
Following the first step, as all the capacitive elements are al-ready known, we can now perform an extraction of resistive and inductive elements ( , , , and ) by selecting a
Fig. 3. Measured and simulated magnitude (S ) over frequencies up to 110 GHz for normal and lossy pads. A characteristic frequency responsible for the minimum ofmag:(S ) is defined as ! . Normal pad: f 90 GHz. Lossy pad:f 50 GHz.
very high-frequency domain, where the inductance effect be-comes significant. As shown in Fig. 3, the measured
[or ] presents a minimum at a frequency situated around 50 GHz (for the lossy pad) or 90 GHz (for the normal pad). This characteristic frequency is due to a resonance ap-pearing in the equivalent LC tank of the substrate network. It appears from circuit analysis that can be mod-eled as a function of and in (9) and (10). Note that is an effective capacitance representing in series with and , which are in parallel, referring to Fig. 2(a). In this way, the substrate inductance can be determined from the mea-sured and in (9) and (10) with known and , as well as . can then be extracted from (11) and (12) under a relevant assumption of with known ,
and as follows:
(9) (10) (11) (12)
Following the second step, all of capacitive and inductive el-ements are known to go the final step for extracting the resistive elements ( and ). The original expressions of and for extracting and are lengthy due to in-corporating all RLC elements. To simplify the problem, char-acteristic frequencies and determined by
and in (11) and (12) are specified to effectively re-duce the formulas, as shown in (13) and (14), corresponding to . As a result, and can be easily extracted from (13) and (14) in which all the elements, except themselves, are known from previous steps of the extraction flow. The extracted parameters serving as the initial model can successfully facilitate an optimization process through the best fitting to measured -parameters over 110 GHz.
TABLE II
OPTIMIZEDRLC PARAMETERS OF THEENHANCEDLOSSYSUBSTRATE
MODELCORRESPONDING TOTHREEPADSTRUCTURES, LOSSY, NORMAL,ANDSMALLPADS
Table II presents the optimized RLC parameters for the en-hanced lossy substrate models associated with lossy, normal, and small pads, respectively. The assumption of
made in (12) for initial extraction is justified by the optimized parameters , , , and . The broadband accuracy of the enhanced model is proven by a good match with mea-sured -parameter over broad frequencies up to 110 GHz in Fig. 3 and an accurate prediction of at around 90/50 GHz for normal/lossy pads, respectively. The apparently lower for lossy pad consistently reflects influence from the dramatic increase of originated from the metal stack topology in lossy pads
(13)
Fig. 4. Scaling trend of RLC parameters versusC in improved lossy sub-strate models for lossy, normal, and small pads. Gate pad (port-1): (a) capacitive elementsC , C , and C (b) resistive and inductive elementsR , L , R , and L .
Fig. 5. Scaling trend of RLC parameters versusC in original lossy substrate models for lossy, normal, and small pads. Gate pad (port-1): (a) capacitive el-ementsC , C , and C (b) resistive and inductive elementsR , L , R , and L .
C. Model Scalability Over Various Pad Structures
Fig. 4 illustrates the extracted RLC model parameters versus corresponding to lossy, normal, and small pads at port-1 (Gate). All RLC elements in this enhanced lossy substrate model present a good scalability featured by a linear function of . For capacitive elements shown in Fig. 4(a), each of them can be predicted by a linearly increasing function. The larger introduces larger substrate network capacitances and subsequently worse substrate loss. As for the resistances and inductances in Fig. 4(b), each individual element follows a linearly decreasing function. The larger results in the smaller substrate resistances and inductances. Note that the increase of capacitances while decrease of resistances and inductances lead to the same trend in substrate loss and noise coupling. A similar scaling relationship in RLC parameters versus can be achieved for port-2, i.e., drain pad (not shown for brevity), which approach closely what was presented in Fig. 4 for port-1 (gate). The lossy pads featuring larger ca-pacitances and smaller resistances will introduce more extrinsic noise and make devices suffer larger noise. The scalability of
RLC parameters in the enhanced lossy substrate model is
fea-tured by an apparent correlation with pad structures and metal topologies represented by . This dependence in the form of a linear function with respect to yields a physics-based and predictive model.
On the other hand, for the original lossy substrate model without , the RLC parameters versus shown in Fig. 5 revealed abnormal results, such as losing a simple linear func-tion with a single slope. For lossy pad compared with normal or small pads with a big difference in , a monotonic increase in substrate network capacitances is demonstrated. However, looking at normal pad versus small pad, an abnormal trend
Fig. 6. Equivalent circuit of MOSFET with parasitic resistances, capacitances, and inductances for dc, ac, RF, and noise simulation.
with a negative slope appears in Fig. 5(a), meaning that the larger leads to the smaller substrate capacitances. The abnormal scaling trend makes the original model not scalable in a certain region for different pad structures with small dif-ference in . Reviewing Fig. 5(b) for substrate resistances and inductances versus , a similar problem of a negative slope in a narrow region is identified in , , and , but the situation is worse in the plot of , which reveals a similar trend over a larger area.
IV. PADSTRUCTUREEFFECT ONRF NOISE—SIMULATION BY BROADBAND ANDSCALABLELOSSYSUBSTRATEMODEL The enhanced lossy substrate model can be easily integrated with intrinsic devices in a standard circuit simulator for a global noise simulation. The primary objective is to investigate the impact of substrate loss on high-frequency characteristics and noise performance with particular interest in pad structure ef-fects on extrinsic noise in nanoscale MOSFETs with various finger numbers. One more interesting and useful application is an accurate and simple noise extraction method to facilitate noise simulation accuracy for low noise CMOS circuit design.
For the reader’s convenience, we recall that the “extrinsic noise” represents the noise generated from all parasitic elements outside of the intrinsic device like the pads, TML, and lossy sub-strate. The “global noise” represents the sum of intrinsic noise and extrinsic noise. The measured noise, before the pad and lossy substrate deembedding is equal to the global noise.
A. MOSFET Model and Parasitic Parameter Extraction
Fig. 6 presents MOSFET equivalent circuit dedicated to dc, ac, RF, and noise simulation. The four terminal device is trans-formed into three-terminal configuration because the source and bulk are internally shorted. The gate resistance incorpo-rates poly gate resistance, metal resistance, and channel sheet resistance. For a 100-nm device in a strong inversion region, channel sheet resistance is negligible compared with poly and metal resistances. and incorporate only the metal resis-tance. represents the bulk resistance. , , and are the parasitic inductances of the metal lines connecting ground/
Fig. 7. R extracted for 100-nm nMOS with various finger numbers (N = 18; 36; 72). (a) Y -method, R = Re(Y )=[Im(Y )] . (b) Z-method, R = Re(Z 0 Z ).
Fig. 8. Comparison of measured and simulated Mag(S ) using R ex-tracted for 100-nm nMOS with various finger numbers (N = 18; 36; 72) (a) Y -method, R = Re(Y )=[Im(Y )] . (b) Z-method, R = Re(Z 0 Z ).
drain/source (G/D/S) contacts to pads. Their contributions be-come significant only at very high frequencies.
First, the parasitic and ( , , , , , , and ) were carefully extracted and deployed in the intrinsic device. An extensive calibration was then done on the intrinsic MOSFET’s I–V and C–V models (BSIM3). Note that gate resistance plays a critical role in determining noise pa-rameters such as noise resistance , noise figure , and the drain and gate equivalent current noise generators ( and ). This requires an accurate extraction of to ensuring a reliable and accurate noise simulation, particularly in miniaturized devices. A conventional method denoted as the -method takes -parameters after two-step deembedding (open and short) and extracts from , which is assumed an appropriate approximation at sufficiently high frequency [19]. In this study, through a small signal circuit analysis on the MOSFET, we derived a new method using
-parameters rather than -parameters. In this approach,
can be expressed as for MOSFETs in the
saturation region, which is valid over a wide range of frequen-cies. The details of circuit analysis and formulas derivation is not covered in this paper. Fig. 7(a) demonstrates extracted by the -method for the 100-nm MOSFET with three different finger numbers. The results extracted using the -method are shown in Fig. 7(b). Both methods present an inverse scaling in versus . However, the -method reveals apparently smaller than the -method. The accuracy of the extracted is verified by , which has strong dependence on and can consistently justify accuracy of . Fig. 8(a) indi-cates an excellent match between simulation and measurement achieved for all three MOSFETs adopting extracted from the -method. As for using the -method, Fig. 8(b) reveals a significant deviation from measurement, particularly worse
Fig. 9. Comparison between the measurement and simulation of an in-trinsic MOSFET model for 100-nm nMOS with various finger numbers (N = 18; 36; 72). (a) g , (b) f , (c) C , and (d) C at V = 1:2 V and varyingV or I .
for the smallest device in higher frequencies. The results suggest that the proposed -method can enable an improved accuracy in extraction and contribute to a reliable and accurate noise simulation.
In contrast with , which dominates the input characteris-tics ( and ), the bulk resistance primarily influence the output characteristics ( and ). Both and have significant effect on noise resistance . The increase of raises with a constant shift over the whole frequency range, whereas the variation of limits its influence on in lower frequencies ( 5 GHz). Taking the -method based on mentioned small signal circuit analysis, was extracted
from . Moreover, in series with
were deployed for simulating drain to source inter-metal coupling effect, which has a nonnegligible effect on and . The simultaneous adoption of and enables a pre-cise fitting to and over high frequencies. In this way, a full set of parasitic RLC parameters corresponding to different finger numbers ( ) were extracted and presented in the table at-tached with Fig. 6. Note that the inverse of parasitic resistances
, , and , and the parasitic capacitance approach a linear function of . The larger , the smaller re-sistances , while the larger capacitance ex-actly match the multifinger layout.
MOSFET model accuracy was extensively verified through a comparison with I–V, C–V, -, -, and -parameters. Fig. 9 indicates a good match with measurement in terms of , , ( -parameters), and ( -parameters) over a wide range of biases or currents for 100-nm nMOS with various finger numbers ( and ). Herein, , , and increase with a finger number following a simple linear function of , whereas keeps nearly a constant value independent of . This result can be consistently explained by a simple analytical model for with the following expression
of .
The full circuit model accuracy can then be verified in terms of -parameters, noise parameters, and equivalent noise cur-rent generators. Note that an improved thermal noise model has
Fig. 10. Full circuit schematics with lossy substrate RLC networks integrated with an intrinsic MOSFET. The lossy substrate RLC parameters are listed in Table II.
been implemented in our previous work and will appear in IEEE TCAD [20]. A comprehensive short channel effects (SCEs) and parasitic resistance induced excess noise were adequately incor-porated for yielding an accurate noise simulation in nanoscale MOSFETs. Fig. 10 depicts the full circuit schematics in which the lossy substrate RLC networks are integrated with the cali-brated intrinsic MOSFET model for high-frequency -param-eter and noise simulation.
B. Two-Port -Parameters
Fig. 11 presents a good match in (magnitude and phase) between the measurement and simulation for full circuits adopting intrinsic devices with three different pads. The broad-band accuracy is proven by measurement up to 40 GHz. The phase polarity change from negative to positive was revealed in Fig. 11(e)–(g) for the full circuits of larger devices (
and ) at sufficiently high frequency. This result suggests the parasitic inductance effect and it can be eliminated for intrinsic devices via the pad and lossy substrate deembedding, shown in Fig. 10. Again, Fig. 12 demonstrates an excellent fit to the measured by the full circuit simulation incorporating lossy, normal, and small pad models and intrinsic character-istics after lossy substrate deembedding. The phase polarity change exhibited in Fig. 12(e)–(g) for the larger devices can be explained by the parasitic inductances associated with port-2 (drain pad), which follows the same mechanism proposed for corresponding to port-1 (gate pad). Besides and , a good agreement is realized for all other -parameters ( and
), as well as -parameters (not shown for brevity).
C. Pad Structure Effect on Noise Parameters
In the following, the pad structure effect on noise parame-ters will be investigated with respect to both frequency depen-dence and finger number dependepen-dence. The global noise incorpo-rating intrinsic and extrinsic noise can be simulated with a full equivalent circuit adopting the enhanced lossy substrate model and compared with measured noise. Subsequently, the intrinsic noise can be extracted through lossy substrate deembedding. A comparison with conventional noise correlation matrix deem-bedding method will be performed to verify the differences and advantages over the conventional approach.
Fig. 11. Comparison of the measured and simulatedS (mag:; phase) in the full circuit model for 100-nm nMOS (N = 18; 36; 72) adopting three different pads. Mag(S ): (a) lossy pad, (b) normal pad, (c) small pad, and (d) intrinsic devices after pad or lossy substrate deembedding. Phase(S ): (e) lossy pad, (f) normal pad, (g) small pad, and (h) intrinsic devices after pad or lossy substrate deembedding. After [17].
An improved thermal noise model [20] was implemented in the intrinsic MOSFET and integrated with the enhanced lossy substrate model for noise simulation.
Fig. 13(a)–(c) indicates the simulated global and its good agreement with measurement for full circuits adopting three pad schemes (lossy, normal, and small pads). Interestingly, the devices adopting lossy pads reveal an abnormally strong finger number dependence and nonlinear behavior with respect to frequency in Fig. 13(a), whereas the finger number depen-dence is almost eliminated and frequency dependepen-dence is re-covered to be linear for the normal and small pads shown in Fig. 13(b) and (c). The larger presented by the smaller finger number ( ) in the category of a lossy pad suggests the amplification effect through the larger noise resistance for smaller . The global is effectively reduced for devices using a normal or a small pad scheme and the enhanced lossy substrate model can accurately predict the measured pad struc-ture effect on noise. The intrinsic simulated after a lossy substrate deembedding shown in Fig. 13(d) are nearly indepen-dent of finger numbers over a wide range of frequencies up to 18 GHz. The intrinsic at V corresponding to the maximum is as low as 0.75 dB at 10 GHz and can be further suppressed to around 0.55 dB under V re-sponsible for the minimum (not shown). Note that noise
Fig. 12. Comparison of the measured and simulatedS (mag:; phase) by the full circuit model for 100-nm nMOS (N = 18; 36; 72) adopting three different pads. Mag(S ): (a) lossy pad, (b) normal pad, (c) small pad, and (d) intrinsic devices after pad or lossy substrate deembedding. Phase(S ): (e) lossy pad, (f) normal pad, (g) small pad, and (h) intrinsic devices after pad or lossy substrate deembedding
deembedding using matrix correlation method was performed simultaneously over the measured noise. The results plotted to-gether with lossy substrate deembedding in Fig. 13(d) indicate an effective suppression on the noise in the lossy pad, but re-main higher than those in normal pad after deembedding. One more obvious problem as compared to lossy substrate deembed-ding is a scattered distribution over frequencies, which leads to negative values in lower frequencies and an increase faster than a linear function in a higher frequency domain.
The pad structure effect on four noise parameters , , , and are illustrated in Figs. 14 and 15 for and , respectively, to investigate the finger number dependence of the extrinsic noise coupled through dif-ferent pads. The smallest device reveals the largest sensitivity to the pad structures with a substantial increase
in , , and for the lossy pad. The
sensitivity is significantly suppressed by increasing the finger number. The increase of mentioned noise parameters in the lossy pad becomes much smaller for the largest device with in Fig. 15(a)–(d). Note that is effectively reduced by increasing attributed to the smaller and larger , but remains nearly constant with respect to different pad schemes. The scalability and broadband accuracy of the enhanced lossy
Fig. 13. Comparison of the measured and simulatedNF by full circuit model for 100-nm nMOS (N = 18; 36; 72) adopting three different pad schemes. (a) Lossy pad, (b) normal pad, (c) small pad, and (d) intrinsic NF after a lossy substrate deembedding and comparison with correlation matrix deembedding results. After [17] and added with correlation matrix deembedding results.
Fig. 14. Measured and simulated noise parameters for 100-nm nMOS by full circuit model of lossy, normal,and small pads and comparison with intrinsic ones using lossy substrate deembedding and noise correlation matrix deembedding N = 18. (a) NF . (b)R . (c) Re(Y ). (d) Im(Y ). From [17] and added with noise correlation matrix deembedding results.
substrate model is proven by a good agreement with the mea-sured noise parameters associated with various pads, as well as finger numbers, and over a broad frequencies up to 18 GHz. The intrinsic noise parameters extracted through the lossy substrate deembedding (solid lines) indicate an effective reduction and then a recovery to a linear frequency dependence in ,
, and . measured from the devices
with a normal or small pad structure are effectively suppressed and approach that of an intrinsic device. The results suggest that pads and TML using highest metal only and smallest area, achieving the minimal and can minimize the ex-trinsic noise introduced from the lossy substrate and approach the intrinsic performance. Note that noise correlation matrix deembedding results (empty symbols) are allocated in the same plot for comparison. An undesired fluctuation over frequencies and deviation from linear distribution appeared in and
Fig. 15. Measured and simulated noise parameters for 100-nm nMOS by full circuit model of lossy, normal, small pads and comparison with intrinsic ones using lossy substrate deembedding and noise correlation matrix deembedding, N = 72. (a) NF . (b)R . (c) Re(Y ). (d) Im(Y ). From [17] and added with noise correlation matrix deembedding results.
D. Pad Structure Effect on Current Noise
Subsequently, a more extensive verification is performed on the power spectral density (PSD) of drain and gate current noises and to explore the lossy substrate effect subject to pad structures. The global current noise and can be derived from the measured noise parameters ( , , and ) and -parameters following (15)–(18) based on the noise equivalent circuit analysis for a two-port network and the application of noise correlation matrix method [21]
(15) (16) where
(17) (18) Fig. 16 presents a good match between the measurement and model for and corresponding to and with lossy, normal, and small pads, respectively. Again, the smallest device reveals a substantially larger corresponding to the lossy pad in Fig. 16(a), whereas there is little difference in for various pads in Fig. 16(b). The extrinsic noise in arising from the lossy pads is mitigated for the largest device , as shown in Fig. 16(c).
The lossy substrate effect on and can be consistently explained by (15)–(18). For the gate current noise in (15), the extrinsic noise revealed by the lossy pads just resorts to a substantial increase of referred to Fig. 14(c). Regarding the drain current noise in (16), a very minor pad structure effect on [see Fig. 14(b)] and and the dominance of by at a relatively lower frequency ( 18 GHz) explain the insignificant change of in Fig. 16(b) and (d). The intrinsic extracted through the lossy substrate deembed-ding exhibits an obviously lower value and frequency depen-dence approaching the ideal theory that is proportional to .
Fig. 16. Measured and simulatedS and S for 100-nm nMOS in a full cir-cuit model of lossy, normal, and small pads, and comparison with intrinsic noise extracted using lossy substrate deembedding and noise correlation matrix deem-bedding method.N = 18. (a) S . (b) S , N = 72. (c) S . (d) S .
As for the intrinsic compared with the global one incorpo-rating extrinsic noise, a minor change at lower frequencies, but a suppression to near a constant at higher frequencies reflects the deembedding effect on . At lower frequencies, is dominated by , which generally keeps near constant after a deembedding. Going to higher frequencies,
may take over the influence on for larger before a deem-bedding. As for the intrinsic one after a deembedding, the sub-stantial decrease of will recover the dominance of and lead to an effective suppression of to near a constant versus frequency. Note that noise correlation ma-trix deembedding results (empty symbols) are presented in the same plot for a comparison. An undesired fluctuation over fre-quencies appeared in , as well as , and deviation from a linear distribution in . Both the fluctuation and deviation in frequency dependence explain the difficulty and limitation in adopting noise correlation matrix method in noise deembedding and simulation.
Fig. 17 demonstrates the finger number dependence of and a remarkable pad structure effect. As shown in Fig. 17(a),
measured with a lossy pad reveals an abnormally small de-pendence on finger numbers and frequency dede-pendence away from the theoretical frequency dependence proportional to . As for the normal and small pads in Fig. 17(b) and (c), an ob-vious finger number dependence is recovered, but the deviation from theoretical frequency dependence still persists at higher frequencies. The intrinsic extracted using lossy substrate deembedding, as shown in Fig. 17(d), can recover both finger number dependence and frequency dependence to a normal con-dition. One more interesting observation is that lossy pad effect on and in terms of finger number dependence just goes in an opposite direction. The lossy pad causes an abnor-mally strong dependence on in (Fig. 13), whereas an abnormally weak dependence on in (Fig. 17). As a re-sult, the broadband accuracy and scalability is again certified on the current noises over a broad range of frequencies and var-ious pad structures. Again, noise correlation matrix deembed-ding results (empty symbols) are presented in Fig. 17(d) for a comparison with lossy substrate deembedding results. A severe
Fig. 17. Comparison of the measured and simulatedS in a full circuit model for 100-nm nMOS (N = 18; 36; 72) adopting different pads and compar-ison with intrinsic noise extracted by lossy substrate deembedding, as well as noise correlation matrix deembedding method. (a) Lossy pad, (b) normal pad, (c) small pad, and (d) intrinsicS after the lossy substrate and pad deembed-ding
fluctuation over frequencies and deviation from a linear distri-bution apparent in suggests the weaknesses of noise corre-lation matrix method in noise deembedding and simucorre-lation.
V. CONCLUSIONS
A broadband and scalable lossy substrate model has been de-veloped and validated over 100-nm RF MOSFETs with various finger numbers and different GSG pad structures (lossy, normal, and small pads). This enhanced lossy substrate model incor-porates substrate RLC networks distributed under the pads and TML. The exact distribution of substrate loss through the pads and TML can accurately simulate the resulted extrinsic noise in miniaturized devices over a broadband region. The physical ele-ments and introduced in the enhanced lossy substrate model consistently follow the scaling factors corresponding to the layout and 3-D topology in different pad schemes. A novel parameter extraction method was established and proven with broadband accuracy in open pad -parameters over 110 GHz. All the model parameters are scalable and can be predicted by a linear function of . In this way, the enhanced model can guide and facilitate an optimal layout in pads and TML for an effective reduction of extrinsic noise and low noise design in nanoscale MOSFETs.
For RF noise simulation and analysis, the broadband accuracy is validated by a good match with the measured -parameters up to 40 GHz, as well as noise parameters and PSD of current noises ( and ) over 18 GHz. The scalability is certified by an accurate prediction for various finger numbers in conjunction with lossy, normal, and lossy pads. A reliable intrinsic noise ex-traction can be realized using the lossy substrate deembedding method through which the intrinsic problems of conventional noise correlation matrix method can be eliminated.
As a result, this broadband and scalable lossy substrate model can facilitate an optimal design to minimizing the extrinsic noise and approaching the intrinsic device noise performance. Ulti-mately, this enhanced model can be easily deployed in general circuit simulators to substantially improve RF circuit simulation
accuracy for low-power and low-noise design in nanoscale RF CMOS technology.
ACKNOWLEDGMENT
The authors would like to acknowledge the helpful support from National Device Laboratory (NDL) for RF device mea-surement and Chip Implementation Center (CiC) for providing the RF simulation environment.
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Jyh-Chyurn Guo (M’06–SM’07) received the
B.S.E.E. and M.S.E.E. degrees from National Tsing-Hua University (NTHU), Taiwan, in 1982 and 1984, respectively, and the Ph.D. degree in elec-tronics engineering from the National Chiao-Tung University (NCTU), Hsinchu, in 1994.
For more than 19 years, she was with the semicon-ductor industry, where her major focus was on device design and VLSI technology development. In 1984, she joined the ERSO/ITRI, where she had been en-gaged in semiconductor integrated circuit technolo-gies with a broad scope that covers high-voltage, high-power, submicrometer project, and high-speed SRAM technologies, etc. From 1994 to 1998, she was with the Macronix International Corporation, where she was engaged in
high-density, as well as low-power Flash memory technology development. In 1998, she joined the Vanguard International Semiconductor Corporation, where she was the Device Department Manager for advanced DRAM device technology development. In 2000, she joined the Taiwan Semiconductor Manufacturing Company (TSMC), where she was a Program Manager in charge of 100-nm logic CMOS FEOL, high-performance analog (HPA) and RF CMOS technology development. In 2003, she joined the Department of Electronics Engineering, NCTU, as an Associate Professor. Since 2008, she has been a Full Professor with NCTU. She has authored or coauthored over 50 technical papers. She holds 19 U.S. patents in her professional field. Her current research interests cover RF CMOS and high-performance analog device design and modeling, novel nonvolatile memory technology, and device integration technologies for system-on-chip (SOC).
Yi-Hsiu Tsai was born in Tainan, Taiwan, in 1982.
He received the M.S. E.E. degree from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 2007, and is currently working toward the Ph.D. degree at the Institute of Electronics, NCTU.
His current research interests are focused on RF CMOS device characterization, modeling, and RF circuit design.
