A Fully Integrated Spread-Spectrum Clock Generator
by Using Direct VCO Modulation
Yi-Bin Hsieh, Student Member, IEEE, and Yao-Huang Kao, Member, IEEE
Abstract—A compact architecture for a fully-integrated spread-spectrum clock generator (SSCG) using voltage-controlled oscil-lator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35- m CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5% and 2% are verified and are close to the theoretical analyses. The size of the chip area is0 82 0 8 mm2 (including the loop filter) and the power consumption was 27.5 mW at 400 MHz.
Index Terms—Phase-locked loop (PLL), spread-spectrum clock generator (SSCG).
I. INTRODUCTION
T
HE electromagnetic interference (EMI) in electronic de-vices such as a PC, printer, PCI Express and SATA in-creases rapidly as the clock speed is raised. In many applica-tions, clock generators are one of the major contributors of EMI. Spread-spectrum clock generators (SSCG) are proven to be an efficient way to reduce EMI levels [1]–[7]. A SSCG is basically a phase-locked loop (PLL) with an appropriate frequency-mod-ulated output. The frequency modulation is used to spread the output spectrum. There are three kinds of modulation schemes employed in PLLs. The first type involves a change to the divider made by a sigma-delta modulator [2]–[4]. The second type in-cludes either digital manipulation of the output of a multiphase PLL or the use of a delay-locked loop (DLL)/phase interpo-lator combo on the output of a standard PLL [5]–[7]. The last type involves direct modulation of the voltage-controlled oscil-lator (VCO) in PLL [8]–[11]. The latter has the advantages of a simple circuit structure and the absence of sigma-delta modu-lator noise. But the loop bandwidth of a PLL has to be much less than the modulation frequency to allow the frequency variation of the VCO. In general, the required loop bandwidth is about one of ten times that in the modulation. The modulation frequency is typically around 30 to 50 kHz so that the loop bandwidth is around 3 to 5 kHz. This leads to a large capacitor of more thanManuscript received November 7, 2006; revised May 31, 2007 and October 22, 2007. First published February 8, 2008; last published August 13, 2008 (pro-jected). This work was supported by the National Science Council of Taiwan, R.O.C. This paper was recommended by Associate Editor B. Zhao.
Y.-B. Hsieh is with the Institute of Communication Engineering, Na-tional Chiao-Tung University Hsin-Chu, Taiwan 30050, R.O.C. (e-mail: yibin.cm93g@nctu.edu.tw).
Y.-H. Kao is with the Department of Communication Engineering, Chung-Hua University Hsin-Chu, Taiwan 300, R.O.C. (e-mail: yhkao@chu. edu.tw).
Digital Object Identifier 10.1109/TCSI.2008.918194
Fig. 1. Proposed SSCG.
10 nF in the loop filter, which becomes too large to be integrated in the chip [8], [9].
Recently, the technique of capacitance multiplication is pro-posed to eradiate this problem [9], [12]–[14]. However, in order to accommodate another charge pump to generate the triangular modulation, a floating capacitor is connected [9]. The floating capacitor in a standard CMOS process can be poly-to-poly (PIP) or metal-to-metal (MIM) and needs extra masks and process steps. It also has the area and cost penalties comparable to those of a MOS capacitor. In this paper, a modified architecture with a grounded capacitor in mixed configuration containing both a dual-path loop filter (DPLF) [12] and an extra charge-pump cir-cuit is proposed to attain a smaller size and triangular modula-tion. This method also reduces both hardware complexity and chip area. Although, a nonlinear modulation profile known as the “Hershey-Kiss” profile [1] shows a better EMI performance, its nonlinear equations make it more expensive due to a larger area and power consumption. Therefore, the linear triangular profile is adopted in this paper.
Section II describes the architecture and presents an analysis of the proposed SSCG. The CMOS circuits used in this work are presented in Section III and the measurement results are presented in Section IV. Finally, the conclusions are given in Section V.
II. PROPOSEDSSCGANDITSTHEORETICALANALYSIS
A. Proposed SSCG
The proposed SSCG is shown in Fig. 1. It consists of a phase-frequency detector (PFD), a dual-path loop filter [12] which is composed of two charge pumps and , a unity-gain buffer, two capacitors and and a resistor , a charge pump , a VCO, and a 8-bits programmable counter. The
1846 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
Fig. 2. (a) Dual-path loop filter. (b) Traditional loop filter.
and provide the dual-path charging currents and , respectively, to the loop capacitors. The provides the charging current to the grounded capacitor in order to form the triangular waveform of the control voltage . The first path composed of the and is a low-pass filter. The second path composed of the and unity gain buffer acts as an inte-grator. The voltages from these two paths are combined together so that a zero is created in transfer function. In order to obtain the multiplication effect of the capacitance , the pumping cur-rent is set at with a factor . To simplify the analysis, the higher order filtering effect of and is ignored in the following analysis. The relationship between the controlling voltage and pumping current can be easily obtained via the dual-path loop filter redrawn in Fig. 2(a). The transfer function is given as
(1)
For a comparison, the conventional second-order loop filter with only one charge pump is presented in Fig. 2(b), in which both the capacitor and the unity gain buffer are replaced by an equivalent capacitor . The corresponding transfer func-tion is given by
(2)
When compared with (1), it was found that two circuits have the same zero response under the condition of . It implies that capacitance in the former case is B times smaller than . The area of capacitor can be reduced dramatically by using this technique. In this work, . Moreover, one of terminals in is grounded. Therefore, capacitor can be realized by using the MOS capacitor. The pole in (2) is caused from and a capacitor with and in series. If
. it is almost equal to that of in (1), it is generally the case that the pole is about ten to hundred times the zero, depending on the damping ratio of the system.
Fig. 3. Block diagram with relevant noise sources.
B. Analysis of Nonideality of Dual-Path Loop Filter
The nonideality of the dual-path loop filter can be viewed in two ways: filter transfer function and phase noise. The unity gain buffer is built by an opamp, which can be modeled by the dc gain and the gain-bandwidth product . The transfer function of unity gain buffer can be expressed as
(3) where denotes the gain error and is less than 1.
By using (3) and re-calculating , one can get
(4) Equation (4) can be reduced to
(5) when . When (5) is compared to (1), it can be expected that the gain error will cause the ratio of capacitance multiplication to be higher than the expected.
With reference to phase noise analysis, the block diagram with relevant noise sources is shown in Fig. 3. Here, noises from , , the unity-gain buffer and VCO are considered and denoted as , , , and , respectively. The unity buffer is only modeled by its gain error for the worst case sce-nario and the second-order loop filter is adopted for the purpose of simplification. It should be noted that all noise sources are assumed to be white although this is only an approximate for VCO.
The noise spectral density at the PLL output is rep-resented as
(6) where , , and are the noise spec-tral densities of VCO, both charge-pump currents, and the unity gain buffer, respectively. The definition of can be found
Fig. 4. Phase noise simulation results.
in [17]. From the PLL linear model shown in Fig. 3, the transfer functions are calculated as follows:
(7) (8) (9) where is the gain of the VCO in hertz/volts,
is the gain of the PFD and CP, is the transfer function of loop filter of (5), and is value of the divider. is the noise transfer function from and and can be found using
(10) From (10) it can be seen that the noise transfer function is slightly different to the signal transfer function (5). The ca-pacitor multiplication factor in noise analysis is not B. In addition, by comparing (8) and (9), the noises from the unity gain buffer and from the VCO have the same contribution when frequency is below . The PLL phase noise simulation results are shown in Fig. 4, where the solid line uses the tradi-tional loop filter presented in Fig. 2(b). The solid line with a cross mark denoted by DPLF case1 uses the dual-path loop filter seen in Fig. 2(a) with . Finally, the dashed line with a circle mark denote by DPLF case 2 uses the dual-path loop filter shown in Fig. 2(a) with . Here, the VCO phase noise is assumed to be 100 dBc at 1-MHz offset frequency. From Fig. 4, it can be seen that the phase noise of solid line, solid line with a cross mark and dashed line with a circle mark at the offset frequency of 100 kHz are 79.83, 76.76, and 79.41 dBc, respectively. The phase noise is degraded by 3.07 dB at the 100-kHz offset frequency if unity
Fig. 5. (a) Proposed technique of triangular modulation (b) waveform ofV andV .
gain buffer noise is the same as the VCO noise, while the phase noise is only degraded by 0.42 dB if the unity gain buffer noise is one order less than the VCO noise. Therefore, it is necessary to design a unity gain buffer with a low phase noise.
In addition to the filter transfer function and the phase noise, the offset of opamp is also considered. If some offsets appear, they are the result of a voltage difference between and . But will automatically adjust to compensate for the voltage difference between and .
C. Analysis of Modulation
The realization of a triangular waveform for controlling voltage is illustrated in Fig. 5(a). The current from , which is controlled by an external pulse, is also applied to . By superposition, the transfer function between and can be expressed as
(11) By assuming that the modulation frequency is much smaller than the pole, , (11) can be further simpli-fied as
(12) Then the controlled voltage is integrated from the modula-tion current. The requested triangular signal at the input node of the VCO is created as a square wave . According to (12), the triangular voltage of modulation is easily obtained by just
1848 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
Fig. 6. Linear model of PLL with frequency modulation.
adding an extra charge-pump circuit without an additional pas-sive component. The particular third charge pump circuit com-bined with the dual-path loop filter can easily generate the trian-gular modulation and considerably reduces the chip area. Here plays an important role that it not only acts as the loop filter in PLL as indicated in [12] but also serves the integration function in triangular wave generation. Unlike [8], the proposed model does not require the parameters , , and to meet the special theory requirement , nor does it require a large capacitor.
The waveforms of and are shown in Fig. 5(b), where is the voltage at the input of the buffer and is almost the equivalent of with only a slightly phase leading. The output range of the charge pump is from to which are the ground voltage plus a saturation voltage and the supply voltage minus a saturation voltage, respectively, as shown in Fig. 5(b). This suggests that has enough headroom to generate the triangular wave. Therefore, the output swing deduced from the three charge pumps can be safely operated without distortion. In [9] with floating capacitance, the output voltage of seems to be equal to zero in steady state. Thus, extra bias circuit might be needed.
The choice of loop bandwidth is essential to achieve a uni-form spread. The modulated behaviors in the closed loop are analyzed through the linear model as shown in Fig. 6. The modu-lated voltage denoted as is applied to the input of the VCO. The instantaneous output frequency is , where is the un-modulated carrier frequency and is the frequency deviation. The transfer function from m(s) to is obtained as
(13) From (1), can be rewritten as
(14) when . By substituting (14) into (13), the following results:
(15)
Actually, its behavior is a high-pass characteristic. As in-dicated earlier, the loop bandwidth is roughly equal to
around a unity damping constant. Equation (15) can be further simplified to
(16) if the modulation frequency is much larger than the loop band-width. This means that the frequency deviation is proportional to the input amplitude with a coefficient of . By defini-tion, the feedback phase signal is
(17) In a steady state, the phase error of the PFD output is
with the assumption that the input phase signal is . To satisfy the linear operation, the phase error is limited by the following relationship:
(18) where is the limit of the linear range of the PFD. Here equals as a typical phase-frequency detector. The tri-angle waveform with a mean of zero can be written as
for
for (19) where is the amplitude and is the frequency. By substi-tuting (19) and (16) into (17), the following is obtained:
(20) under the constraint of (19) with its lower limit of 0 and its upper limit of . It can be seen that the maximum amplitude of the triangle wave is proportional to the divider value and modu-lation frequency, and is inversely proportional to the VCO gain. Accordingly, the upper bond of a peak to peak spread ratio is found as
(21) where is the center frequency of the VCO output. The distor-tion occurs if the spread ratio exceeds this limit. The upper bond is limited by the divider value and the modulation frequency, and is independent of VCO gain.
The spread ratio can be controlled by adjusting the value of . According to (12) and (21), the can be determined by using
Fig. 7. Simulation results of (a) frequency profile, and (b) spectra under dif-ferent loop bandwidth withf = 40 kHz.
Equation (22) indicates that the variation in the spread ratio comes from the process variations of , and . In this work, is about 1.05 uA for a 1.5% spread ratio with
MHz/V, kHz, pF, and MHz. Based on condition (12), the loop bandwidth is required to be much less than the modulation in order to achieve linear integra-tion. The effect of the loop bandwidth on the modulation pro-file is examined as follows. The simulated frequency deviation and suppressed spectra of a 400-MHz output signal by Matlab under different bandwidths are shown in Fig. 7(a) and (b), re-spectively. In Fig. 7(a), the frequency variation becomes non-linear (solid line) and smaller as the loop bandwidth is raised toward the modulation frequency. The simulated spread ratio is 1.47% for a 7-kHz loop bandwidth, while it is reduced to 1.21% for a 28-kHz loop bandwidth with kHz. The reason for this can be found in the fact that the PLL acts as a high-passed filter with a corner frequency at the loop bandwidth and the
Fig. 8. Simulation results of output frequency for different poles.
modulated signal is attenuated as the modulation frequency ap-proaches the loop bandwidth. The EMI reductions for 7- and 28-kHz loop bandwidths are 18.83 and 15.80 dB, respectively. The spectra level for the latter is 3.03 dB worse than that for the former bandwidth. It is suggested that the loop bandwidth should be at least five times less than modulation frequency.
D. Spurious Modulation
In addition to the requirement of a loop bandwidth, the spurious effect is also taken into account. The spurious effect is mainly caused by the mismatch of the pumping currents and the switches in the charge pump circuits. As modulated in a SSCG, the phase error of the PFD output is periodically perturbed by the triangular profile. As a result of the loop bandwidth being small, the modulation signal is not cancelled. The high frequency components of the phase error may pass through the loop filter and deteriorate the jitter. This spu-rious modulation can be suppressed by appropriately adding a pole, i.e., . The variations in output frequency under the influence of different poles are illustrated in Fig. 8. The solid and doted lines are with 0.4- and 2-MHz poles, respectively. The corresponding values of are 400 and 80 pF which both have k . It is clearly seen that except for the sweep, there exist instantaneous frequency spikes. The higher the frequency of the pole has, the greater the variation of the spike has. These undesired frequency spikes result in a poor triangular modulation profile and generate extra jitter. Accordingly, the pole is traded off between the linear modulation and spurious rejection. In this work, the pole is chosen as 0.4 MHz. Extra poles composed of and are employed to further lower spurious modulation. Here, k and pF are adopted and the pole is 1.59 MHz.
It is noted that there are many tradeoffs in frequency set-ting involving direct VCO modulation. First of all, the refer-ence clock of the PFD is chosen as the guidepost, which is the highest one in the loop and is far from the loop bandwidth. Then, the zero is traded off between capacitance area and
1850 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
TABLE I
CRITICALPARAMETERS OFPLL
Fig. 9. (a) VCO. (b) Delay cell in VCO.
Fig. 10 (a) PFD circuit. (b)CP and CP circuits. (c) CP circuit.
damping constant. The loop bandwidth is traded off between stability and modulation. Modulation is set higher than the loop bandwidth. The pole is then traded off between linear integra-tion and modulaintegra-tion spurious rejecintegra-tion. The critical parameters of the PLL are listed in Table I.
Fig. 11. Unity gain buffer circuit used in dual-path loop filter.
Fig. 12. Die photograph of the proposed SSCG.
Fig. 13. Measured VCO frequency tuning curve.
III. CMOS CIRCUITS
The circuits used in this work are briefly described next. The wide band VCO [15], which consists of the three stages of dif-ferential delay cells, is shown in Fig. 9(a). The schematic of each delay cell is shown in Fig. 9(b). A cross-coupled connection is
Fig. 14. Measured jitter of SSCG output at 400 MHz when: (a) SSC off and (b) SSC on of 1.5% spread ratio.
Fig. 15. Measured spectra of the 400-MHz output signal: (a) without modulation, (b) with 1.5% center-spread and 7-kHz bandwidth, and (c) with center-spread 1.5% and 28-kHz bandwidth.
employed to obtain full swing and sharp output waveform to re-duce the jitter. A conventional voltage to current converter and tail current source are omitted for low-voltage applications and for lower flicker noise up-conversion [15]. The PFD and charge pumps and are shown in Fig. 10(a)–(c), respec-tively. The cascoded current sources with a wide-swing bias circuit in Fig. 10(b) are employed to achieve good immunity against the power supply noise. The controlling signals of UP, UPB, DN, and DNB switches are directly fed from the outputs of PFD represented in Fig. 10(a). A unity-gain buffer is used to clamp the terminal voltages of the current sources during the zero-current pumping period. In this way, voltage glitches on the loop filter resulting from charge sharing can be eliminated [16]. The currents and of and are 25 and 0.5 uA, respectively. The current is adjusted by using an external re-sistor to match the various spread ratios.
The unity gain buffer with rail-to-rail input and output used in the dual-path loop filter is shown in Fig. 11. The driving current is designed to be twice that of to provide enough driving ca-pacity. The simple one-stage design is adopted for the low phase noise requirement discussed in part B of section II. In the mean time, the long channel devices are used for M1 through M8. The GBW is designed much larger than the poles of and
to maintain linear modulation. The load of the buffer comprises a resistor series with a capacitor; therefore, no driving stage is needed.
IV. MEASUREMENTRESULTS
The proposed SSCG has been fabricated using TSMC 0.35- m single-poly quadruple-metal CMOS process. The die photograph with its area of mm is shown in Fig. 12. The tuning sensitivity of the VCO is shown in Fig. 13 with a gain of 275 MHz/V at 400-MHz output. The VCO re-veals a good linear voltage to frequency transfer curve and has a maximum frequency of more than 500 MHz. The measured jitter with the SSC off and on is shown in Fig. 14(a) and (b), respectively. The peak-to-peak period jitter is 67 ps with the SSC off and 98 ps with it on, and with a 1.5% spread ratio. The measured spectra of the 400-MHz output signals without and with a center spread of 1.5% are shown in Fig. 15(a) and (b), respectively. The peak amplitude reduction is 16.603 dB, which is only 2.227 dB lower thans the simulation results, as shown in Fig. 7(b). For comparison, the measured result with the larger loop bandwidth of 28 kHz is shown in Fig. 15(c). The reduced peak amplitude is 13.315 dB, which is 3.288-dB deterioration
1852 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
TABLE II
PERFORMANCESUMMARIES ANDCOMPARISONWITHPREVIOUSWORKS
compared with Fig. 15(b). Thus, the effect of a higher loop bandwidth is clearly verified.
Table II summarizes the performances of the proposed SSCG and compares them with the others. The power consumption is only 27.5 mW and this is much lower than for the previous models in [8] and [9] with a similar frequency due to the benefits of full integration. The total capacitor used here
is only 1.01 nF while it is 352.47 nF for the one in [8] and 78.959 nF for the one in [9]. Hence, the advantage of capacitor multi-plication is clearly evident. The added jitter is in the proposed SSCG is only 31 ps while it is 127 ps in [2] due to the larger sigma-delta noise.
V. CONCLUSION
In this work, a new 400-MHz SSCG which adopts a direct VCO modulation is presented. By using a dual-path loop filter, the capacitance of the low-frequency loop filter is so signifi-cantly reduced such that full integration becomes possible. At the same time, a triangular modulation of spectral spread is easily obtained by the appropriate inclusion of both an extra charge-pump circuit and an isolated buffer in the loop filter. The determination of zero, loop bandwidth, modulation frequency, pole, and comparison clock are carefully studied. The chip is fabricated using a 0.35- m standard CMOS process. The mea-surement results are mostly as predicted.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Imple-mentation Center and the National Science Council of Taiwan, R.O.C., for chip implementation and financial support, respec-tively.
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Yi-Bin Hsieh (S’07) was born in 1973, Taiwan, R.O.C. He received the B.S. degree from the National Taipei Institute of Technology, Taipei, Taiwan, R.O.C., in 1993, the M.S. degree from the Institute of Communication Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C., in 1998, where he currently is working toward the Ph.D. degree.
His research interests include mixed-mode signal processing integrated design, and clock and data re-covery circuit design.
Yao-Huang Kao (M’76) was born in Tainan, Taiwan, R.O.C., in 1953. He received the B.S., M.S., and Ph.D. degrees in electronic engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C., in 1975, 1977, and 1986, respectively.
From 1986 to 2006, he was a member of the De-partment of Communication Engineering at National Chiao-Tung University, where he was also appointed to a full professorship. In 1988, he was a Visiting Scholar researching nonlinear circuit at the Univer-sity of California, Berkeley. In the following year he was at Bell Communication Research (Bellcore). Currently he is a Professor in the Department of Communication Engineering, Chung-Hua University, Hsin-Chu, Taiwan, R.O.C. His current research interests involve nonlinear dynamics and chaos, high speed optical communications, and microwave and RF circuit designs. He is also a technical consultant for RF circuits in many industrial com-panies and government institutes.
