行政院國家科學委員會補助專題研究計畫
█ 成 果 報 告
□期中進度報告
單封裝系統訊號完整性之前瞻整合研究(3/3)
計畫類別：□ 個別型計畫 █ 整合型計畫
計畫編號：NSC 96－2221－E －110－029
執行期間：
95 年 8 月 1 日至 96 年 7 月 31 日
計畫主持人： 洪子聖
共同主持人：
計畫參與人員： 黃建祥、魏祖強
成果報告類型(依經費核定清單規定繳交)：□精簡報告 █完整報告
本成果報告包括以下應繳交之附件：
□赴國外出差或研習心得報告一份
□赴大陸地區出差或研習心得報告一份
□出席國際學術會議心得報告及發表之論文各一份
□國際合作研究計畫國外研究報告書一份
處理方式：除產學合作研究計畫、提升產業技術及人才培育研究計畫、
列管計畫及下列情形者外，得立即公開查詢
□涉及專利或其他智慧財產權，□一年□二年後可公開查詢
執行單位：國立中山大學電機系
中 華 民 國 97 年 9 月 30 日
中文摘要
本整合型計畫從事單封裝系統訊號完整性前瞻性研究，涵蓋寬頻模型化、射頻積體電
路封裝效應、內埋被動式元件整合、電源分佈網路分析、以及時域有限差分之全波電磁模
擬等幾項研究主題。共分為四項子計畫，各子計畫成果摘要如下：
子計畫一：單封裝系統射頻模組元件設計資料庫之研究與建立
在現代的射頻單封裝系統模組的研究發展中，在多層封裝基板內埋被動式元件可有效
縮小模組體積，並能提升模組整體電性性能。子計畫一從事在多層封裝基板中設計各種三
維造型高品質因子內埋式電感器、電容器等基礎微波集總元件，並以首創修正
T 型等效電
路架構，由頻域散射參數直接萃取方法建立寬頻模型資料庫。另一項研究成果在將封裝效
應具體納入射頻積體電路的設計考量中，配合微波網路萃取方法，建立封裝互連及接地效
應之寬頻模型資料庫。
子計畫二：單封裝系統高速互連結構設計資料庫之研究與建立
隨著系統級封裝或系統單晶片時脈速度快速的增加與互連結構佈局密度的增高，在相
鄰互連結構間的串音雜訊 對於電路系統訊號完整性的影響也日益增加。正確地得到多導體
高速耦合互連結構的等效電路模型來預測其暫態響應，並執行整個系統的訊號完整性模擬
是相當重要的。子計畫二的研究成果包括提出一種新的時域演算法，架構在多維度逐層萃
取技術的基礎上，只需單一激發源之時域暫態響應，就可建立耦合互連結構之等效寬頻模
型。另一項研究成果在針對系統級封裝中常見的差動貫穿孔，將量測所得時域暫態響應以
最佳化的有理函數方法處理，再配合集總元件萃取技術建立寬頻模型資料庫。
子計畫三：單封裝系統被動元件整合與屏蔽設計
單晶片系統因為需要增加額外的光罩，去整合數位邏輯、記憶體與類比功能在特別的
基材上，這會導致其成本大幅的提升，所以單封裝系統在現階段仍是被廣泛使用的通訊模
組解決方案。在實現單封裝系統技術中被動元件整合技術是模組縮小化的重要關鍵，子計
畫三研究成果包括單封裝系統之天線、多層基板濾波器及巴倫器、表面聲波元件、螺線管
電感器等被動元件與其屏蔽結構設計，並利用缺陷接地面、超穎材料、電磁能隙等方法來
同時增進被動式元件之效能與隔絕度。
子計畫四：單封裝系統訊號完整性之電磁模擬方法研發
單封裝系統內，混和數位、類比、及射頻訊號是常見的應用，由於混和訊號系統的電
源分佈平面通常是不規則狀，使用傳統的時域有限差分方法分析外型不規則的金屬面時，
如果採用階梯狀的方式近似，會有準確度不高的問題，當然縮小空間網格的尺寸可以減小
誤差，但相對的亦必須使用較長的計算時間。子計畫四研究成果包括利用適形時域有限差
分法，配合平面型電路特性的演算法，去準確分析不規則狀的電源分佈平面。另一項研究
成果在利用時域有限差分方法結合模型階數減縮法，建立電源分佈網絡的寬頻模型。
關鍵詞：單封裝系統、訊號完整性、寬頻模型、射頻積體電路封裝效應、被動元件整合、
電源分佈網路、時域有限差分
英文摘要
This project was devoted to the advanced coordinated research on system-in-package (SiP)
signal integrity (SI). The main research results included the broadband component library, RFIC
package effects, embedded passives integration, power distribution network analysis, and FDTD
electromagnetic simulation. The research results in each subproject are summarized as follows.
Subproject 1: In the modern SiP design for miniature RF modules, the development of passive
library is recognized as crucial to the success of the EDA-based approach. This subproject took
up the design and modeling techniques for the library development of embedded high-Q 3-D
inductors and capacitors. The proposed modified-T equivalent circuits using S-parameter
extraction can provide the broadband models for these embedded 3D components. This
subproject also investigated and modeled the package effects on RFICs for wireless applications.
The equivalent circuit extracted from S-parameters was used to model the package interconnect
and grounding effects over a large frequency range.
Subproject 2: With rapidly increasing clock rate and denser interconnect layout for SiP or system
on chip (SoC), crosstalk noise between neighboring interconnects is a critical factor to degrade
the signal integrity of circuit systems. It’s important to get accurately the equivalent models of
crosstalk effect for multi-conductor high speed interconnects to predict transient behavior and
perform overall system-level SI simulation. In this subproject, a time-domain approach was used
to synthesize the broadband SPICE-compatible macromodels of the coupled interconnects using a
multi-dimensional layer-peeling technique based on only one excitation source. Another research
results focused on the broadband models of the differential via in the SiP. The step responses of
the differential via were solved in terms of rational functions in the optimum pole-residue forms.
Using a systematic lumped-model extraction technique, all the pole-residue rational functions can
transfer into a corresponding broadband SPICE model composed by the R-L-G-C series-parallel
connection.
Subproject 3: The SoC movement is ambushed by the cost of additional mask layers needed to
marry digital logic with memory and analog function on one specific and optimum substrate.
Therefore, the SiP is widely used in the current communication modules that generally need more
functionality, better performance, low cost, and more integrity. The critical designs in a viable
SiP technology include integrated passive elements, shielding approach, and embedded RF
function including high-performance filters, baluns, and integrated antenna technologies. For this
reason, this subproject designed and implemented the embedded antennas, multilayer filters and
baluns, SAW devices, solenoid inductors, and shielding structures for wireless SiP applications.
Furthermore, this subproject used defected ground plane, metamaterial and electromagnetic
bandgap techniques to enhance the performance and isolation properties for the designed passive
components.
Subproject 4: SiP is an application of mixed signal between digital, analog, and RF subsystems.
Since the power plane of mixed-signal system is typically irregular, conventional Yee’s FDTD
scheme usually renders large error with staircase approximation. Reducing the grid size alleviates
the problem with the added cost of longer computation time. Therefore, the subproject developed
a numerical method based on the conformal FDTD method. The method took into account the
characteristics of planar circuits in order to accurately analyze irregular shape power distribution
plane. This subproject also developed the macromodel of the power distribution network based
on the model order reduction (MOR) method.
Keywords: System-in-Package (SiP), signal integrity, broadband SPICE model, RFIC package
effects, embedded passives integration, shielding structure, power distribution network, full-wave
electromagnetic simulation
報告內容
ㄧ、前言與目的
單封裝系統技術是根基在現有的
IC 製程技術、封裝技術、被動式元件技術、印刷電路
板技術以及表面粘著元件技術，在台灣皆有深厚的產業基礎，此為發展單封裝系統之有利
條件。單封裝系統設計業者需能充分整合上述不同製程特性以對系統做出最佳化設計，所
需知識遠比只做
IC 設計更為廣泛。本計畫研究目標在發展單封裝系統中有關於縮小化設計
以及高頻/高速訊號完整性分析之關鍵性 IP，讓系統製造業者在完全不具備這方面知識的情
況下也能達成有效率的量產目標。
二、文獻探討
目前單封裝系統技術發展趨勢可分為基板、互連、被動元件整合以及縮小化等四大方
向[1]-[6]，分別探討如下：基板技術可概分為壓層基板、薄膜製程基板以及厚膜製程基板三
大類[7]-[13]，壓層基板常用如 FR4、BT 以及軟板等有機基板，薄膜製程基板則以氧化鋁、
玻璃、及高阻值矽、砷化鎵等基板為代表，厚膜製程基板則以低溫共燒陶瓷基板最為大家
所熟悉。分析單封裝系統各種基板技術彼此競爭之優勢與劣勢，其中壓層基板最大優勢是
成本低，但損耗大及熱傳導不佳。低溫共燒陶瓷基板最大優勢在於層數多，可有較大往垂
直方向的佈局空間，並且容易內埋被動式元件，但因需要經過共燒過程，基板會收縮而限
制其佈線密度且所用金屬材料損耗偏高。而一般薄膜基板則有高佈線密度、低損耗以及熱
傳導較佳等特性，但製造成本高。近年來隨著材料科技的進步，以上所述各基板製程技術
已逐漸往改善缺點的方向邁進，如
FR4/BT 基板增添 PTFE 材料及軟板增添 LCP 材料可使
壓層基板損耗大幅降低；低溫共燒陶瓷基板在共燒過程中已發展出無收縮性製程並可採用
銅金屬材料，可大幅提高佈線密度並且降低金屬損耗；薄膜基板製程良率也逐漸上升而導
致成本下降，並且藉由
SiC 等高楊氏係數基板技術的開發，佈線密度已不亞於先進的半導
體製程技術。
互連技術主要區分鎊線及覆晶兩種類型，相較於傳統的鎊線技術，覆晶技術擁有較短
的電性及散熱路徑，並適合陣列式高腳數密度封裝，但成本較高。為了更加縮短電性及散
熱路徑，最新的覆晶技術已進一步發展出無銲錫凸塊基板封裝技術[14]，可直接將晶片覆晶
於增層(build up)基板中空腔內，周圍再灌封裝模膠，而晶片與增層基板盲孔之間直接電性
接觸，晶片上無須再長銲錫凸塊。另外，晶圓級封裝[15]直接在晶圓表面增加介質層作重佈
線工作及長銲錫球後，就可直接將晶片表面粘著於電路板中，之間無須再用覆晶封裝基板。
被動元件整合技術主要是將被動元件納入於封裝結構體中，可有效減少系統使用離散
被動元件的數量，縮小系統體積並提升系統性能。目前可歸類下列幾項主要技術：
(a) 在封
裝基板上表面粘著離散被動元件；(b) 在封裝基板上內埋圖案(patterned)被動元件，包括螺
旋電感器、濾波器與巴倫器等[16],[17]； (c) 薄膜製程技術製作之積體化被動元件(Integrated
Passive Devices, IPD)[18],[19]，並利用鎊線及覆晶技術與晶片相連接。目前在壓層封裝基板
上較難內埋電阻與電容元件，因而被動元件整合度較差。但最新的發展趨勢則包括在在壓
層基板上內埋損耗性及高
k 值介質材料，使得內埋電阻與電容元件得以實現[20],[21]。另
外，傳輸線及被動元件整合於軟板中，可以提供適形(conformal)方式之訊號傳輸，有利於
應用在不規則的單封裝結構體中[22]。圖一為目前常見的無線單封裝系統架構，封裝體所整
合被動元件主要為表面粘著式離散元件，加上少許內埋螺旋電感器。
RFIC 0402 Capacitor 0201 ResistorEmbedded Spiral Inductors RFIC 0402 Capacitor
0201 Resistor
Embedded Spiral Inductors
Build up substrate Integrated passive device Si carrier RF+BB chip Molding compound Si carrier Balun BPF Antenna Bump Bondwire Through silicon via Plated through hole Buried via Solder ball
圖一 現有無線單封裝系統架構 圖二 先進無線單封裝系統架構
縮小化技術是單封裝系統的重要優勢項目，因為在採用晶圓級封裝[15]與晶片堆疊[23]
等封裝技術後，面積上可以比單晶片系統更小，而且在被動元件的整合上也比單晶片系統
有更大的彈性與更佳的性能。最新縮小化的技術發展中，特別注重內埋天線設計問題
[22],[24]，因為天線受限於輻射效率的要求，所需物理尺寸遠大於其他被動元件，而且其性
能又容易被其他元件所干擾，以致於一般單封裝系統設計，鮮見整合天線於單封裝結構體
的例子。另外，配合縮小化的要求，多晶片及被動元件在以高密度整合於單封裝結構體中
時，電磁干擾與散熱現象會變得相當嚴重，需要發展內埋屏蔽與散熱結構等設計技術[25]。
圖二為未來無線單封裝系統架構，採用
IPD 與內埋天線、濾波器與巴倫器等先進技術，
能高密度整合被動元件；晶片採用堆疊技術，能有效縮小系統面積；發展垂直方向互連技
術，如各式連通柱等，可以縮短訊號傳輸路徑來提高電性性能。本整合型計畫是基於各子
計畫先前研究成果以及國外重要代表文獻，包括頻域[26]-[30]及時域[31]-[33]模型化方法、
封裝基板天線設計[34]-[42]、適形時域有限差分法[43]-[45]、射頻積體電路封裝模型
[46]-[50]、內埋被動式元件設計[51]-[57]、模型階數減縮法[58],[59]、差動貫穿孔模型
[60]-[62]、結合巨集與集總模型之時域有限差分法[63]等。
三、研究方法與結果討論
本整合型計畫應用於單封裝系統之幾項研究成果，包括頻域寬頻模型化方法、時域寬
頻模型化方法、時域有限差分電磁模擬方法、射頻積體電路封裝效應、內埋被動式元件與
屏蔽結構整合設計、覆晶封裝匯流排寬頻巨集模型、電源分佈網路寬頻巨集模型、貫穿孔
寬頻等效模型，綜合敘述其研究方法與討論如下：
1. 第一年研究成果
在頻域寬頻模型化方法的研究上，著力於多層封裝基板內設計各種高
Q 值內埋被動元
件並建立寬頻模型資料庫。在多層封裝基板的選擇上，包括以薄膜技術為主的矽及玻璃基
板，以厚膜技術為主的低溫共燒陶瓷基板，及以壓層板為主的有機及軟性基板等。在被動
元件設計上包括各種三維造型之內埋電感器與電容器，並擴及三維造型之濾波器與巴倫器
等設計。在元件模型化研究上，則以修正
T 等效電路為基礎建立寬頻等效電路模型，如圖
三之電感器模型化實例，圖四顯示模型化散射參數結果可超越傳統
PI 模型等效電路數倍以
上頻寬。
在時域寬頻模型化方法的研究上，發展出一種新的時域演算法，架構多維度逐層萃取
技術的基礎上，可針對多導體耦合結構來獲取其
SPICE 相容寬頻巨集模型。這種演算法的
優點在於只需單一激發源即可完成。分別在每個訊號輸入端激發一測試訊號並記錄在各個
端點所得到的時域響應波形，代入所提出的演算法裡，即可完成一個以傳輸線導向的等效
寬頻模型。同時，所建構模型的每一元件都是處在一個被動模態中，故此模型同時具備有
穩定性與被動性。
在天線與屏蔽結構的整合設計上，為了要增加天線的頻寬與減少接地平面的需求尺寸
和接點損耗，在低溫共燒陶瓷基板中設計垂直饋入的後空腔型平面天線來符合所需，並利
用
HFSS 與時域有限差分來設計與分析天線的性質，包括頻寬與場形等。天線與系統電路
間的屏蔽結構會影響到天線本身的效能，因此屏蔽的結構在設計天線時予以一併考量，主
要利用電磁能隙方法來降低屏蔽結構對天線效能的影響，並採用超穎材料技術增進天線性
能。
在全波電磁模擬方法的研究上，主要是發展時域有限差分方法，以三維全波分析的方
式，從封裝基板層級的電源品質著手，進而擴展到晶片內的切換雜訊分析。由於電源分佈
平面典型的是不規則狀，使用傳統的時域有限差分方法分析外型不規則的金屬面時，如果
採用階梯狀的方式近似，會有準確度不高的問題，當然縮小空間網格的尺寸可以減小誤差，
但相對的亦必須使用較長的計算時間。本計畫發展出以適形時域有限差分法為基礎，能準
確地分析不規則狀的電源分佈平面。
Metal Layer 1 Metal Layer 2 Metal Layer 3 Metal Layer 4 Plated Through Hole
nH 1.58 2.20nH fF 327 nH 1.51 fF 163 nH 1.10 Ω k 5.60 Ω 0.359 0.392Ω Ω 1.70 fF 68.2 11.4Ω 1.44nH fF 19.9 17.5Ω 1.64nH
圖 三 壓 層 封 裝 基 板 內 埋 螺 旋 電 感 器 與 等 效 修 正 T 模 型
0 5 10 15 20 Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0 M ag n it u d e o f S21 ( d B )Expanded Modified-T Model PI-Section Model Measurement
0 5 10 15 20 Frequency (GHz) -180 -120 -60 0 60 120 180 P h as e o f S21 ( d eg re e)
圖 四 模 型 化 與 量 測 散 射 參 數 之 比 較
2. 第二年研究成果
在射頻積體電路封裝效應的研究上，重心在將封裝效應具體納入射頻積體電路的設計
考量中，主要研究的封裝種類包括無引線晶片載體封裝與覆晶型球陣列封裝。主要研究成
果包括封裝效應對低雜訊放大器、混波器、正交調制器等射頻積體電路的影響，實驗與模
型所驗證的射頻參數則包括增益、雜訊指數、三次交叉點、調制準確度等。
在內埋濾波器元件與屏蔽結構的整合設計上，是以內埋電感器與電容器為基礎，設計
出應用於無線通訊系統的縮小化帶通濾波器，圖五及圖六分別顯示設計實例與模擬及量測
散射參數之比較。研究中發現被動元件與系統電路間會產生嚴重的耦合問題，因此，利用
缺陷接地面與電磁能隙方法設計屏蔽結構，能有效抑制耦合現像並降低對帶通濾波器性能
的影響。
在匯流排寬頻巨集模型的建立上，是以時域模型化方法為基礎，針對傳輸線彎角在系
統級封裝中所造成的的影響，建立寬頻等效電路模型，並利用實驗以及時域有限差分法電
磁模擬加以驗證。模型化成果包括帶有
45 或 90 度彎角的訊號匯流排，匯流排的導體數目
可能為
8、16 或 32 條。模型化、電磁模擬與實驗結果皆能相互符合並顯示此彎角結構的寄
生效應會隨著時脈速度的增快而更加明顯。圖七及圖八分別顯示一匯流排模型化實例與其
時域響應之比較。
在電源分佈網路寬頻巨集模型的建立上，主要是利用適形時域有限差分法，配合模型
階數減縮法，研發電源分佈網絡的寬頻模型。由於準確的寬頻模型必須納入多導體傳輸線
不連續結構之等效電路，這會使得整體電源分佈網路的等效電路模型過於龐大，形成計算
資源很大的負擔。故在本計畫研究中，電源分佈網路內之多導體傳輸線加上連通柱、導線
跨接處等不連續結構，是以一階數遠小於原有系統自由度的巨集模型所取代，巨集模型的
階數縮減是透過
Pade 近似法配合 Lanczos 或 Arnoldi 演算法，以逼近原有系統之響應而達
成，但是仍然能維持原結構重要的物理特性，使得巨集模型在寬頻帶範圍內具備高準確度。
Plated through hole Metal 1 Metal 2 Metal 3 Metal 4 Plated through hole Metal 1 Metal 2 Metal 3 Metal 4 Plated through hole Metal 1 Metal 2 Metal 3 Metal 4
圖五 壓層封裝基板內埋帶通濾波器
0 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) -100 -80 -60 -40 -20 0 M ag n it u d e o f S2 1 ( d B ) Equivalent circuit HFSS Measurement 0 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) -20 -15 -10 -5 0 M ag n it u d e o f S1 1 ( d B ) Equivalent circuit HFSS Measurement圖六 內埋帶通濾波器電磁模擬散射參數與量測結果之比較
圖 七 多 導 體 耦 合 結 構 及 等 效 傳 輸 模 型
圖 八
模 型 化 與 時 域 有 限 差 分 模 擬 時 域 響 應 之 比 較
3. 第三年研究成果
在射頻單封裝系統模組的設計上，是以高性能縮小化之射頻單封裝系統為設計目標，
研製應用於無線區域網路及第三代行動通訊系統之射頻電路模組，包括高平均效率發射機
與高整合度傳收機模組等成果，並能驗證所建立元件資料庫對模組最佳化設計的成效。
在差動貫穿孔寬頻等效模型的建立上，由於差動貫穿孔在高時脈的趨勢下已經成為一個
主要的訊號不連續面，可能會造成串音、反射或是接地彈跳等訊號品質上的問題。本計畫
提出新的時域模型化方法，藉由實域反射儀量測或時域有限差分模擬所得的時域波形，將
差動貫穿孔轉換成一個以三模組所組成的等效寬頻
π 模型。主要的方法是利用矩陣束法將
量測所得的步階響應轉換成有理函數表示式，再配合雙埠
ABCD 矩陣轉換，π 模型的三模
組即可以最佳化的極與餘數的有理函數形式表示。最後再利用集總元件萃取技術，將此三
模組的有理函數分別轉換成相對應的
R-L-G-C 串並聯形式的集總電路模型。
在內埋被動元件模組與屏蔽結構整合設計
---設計出應用於無線通訊射頻前端的多層縮
小化巴倫器與屏蔽結構，此屏蔽結構能有效降低系統電路對巴倫器平衡性的影響。除此之
外，本計畫前期所研究的天線，帶通濾波器則與巴倫器同時整合設計，並綜合利用缺陷接
地面、電磁能隙及超穎材料方法發展出更為完整的屏蔽結構。
在單封裝系統電磁模擬上，則整合時域有限差分電磁模擬方法、電源分佈網絡的寬頻
巨集模型、多導體耦合互連結構的寬頻巨集模型，與貫穿孔寬頻集總電路模型，發展出對
單封裝系統整體訊號完整性的
hybrid 電磁模擬技術。
四、計畫成果自評
本整合型研究計畫三年研究成果
2006 年迄今所發表的 SCI 期刊論文詳列於后，共有
34 篇，所發表的 EI 國際會議論文超過 40 篇，成果頗為豐碩。
本整合型計畫研究所發表期刊論文(SCI/EI)
[1] J.M. Wu, F.Y. Han, T.S. Horng, and J. Lin, “Direct-conversion quadrature modulator MMIC design with a new 90 degrees phase shifter including package and PCB effects for W-CDMA applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, pp. 2691-2698, Jun. 2006.
[2] J.K. Jau, Y.A. Chen, T.S. Horng, and J.Y. Li, “Envelope following-based RF transmitters using switching-mode power amplifiers,＂ IEEE Microwave and Wireless Components Letters, vol. 16, pp. 476-478, Aug. 2006.
[3] F.Y. Han, J.M. Wu, and T.S. Horng, “A rigorous study of package and PCB effects on W-CDMA upconverter RFICs,＂ IEEE Transactions on Microwave Theory and Techniques, vol. 54, pp. 3793-3804, Oct. 2006.
[4] Y.S. Tsai and T.S. Horng, “A broadband single-stage equivalent circuit for modeling LTCC band-pass filters,＂ IEEE Transactions on Microwave Theory and Techniques, vol. 54, pp. 4412-4421, Dec. 2006.
[5] C.Y. Pan, T.S. Horng, W.S. Chen, and C.H. Huang, “ Dual wideband printed monopole antenna for WLAN/WiMAX applications,＂ IEEE Antennas and Wireless Propagation Letters, vol. 6, pp. 149-151, Jun. 2007. [6] C.J. Li, C.T. Chen, T.S. Horng, J.K. Jau, and J.Y. Li, “High average-efficiency multimode RF transmitter using a hybrid quadrature polar modulator,＂ IEEE Transactions on Circuits and Systems II, vol. 55, pp. 249-253, Mar. 2008.
[7] C.J. Li, C.T. Chen, T.S. Horng, J.K. Jau, J.Y. Li, and D.S. Deng, “HQPM-based transmitter with digital predistorter for simultaneous enhancement of ACPR and PAE,＂ IET Microwaves, Antennas & Propagation, accepted, 2008.
[8] H. L. Su and K. H. Lin, “Design of an anisotropic quarter-wave polarizer without insertion loss caused by mismatch,” IEE Proc. Microw. Antennas Propag., vol. 153, no. 3, pp. 253–258, June 2006.
[9] K. Y. Lin and K. H. Lin, “Study of sacrificial electrode with fractal concept on SAW pattern for ESD protection using FDTD,” IEEE Microwave Wireless Compon. Lett., vol. 16, no. 5, pp. 311–313, May 2006.
[10] M. H. Chang, K. H. Lin, J. W. Huang, and A. K. Chu, “On-chip solenoid inductors with high quality factor for high frequency magnetic integrated circuits,” IEEE Microwave Wireless Compon. Lett., vol. 16, no. 4, pp. 203–205, April 2006.
[11] C. A. Shen and K. H. Lin, “A broadband internal planar monopole antenna for mobile phone,” Microwave Opt. Technol. Lett., vol. 48, no. 4, pp. 768–769, April 2006.
[12] B. C. Liu, K. H. Lin, and J. C. Wu, “Analysis of hyperbolic and circular positioning algorithms using stationary signal strength difference measurements in wireless communications,” IEEE Trans. Vehicular Technology, vol. 55, no. 2, pp. 499–509, March 2006.
[13] C. C. Chou, K. H. Lin, and H. L. Su, “Broadband circularly polarized cross-patch-loaded square slot antenna,＂ Electron. Lett., vol. 43, no. 9, pp. 485–486, April 26, 2007.
[14] H. L. Su and K. H. Lin, “Axial ratio bandwidth enhancement for quarter-wave polarizer using a genetic algorithm,＂ IEEE Antennas Wireless Propagat. Lett., vol. 6, pp. 47–50, 2007
[15] B. C. Liu and K. H. Lin, “ Distance difference error correction by least-square for stationary signal-strength-difference-based hyperbolic location in cellular communications,＂ IEEE Trans. Veh. Technol., vol. 57, no. 1, pp.227–238, Jan. 2008.
[16] B. C. Liu and K. H. Lin, “Wireless location uses geometrical transformation method with single propagation delay,＂ accepted to appear in IEEE Trans. Veh. Technol., May 2008.
[17] H. F. Chen, M. Y. Lin and K. H. Lin, “A V-Shaped edge-groove design for a finite ground plane to reduce pattern ripples of a monopole,＂ accepted to appear in IEEE Antennas Wireless Propag. Lett., 2008.
[18] S. L. Chen and K. H. Lin, “Characterization of RFID strap using single-ended probe,＂ accepted to appear in IEEE Trans. Instrumentation & Measurement, 2009.
[19] B. C. Liu and K. H. Lin, “SSSD-based mobile positioning: on the accuracy improvement issues in distance and location estimations,＂ accepted to appear in IEEE Trans. Veh. Technol., 2009.
[20] C. C. Wang, C. W. Kuo., and T. L. Wu, “A time-domain approach for extracting broadband macro-pi models of differential via holes,” IEEE Trans. on Advanced Packaging, vol. 29, pp. 789-797, Nov. 2006.
[21] C.W. Kuo and C.C. Wang, “Scheme to process arbitrary microwave devices in FDTD,” Electronic Letters, Vol. 42 No. 22, pp. 1287 - 1288, Oct. 2006.
[22] C.C. Wang and C.W. Kuo , “An efficient scheme for processing arbitrary lumped multiport devices in the finite-difference time domain method,＂ IEEE Trans. Microw. Theory Tech., Vol. 55, No. 5, pp. 958-965, May 2007. [23] H. H. Su and C. W. Kuo, “Efficient generation of FDTD subcells using Krylov subspace technique to the wave equation,＂ IEEE Microw. and Wireless Compon. Lett., Vol. 17, No. 4, pp. 280-282, Apr. 2007.
mushroom-structure based left-handed materials,＂ IET Microwaves, Antennas & Propagation, Vol. 1, pp. 100-107, Mar. 2007.
[25] C.W. Kuo, S.Y. Chen, M.H. Chen, C.F. Chang, and Y.D. Wu, “Analyzing multilayer optical waveguide with all nonlinear layers,＂ Opt. Express, Vol. 15, No. 3, pp. 2499-2516, Mar. 2007.
[26] C.W. Kuo, C.F. Chang, M.H. Chen, S.Y. Chen, and Y.D. Wu, “A new approach of planar multi-channel wavelength division multiplexing system using asymmetric super-cell photonic crystal structures,＂ Opt. Express, Vol. 15, No. 1, pp. 198-206, Jan. 2007.
[27] S. Sun, D. Pommerenke, J. Drewniak, K. Xiao, S.T. Chen, and T.L. Wu, “Characterizing package/PCB PDN interactions from a full-wave finite-difference formulation,” IEEE International Symposium on Electromagnetic, pp. 550-555, 2006.
[28] C.C. Wang, C.W. Ku, C.C. Kuo, T.L. Wu, “A time-domain approach for extracting broadband macro-π models of differential via holes,” IEEE Transactions on Advanced Packaging, vol. 29, No. 4, pp. 789 - pp. 797, Nov. 2006. [29] T.L. Wu and S.T. Chen, “A photonic crystal power/ground layer for eliminating simultaneously switching noise in high-speed circuit,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 8, pp. 3398 - 3406, Sept. 2006.
[30] T.L. Wu and S.T. Chen, “An electromagnetic crystal power substrate with efficient suppression of power/ground plane noise on high-speed circuits,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 7, pp. 413 - 415, Jun. 2006.
[31] T.L. Wu and T.K. Wang, “Embedded power plane with ultra-wide stop-band for simultaneously switching noise on high-speed circuits,” Electronic Letters, vol. 42, no. 4, pp. 213 - 214, Feb. 2006.
[32] T.K. Wang, S.T. Chen, C.W. Tsai, S.M. Wu, J. J. Drewniak, T.L. Wu, “Modeling Noise Coupling Between Package and PCB Power/Ground Planes with an Efficient 2D-FDTD/Lumped Element Method,” IEEE Transactions on Advanced Packaging, Vol. 30, pp. 864 - pp. 871, Nov. 2007.
[33] W.T. Liu, C.H. Tsai, T.W. Han, T.L. Wu, “An Embedded Common-mode Suppression Filter for GHz Differential Signals Using Periodic Defected Ground Plane,” IEEE Microwave and Wireless Components Letters, Apr. 2008 [34] T.K. Wang, T.W. Han, T.L. Wu, “A Novel Power/Ground Layer Using Artificial Substrate EBG for Simultaneously Switching Noise Suppression,” IEEE Transactions on Microwave Theory and Techniques, 2008, accepted.
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