Capacitance Tolerance in 0.18
m CMOS Technology
Chia-Ming Tsai, Member, IEEE
Abstract—By combining an appropriate differential-sensing
scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the negative impedance compensation is employed to enhance the gain-bandwidth product. The IC is shown to be tolerant of ESD protection circuit with 0.5 pF equiva-lent capacitance at the differential inputs. While connected to an InGaAs PIN photodiode exhibiting 0.8 pF equivalent capacitance, the implemented IC has achieved a differential transimpedance gain of 3.5 k and a 3 dB bandwidth of 1.72 GHz. At a data rate of 3 Gb/s, the measured dynamic range is from 20 dBm to
+0 dBm at a bit-error rate of 10 12with a 231 1 pseudorandom
test pattern. The negative impedance compensation is shown to achieve enhancement factors of 4.5 dB and 520%, respectively, for transimpedance gain and 3 dB bandwidth. The IC totally consumes 40 mW from a 1.8 V supply.
Index Terms—Negative impedance compensation, optical
re-ceiver, transimpedance amplifier.
I. INTRODUCTION
F
OR optical communications, the optical receiver front-end plays an important role in determining the dynamic range of the whole network. A typical optical receiver front-end con-sists of a photodiode (PD), a transimpedance amplifier (TIA) and a limiting amplifier (LA). Nowadays, most commercial products have been connected to off-chip PDs fabricated in III-V compound semiconductor technology to achieve high bandwidth and high sensitivity simultaneously. To guarantee acceptable production yield, appropriate on-chip ESD protec-tion circuit must be included in the TIA design. Inevitably, both the PD and the ESD protection circuit may contribute significant input capacitances to the TIA. For multi-gigabit applications, generally the PD equivalent capacitance lies between 0.5 pF and 1 pF. Typically, the equivalent capacitance of the ESD protection circuit lies in sub-pF range. It has beenManuscript received January 24, 2009; revised June 17, 2009. Current ver-sion published September 28, 2009. This paper was approved by Associate Ed-itor Andreas Kaiser. This work was supported in part by the National Science Council (NSC), Taiwan.
The author is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (e-mail: cmtsai@mail.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2009.2027555
shown that the resulting input capacitance may significantly degrade both the bandwidth and the sensitivity in conventional designs [1]. To make a high-gain TIA more tolerant of large input capacitance, the multi-stage design topology has been widely employed in the past decade [2], [3]. It is capable of achieving low equivalent input resistance without sacrificing transimpedance gain and noise performance. However, it may suffer from large power consumption and poor phase margin. Considering the low input resistance requirement, apparently the common-base and common-gate amplifier may become other attractive candidates. Furthermore, by incorporating the transconductance boosting technique, the regulated-cascode design topology has become one other main stream especially suitable for high-speed applications [4]–[6]. However, its major drawback is the resulting poor noise performance. To further extend the operating data rate of a TIA, various inductive peaking techniques have been developed in the past years [7], [8]. Recently, the negative-impedance compensation (NIC) has been successfully employed to implement low-power low-noise TIA [9] and LA [10]. The NIC has been shown to be capable of improving gain and bandwidth simultaneously. Compared to the inductive peaking, the NIC is not only more flexible but also cost-effective. In summary, all of the design techniques described above focus on the TIA design without any appro-priate treatment of the input loading capacitances. Apparently, once the input capacitance can be reduced, the following TIA design becomes significantly simplified. Employing a positive feedback loop for the voltage control of the PD, the boot-strapping technique, as proposed in our previous work [11], has been shown to be capable of reducing the effective input capacitance due to the PD. As a result, a TIA with both high transimpedance gain and wide dynamic range can be easily achieved. Furthermore, by combining an appropriate differen-tial-sensing scheme with the bootstrapping technique, we have successfully demonstrated a self-compensated TIA (SC-TIA) with enlarged input capacitance tolerance [12]. Recently, sev-eral fully-differential CMOS TIAs have been demonstrated for multi-gigabit applications in literatures [13], [14]. However, these designs lack the capability to provide dc signal path as well as a suitable PD reverse bias voltage. In this paper, we will discuss the fundamentals of the SC-TIA and the NIC. Then we will propose a wide dynamic range CMOS SC-TIA design employing the NIC for achieving greatest enhancements in both transimpedance gain and bandwidth.
Fig. 1. Schematic of TIA employing bootstrapping technique.
II. FUNDAMENTALS OFSC DESIGNTOPOLOGY
In a conventional single-ended TIA, one terminal of the PD is connected to the TIA input and the other terminal is con-nected to a constant bias voltage. Therefore the PD behaves like a loading capacitance at the TIA input. The bootstrapping tech-nique, as shown in Fig. 1, introduces an additional positive feed-back loop for appropriate voltage control of the PD. Therefore, the voltage at the PD anode will automatically track the voltage at the PD cathode to reduce the photocurrent-induced transient voltage across the PD. As a result, the effective input capaci-tance due to the PD with a equivalent capacicapaci-tance is given by
(1) To achieve a better capacitance suppression ratio, a unity-gain voltage buffer with low output impedance is required. How-ever is required for stability in this design. On the other hand, if both the photocurrents coming from the anode and the cathode of the PD can be used for signal detection si-multaneously, then a differential-sensing design with doubled transimpedance gain can be obtained. The differential-sensing scheme potentially provides improved signal-to-noise ratio and power supply rejection. Apparently the simplest implementa-tion of the unity-gain voltage buffer is a source follower. As we can see, the source buffer can also serve as a unity-gain current buffer to transfer the photocurrent coming from the PD anode to its drain terminal so as to enable the desired differential-sensing capability. The proposed SC design topology is shown in Fig. 2, where and denote the grounded input capacitances due to the bondpads and the ESD protection circuits, denotes the equivalent input resistance of the following TIA. Both the cur-rent sources and are required to bias properly. Assume that the channel length modulation effect, the body effect, and all the other parasitic capacitances are negligible. We have
(2)
(3) where
(4)
and (5)
Fig. 2. Schematic of the SC design topology.
Fig. 3. Photo responses of the SC design topology.
Assuming and , the two pole frequencies
can be approximated as
(6) It is apparent that . Therefore the differential photoresponse is given by
(7)
Considering a typical case , from (5) and (6) we have . As a result, perfect pole-zero cancellation occurs in (7). It follows that the 3 dB bandwidth of the differential photo response is limited by the second pole which is given by (8) Fig. 3 shows the corresponding Bode magnitude plots of the photo responses derived above. In summary, the grounded input capacitances and cause a bandwidth reduction in the photo response and a high-frequency peaking in the photo response . If and are approximately equal, then these two effects can ideally cancel each other to minimize the re-sulting bandwidth degradation. Therefore, the differential photo response becomes less sensitive to the grounded input capaci-tances. If the bootstrapping transistor is excluded in Fig. 2,
From (8) and (9), it shows that the SC design topology achieves a bandwidth enhancement factor of ( ). Moreover, as we can see in Fig. 2, the SC design topology can automatically pro-vide a reverse bias voltage of to the PD so as to guarantee an acceptable operating bandwidth.
The price paid in the SC design topology is the extra noise introduced by the bootstrapping transistor and the required bias current sources. Assuming that the noise currents in these three components follow the direction of the bias current, the equiva-lent input noise currents of the following TIA are derived as
(10) (11)
where . The differential noise
cur-rent is given by
(12)
It follows because . That is, the noise
current is negligible compared to . Computing the mean-square values, we have
(13)
where is the angular frequency and is the noise factor of the MOSFET. At low frequencies the noise performance is domi-nated by the noise components introduced by and [1]. The noise component introduced by increases with increasing frequency. To reduce the noise current, long-channel transistors can be used to provide and owing to the decrease in . Furthermore, for a given bias current, the overdrive voltages of the transistors must be maximized to improve the noise perfor-mance. As we can see, the obtained noise performance is sim-ilar to that obtained in the common-gate amplifier. The major advantage of the SC design topology is the improved SNR by a factor of 6 dB due to its differential-sensing capability.
III. FUNDAMENTALS OFNIC
Fig. 4 shows the small-signal model for a TIA employing the NIC, where the Norton equivalent is used to model the inverting
Fig. 4. Schematic of TIA employing NIC.
amplifier and the employed negative impedance is denoted by . The closed-loop transimpedance gain can be derived as
(14) where
(15) (16) Typically we have . From (15), the NIC is shown to effectively cancel the loading effects caused by and . To maximize the enhancement, the NIC must provide both resistive and capacitive compensations. As we can see from (15), the neg-ative resistance and the negneg-ative capacitance can enhance the dc gain and the bandwidth of the closed-loop voltage gain, , re-spectively. From (16), hence the equivalent input impedance can be significantly reduced. For a large , generally the input pole dominates the frequency response of the transimpedance gain. Once can be reduced, the input pole can be moved to a higher frequency. For high-gain applications, it is apparent that is the major object to be compensated. Therefore, if the output impedance can be kept as high as possible, then not only the implementation of the required NIC becomes easier but also the noise introduced by the NIC can be minimized.
IV. CHIPIMPLEMENTATION
Fig. 5 shows the complete circuit diagram of the SC-TIA IC. The IC is implemented in a 0.18 m CMOS technology. To reduce waveform distortion and improve overload charac-teristic, it is necessary to incorporate automatic offset cancel-lation (AOC) circuit. In this design, the AOC is provided by a dual-loop feedback circuit comprising two error amplifiers and two controllable current sources realized by and . The working principle of the AOC is to maintain constant dc cur-rents passing through both feedback resistors while receiving the photocurrent. An on-chip grounded capacitor of several pF is connected to the output of each error amplifier to introduce a lower cut-off frequency of about 50 kHz. A simple RC network, comprising and , is used to provide both the ac coupling path required for capacitance suppression and the dc control of the PD reverse bias voltage. In this design, the supply voltage is 1.8 V and the reverse bias voltage for the PD is 1.2 V. If the input dc currents of the core differential TIA, , are kept close to zero, then the voltage headroom available for the output of is about a half of the rest voltage headroom, that is, 0.3 V. Apparently, it may cause difficulty in achieving high open-loop
Fig. 5. Schematic of the SC-TIA IC.
Fig. 6. Schematic of the core differential TIA.
gain. To overcome this problem, the two error amplifiers used for achieving AOC are designed with a built-in offset voltage, , of approximately 0.3 V. Thus the available voltage head-room is doubled. Following the core circuit, a wideband gain stage and an output buffer capable of driving 50 loads are included. The capacitors and are used to simulate the equivalent capacitances of the ESD protection circuits. In this
design pF is used. By controlling the switches
and , the effects of the parasitic capacitances on the receive performance can be evaluated directly.
Fig. 6 shows the circuit diagram of the core differential TIA, . A simple single-stage design is used to serve as the main amplifier due to its excellent noise performance and stability. The major drawback is the poor open-loop gain. In general, ac-tive loads can be employed instead of resistors to achieve sig-nificant gain boosting. However it inevitably results in degraded dynamic range due to the poor linearity of the active loads. In this design, both the built-in offset creation and the NIC are used instead to improve the gain-bandwidth product. The former technique results in doubled voltage headroom and hence the open-loop gain can be increased by using a larger resistance
Fig. 7. Schematic of the error amplifier with built-in offset.
for . The negative resistance is generated by , and . The negative capacitance is generated by , and . Both compensation strengths can be adjusted by and , sep-arately. Moreover, an additional feedback circuit, consisting of the resistor string using two resistors, an error amplifier and , is included to properly control the output common-mode voltage so as to guarantee a stable operating condition.
To evaluate the effect of the NIC on the overall performance, the tail currents , and can be fully turned off if required. The AOC along with the common-mode control loop in keeps the input and output common-mode voltages of con-stant all the time. When the NIC is turned off, the common-mode control loop increases the bias current of and . The in-creasing increases the loop gain, hence increasing both the transimpedance gain and the bandwidth simultaneously. Basi-cally, the evaluation of the NIC is based on identical power con-sumption in . If remains constant in the evaluation, then a wider performance gap is to be expected.
To simplify the noise analysis for , a fully-symmetric cir-cuit is assumed and the input capacitances are neglected.
As-suming , for the equivalent differential
noise current at each output can be approximated as
(17)
where . Assuming ,
the corresponding input referred noise current in the differential-sensing scheme is derived as
(18) By using the built-in offset creation technique, is almost doubled. As a result, the required becomes smaller and hence the resulting noise degradation is reduced. In general, the SNR of a differential TIA is 3 dB worse than its single-ended counterpart. However, the differential-sensing capability can provide a 6 dB SNR improvement. Therefore, a differential TIA with differential-sensing capability can potentially achieve a 3 dB SNR improvement according to (18).
Fig. 7 shows the circuit diagram of the error amplifier used for the AOC. It is basically a two-stage amplifier employing the negative resistance compensation for gain boosting. The 0.3 V
Fig. 8. Schematic of the gain stage and the output buffer.
built-in offset is created by introducing large geometric mis-match between the differential input transistors according to the relation given by
(19) where denotes the width ratio between the input transistors, denotes the threshold voltage for NMOS devices. From (19), ap-parently the overdrive voltage must be maximized to minimize the undesired variation in due to the variation in , hence the tail current source of the input differential pair is excluded as we can see in Fig. 7. In addition, the negative resistance created by the cross-coupled pair consisting of and is used to improve the voltage gain. The resulting voltage gain is inversely proportional to the difference in transconductance between and , hence it can be easy to achieve great enhancement by keeping the ratio of slightly smaller than that of . For the error amplifier design used for the output common-mode voltage control in Fig. 6, a matched differential pair with a tail current source is used as the input stage to minimize the offset. For the design of the gain stage following the core differen-tial TIA, the active feedback technique [15], [16] combined with negative capacitance compensation is used to not only achieve wideband performance but also reduce the large loading capac-itance due to the output buffer. On the other hand, a wideband -doubler is used for the output buffer design. Fig. 8 shows the corresponding circuit diagram.
Fig. 9 shows the die micrograph of the TIA IC. The IC occu-pies a chip area of 560 400 m and the active area excluding the decoupling capacitors is about 100 100 m . The IC to-tally consumes 40 mW from a 1.8 V supply. The SC-TIA core only uses 8 mW, including 3 mW for the NIC. The rest of the circuits consume 32 mW.
V. EXPERIMENTALRESULTS
Due to the special circuit arrangement, electrical test is not appropriate for performance evaluation of the TIA IC. For op-tical test at wavelength of 1310 nm, the TIA IC is connected to a commercial InGaAs PIN PD in a chip-on-board assembly.
Fig. 9. Die micrograph.
Fig. 10. Measured frequency responses.
The active area of the PD is 70 m in diameter. The PD re-sponsivity is 0.9 A/W and the corresponding equivalent capaci-tance is around 0.8 pF at a 1.2 V reverse bias. Fig. 10 shows the measured optical frequency responses. As the NIC is disabled, the measured 3 dB bandwidth is about 350 MHz whether and are connected or not. While enabling the NIC, the mea-sured 3 dB bandwidth is slightly degraded from 1.82 GHz to 1.72 GHz as and are connected. The NIC is shown to
Fig. 11. Measured eye diagrams: (a) without NIC at 1 Gb/s,and (b) with NIC at 3 Gb/s.
Fig. 12. Measured BER versus input optical power at 3 Gb/s.
achieve enhancement factors of 4.5 dB and 520% respectively for transimpedance gain and bandwidth. For eye diagram mea-surement, a 2 1 pseudo-random bit sequence is used and the extinction ratio of the optical transmitter is 10 dB. Fig. 11 shows the measured eye diagrams at an input optical power of 15 dBm. Without the NIC, the IC cannot properly operate at 1 Gb/s. With the NIC, the IC can support applications at data rate up to 3 Gb/s. The loading effects of and on the sured eye diagrams are almost negligible. Apparently the sured time-domain results are in great agreement with the sured frequency responses. For the bit-error rate (BER) mea-surement, the output signal of the optical receiver is amplified by a commercial 10 Gb/s limiting amplifier before it is sent into the BER tester. Fig. 12 shows the measured BER versus input optical power at 3 Gb/s. At a BER of , the sensitivity is
slightly degraded from dBm to dBm as and
are connected. To evaluate the overload characteristic at 3 Gb/s, the IC is tested at an input optical power of dBm and the measured eye diagram is shown in Fig. 13. The observed jitter is 75 ps . In summary, the IC has achieved a dynamic range of greater than 20 dBm to 0 dBm without incorporating any gain control. The measured differential transimpedance gain is
Fig. 13. Measured 3 Gb/s eye diagram at input optical power of+0 dBm.
TABLE I PERFORMANCECOMPARISON
3.5 k without any stability problem. The measured maximum differential output swing is 570 mV .
Table I summarizes the performance of our SC-TIA along with previous publications. Apparently, the SC-TIA can achieve high gain, wide dynamic range and low power consumption si-multaneously. Combining with the NIC, the SC-TIA is suitable for low-voltage applications.
VI. CONCLUSION
The SC-TIA has been shown to provide improved SNR owing to the differential-sensing capability. The SC-TIA IC is shown to be tolerant of ESD protection circuit with 0.5 pF equivalent capacitance at the differential inputs. The observed sensitivity degradation is 0.3 dB due to the additional 0.5 pF input capac-itances. The built-in offset creation technique not only doubles the voltage headroom available for the core TIA but also im-proves the overload characteristic. By using the NIC, the ob-tained enhancement factors for transimpedance gain and band-width are 4.5 dB and 520%, respectively. Without incorporating any gain control, the IC has achieved a dynamic range of greater than 20 dB.
ACKNOWLEDGMENT
The authors wish to acknowledge the SoC Technology Center (STC) in Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, for chip fabrication, and thank
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Chia-Ming Tsai (M’06) was born in Tainan, Taiwan, in 1967. He received the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1991 and 1997, respectively.
After that, he joined the Opto-Electronics and Sys-tems Laboratories, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, as a designer for optoelectronic devices. In 2000, he joined the SoC Technology Center, ITRI, as an analog IC designer. Since July 2005, he has been with the Department of Electronics Engineering, National Chiao-Tung University, as an Assistant Pro-fessor. His research interests are in the area of high-speed integrated circuits and optoelectronic devices. He is currently working on the analog front-end design for fiber communication applications.
