Background calibration of integrator leakage in discrete-time delta-sigma modulators

Background calibration of integrator leakage in discrete-time

delta-sigma modulators

Su-Hao Wu•_{Jieh-Tsorng Wu}

Received: 26 March 2014 / Revised: 31 August 2014 / Accepted: 30 September 2014 / Published online: 16 October 2014 Ó Springer Science+Business Media New York 2014

Abstract This paper presents an integration-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. To calibrate an integrator, its integration leakage is detected in the digital domain, and the leakage compen-sation is applied to the same integrator in the analog domain. The proposed scheme can calibrate all integrators in a discrete-time DSM of any form. It can be proceed in the background without interrupting the normal DSM operation. The design considerations for the proposed calibration scheme are discussed. Design cases of a 1st-order, a 2nd-1st-order, and a 3rd-order DSM are demonstrated and simulated.

1 Introduction

Delta-sigma modulators (DSMs) are widely used in high-resolution analog-to-digital converters (ADCs). A DSM can effectively suppress the quantization noises arising from its internal quantizer by combining its noise-shaping function with the oversampling operation. Comparing to Nyquist-rate ADCs of similar performance, DSMs require analog circuits of higher speed. Consider a discrete-time single-loop DSM that comprises a cascade of

switched-capacitor (SC) integrators. Each integrator contains an opamp. The open-loop unity-gain frequency and slew rate of the opamp determine the speed of the integrator, while the dc voltage gain of the opamp dictates the quality of the integration function. An SC integrator realized with a low-gain opamp is lossy, i.e., it exhibits integration leakage. If the integrators in a DSM are lossy, the noise-shaping capability of the DSM is weakened, resulting in degraded signal-to-quantization-noise ratio (SQNR).

As CMOS technologies advances, MOSFETs become smaller and faster, but their intrinsic voltage gain, gm=gds,

also decreases. Consider a standard 32 nm CMOS. A minimum-channel-length MOSFET has a maximum transit frequency fTof over 400 GHz, but it has an intrinsic gain of

only about six [1]. Furthermore advanced CMOS technol-ogies have lower supply voltage, it is difficult to design high-speed opamps that also have a good dc gain. Although correlated double sampling [2], correlated level shifting [3], and multiple-stage configuration [4] can be used to raise the dc gain of opamps, all sacrifice the speed.

To take advantage of the advanced nano-scale CMOS technologies, we propose using opamps with simple circuit configuration and MOSFETs of minimum channel length. The resulting SC integrators are high-speed and low-power but also lossy. We then employ calibration to compensate the integration leakage of the integrator and recover the noise-shaping capability of the DSM. There are calibration techniques that can improve the frequency accuracy of the noise-shaping functions of the DSMs [5–8]. They all assume the opamps have sufficiently large dc gain. A calibration technique has been proposed to correct both the integration leakage and the distortion of the integrators in a cascade DSM [9]. However, it is difficult to obtain the required modeling parameters from the DSM digital output alone.

S.-H. Wu (&)  J.-T. Wu

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan

e-mail: [email protected] J.-T. Wu

e-mail: [email protected] DOI 10.1007/s10470-014-0421-y

This paper proposes an integration-leakage calibration technique for the integrators in an SC DSM. To calibrate an integrator, its integration leakage is detected in the digital domain, while the leakage compensation is added to the same integrator in the analog domain. Once all integrators are calibrated, the SQNR performance of the DSM is restored. The proposed scheme can calibrate all integrators in a DSM of any form. It calibrates one integrator at a time. It can proceed in the background without interrupting the normal DSM operation.

The rest of this paper is organized as follows. Section2

discusses the effect of integration leakage on the SQNR performance of DSMs. Section3 introduces the SC inte-grators with leakage compensation. Section4 introduces the proposed calibration technique with a 1st-order DSM design case. Design considerations are outlined. Section5

applies the calibration technique to a 2nd-order DSM design case. Section6applied the techniques to high-order DSMs. Section7 demonstrates a 3rd-order DSM design case. Finally, Sect.8draws conclusions.

2 Integration leakage and its effect

Figure1 presents a conventional SC integrator, its z-domain transfer function is

HðzÞ ¼VoðzÞ ViðzÞ ¼ a 1 bz1 ð1Þ with a¼  Cs Ci 1þ 1 A0 CiþCsþCp Ci b¼ 1þ 1 A0 CiþCp Ci 1þ1 A0 CiþCsþCp Ci ð2Þ where A0 is the dc voltage gain of the opamp and Cpis the

total parasitic capacitance associated with the negative terminal of the opamp. If the opamp is ideal with A0¼ 1,

then a¼ Cs=Ci and b¼ 1. Figure2 illustrates the

inte-grator time-domain output response, in which Vi½k ¼ 0 for

k[ 0. If b¼ 1; Vo½k maintains its Vo½0 value for k [ 0. If

b\1, then the charge on capacitor Ci leaks and Vo½k

decreases as k progresses. An integrator with b\1 is a lossy integrator.

Figure3 shows a DSM that uses the lossy integrators. Although the coefficient a for the integrator of Fig.1 is negative, the coefficients a1 and a2 in Fig.3 are positive

for simplicity. Their polarities can be easily changed in a fully differential circuit configuration. Assume the digital-to-analog converter (DAC) is ideal. The difference between the sampled analog input x½k and the DAC output is integrated by two lossy integrators and then quantized by a sub-ADC. The sub-ADC introduces quantization errors e½k. The sub-ADC digital output y½k can be expressed as YðzÞ ¼ STFðzÞ  XðzÞ þ NTFðzÞ  EðzÞ. Where STFðzÞ is the signal transfer function and NTFðzÞ is the noise transfer function. If the integrators are lossy, i.e., b1\1 and b2\1, then the zeros of the NTF deviate

from the unit circle in the z-plane, diminishing the the DSM’s ability of suppressing the sub-ADC quantization errors. Consider an M-th order DSM with M lossy inte-grators. Its NTF is expressed as

NTFðzÞ ¼ 1  bz 1M ð3Þ

The b coefficients are assumed to be identical for sim-plicity. If the sub-ADC in the DSM has B-bit resolution, then the DSM’s maximum SQNR is

SQNR¼ 2B_pffiffiffiffiffiffiffiffi_{3=2 SQNR}

NTF ð4Þ

where SQNRNTFis the SQNR enhancement by the NTF. It

can be expressed as Cs Ci Vo Cp Vi 1 1 2 2

Fig. 1 A conventional switched-capacitor (SC) integrator

Vo Vo [k] [k] β = 1 β < 1 k 5 0 1 2 3 4 6 7 8 k 5 0 1 2 3 4 6 7 8

Fig. 2 Integrator time-domain output response. Vi½k ¼ 0 for k [ 0

1 z β2 α2 1 z 1 z α1 β1 DAC 1 x[k] y[k] sub−ADC 1

SQNRNTF¼ Pe Pe;sh ¼2Mþ 1 h p2M  OSR 2Mþ1 ð5Þ with h¼X M n¼0 M! n!ðM  nÞ! ð2M þ 1ÞbMn 2M 2n þ 1 OSRð1  bÞ p  2n ð6Þ where OSR is the oversampling ratio. If b¼ 1, then each term of (6) is zero except n¼ 0, and h ¼ 1. If b 6¼ 1, then h [ 1, yielding a larger in-band quantization noise power. Figure4 shows the effects of b on SQNRNTF when

OSR¼ 64. If b ¼ 1, an ideal 3rd-order DSM can offer an SQNRNTF of 105 dB. However, if b¼ 0:9, the resulting

SQNRNTFis degraded to 77 dB. Figure5shows the effects

of b on SQNRNTF when OSR increases. For an ideal

M-order DSM, the SQNRNTF is improved by 6 Mþ 3 dB

when the OSR is doubled. If b\1, it becomes less effec-tive for the DSM to improve SQNRNTFby increasing OSR.

Although above conclusions are established on assuming

that all NTF’s zeros are located at b for simplicity, similar results are obtained even NTF’s zeros are separated.

3 Integrator with leakage compensation

Consider the lossy integrator, its output falls by ð1  bÞVo½k  1 from cycle k  1 to cycle k. Figure6shows the

proposed SC integrator to compensate this leakage. The capacitor Cf is added to sample Vo. The charge on Cf is

added to the integrator in the next clock cycle. Similar integrators can be found in [10, 11]. The resulting b coefficient of the integrator is

b¼ 1þ Cf Ciþ 1 A0 CiþCp Ci 1þ1 A0 CiþCsþCfþCp Ci ð7Þ If Cf ¼ Cs=ðA0 1Þ, then b ¼ 1 and the integrator

becomes lossless. Since Cf  Cs, this Cf capacitor and its

associated switches add minuscule loading and noise to the integrator. The required Cf is sensitive to

process-voltage-temperature variations. Therefore, the integrator requires calibration to adjust Cf. In our design, a digital signal

T½k 2 f0; 1; 2; . . .g controls Cf. A calibration processor

(CP) continuously runs in the background to adjust Cf to

ensure b¼ 1. The adjustable b can be expressed as

b¼ b0þ Db  T½k ð8Þ where Db¼ 1þ 1 A0 CsþCp Ci 1þ2 A0 CiþCsþCf 0þCp Ci DCf Ci ð9Þ and DCf is the digital-control capacitance step size. A

smaller DCf makes b closer to 1 when calibration is applied

to adjust Cf, resulting in a better SQNRNTF.

0.90 0.95 1.00 1.05 1.10 β 40 50 60 70 80 90 100 110 SQNR NTF (dB) M=3 M=2 β=1 M=1

Fig. 4 DSM SQNR enhancement versus b. Assume OSR¼ 64. For a 1st-order DSM, M¼ 1. For a 2nd-order DSM, M ¼ 2. For a 3rd-order DSM, M¼ 3

4 8 16 32 64 128

Oversampling Ratio (OSR)

20 40 60 80 100 120 SQNR NTF (dB) Μ=3,β=1 Μ=2,β=1 Μ=3,β=0.9 Μ=2,β=0.9 21dB/octave 15dB/octave Μ=1,β=0.9 Μ=1,β=1 9dB/octave

Fig. 5 DSM SQNR enhancement versus oversampling ratio (OSR)

Vo Cp Ci Cs Vi 2 S 1 S Cf Cf 1(2) 1 1(2) 2 2(1) 2(1) Δ = T[k]

Fig. 6 A switched-capacitor integrator with leakage compensation. It is either an inverting integrator or a non-inverting integrator, depending the clock phases denoted on the switches

4 First-order DSM design case

4.1 Architecture

Figure7shows a 1st-order DSM using the integrator of Fig.6. If Cs¼ Ci and A0¼ 8, then a ¼ 0:8 and b ¼ 0:9.

This DSM includes a background calibration that auto-matically adjusts the Cf capacitor in the integrator to

maximize the DSM’s SQNR. The sub-DAC has N levels and covers an output range of1. The least-significant-bit (LSB) size is D¼ 2=ðN  1Þ. The DSM output is y½k. If N is odd, y½k has its value among f0; 1; 2; . . .;  ðN  1Þ=2g. If N is even, y½k has its value among f0:5; 1:5; . . .; ðN=2  0:5Þg, The DAC output is Vda½k ¼ D  y½k  1. The input thresholds of sub-ADC

correspond to the middle of adjacent DAC outputs, its LSB size is also D. The DSM has a sampling rate of fs. The

modulator digital output y½k is

D Y ¼ STF1 X þ NTF1 E ð10Þ where STF1¼ H 1þ z1_H NTF1 ¼ 1 1þ z1_H ð11Þ

and H is the transfer function of the integrator expressed in (1). As proposed in Sect.3, the b of the integrator is adjustable. It is adjusted automatically by the calibration processor (CP) shown in Fig.7. To facilitate calibration, a periodic square wave c½k ¼ q½k  Vcis added to the

sub-ADC input. The CP detects the calibrating signal embed-ded in y½k, generates a control signal T½k, and adjusts b to make b¼ 1.

Figure8shows a signal flow diagram of the calibration. The modulator input x½k and sub-ADC quantization errors e½k are shaped by STF1 and NTF1 respectively. The

cali-brating signal c½k is shaped by NTF1, yielding d½k. The

summation of the above three signals is converted to y½k

with a conversion gain of 1=D. The calibrating signal c½k is expressed as a periodic binary square wave q½k 2 f1; þ1g multiplied by an amplitude of Vc. Thus,

embedded in y½k, d½k is the step response of NTF1

trig-gered by c½k. Figure9shows the d½k waveform. The step response has an initial value of

Vci¼ Vc

2aþ 1  b

aþ 1  b ð12Þ

and settles toward a final value of

Vcf ¼ Vc

1 b

aþ 1  b ð13Þ

Since Vcf depends on 1 b, it can be used to detect b. Vc 1 z

Σ

Σ

Fig. 7 A 1st-order DSM with the proposed calibration scheme

Σ g[k] STF1 NTF1 NTF1 1 BPD y[k] d[k] x[k] e[k] c[k] r[k] ACC1 AAR reset s[k] b[k]

Fig. 8 Calibration signal flow diagram

Vcf Vc −Vc −Vcf 1 1 1 1 k 0 q[k] k k 0 0 d[k] g[k] k 0 c[k]

Fig. 9 Calibration signal waveforms

Nth Nth [k] β k k 0 s[k] 1

Figure8 shows the CP operation. The CP correlates the DSM output y½k with a triple-valued sequence g½k 2 f1; 0; þ1g. The g½k waveform is illustrated in Fig.9. It has the same polarity as q½k, but its value is set to 0 during the initial transition phase of d½k. Thus, the resulting product r½k contains only the valid Vcf

informa-tion. Following r½k is an accumulator (ACC1). It is fol-lowed by a binary peak detector (BPD). Together they perform the accumulation-and-reset (AAR) operation [12] to extract Vcf from r½k while removing the perturbations

caused by x½k and e½k. The AAR operation is described as follows. Accumulator ACC1 accumulates the r½k sequence. Its output s½k is monitored by a BPD with a threshold Nth [ 0. Whenever s½k reaches either þNth or Nth, the BPD issues an output b½k ¼ þ1 or b½k ¼ 1 for one clock cycle respectively and reset s½k to 0. The BPD output b½k remains at 0 when no reset occurs. The BPD output b½k is an estimate of the ð1  bÞ polarity. The CP uses it to adjust the b of the integrator. As shown in Fig.7, following b½k is another accumulator, ACC2, that accumulates the b½k sequence. Its output T½k controls the b according to (8). Figure10 illustrates the time-domain waveform of the ACC1 output s, and the waveform of the resulting b. When b approaches 1, both j1  bj and Vcf

become smaller, and it takes a longer time to activate the BPD.

4.2 Calibration parameters

This calibration has five design parameters, including the c½k amplitude Vc, the c½k frequency fq, the g½k duty ratio

Dg, the BPD threshold Nth, and the T½k control step size

Db. Referring to Fig.9, the duty ratio Dg is defined as the

ratio of the time for g½k ¼ þ1 to the time for q½k ¼ þ1. The duty ratio for g½k ¼ 1 and q½k ¼ 1 is assumed to be the same as Dg.

We use the aforementioned 1st-order DSM design case to illustrate the design considerations for the proposed calibration scheme. The DSM block diagram is shown in Fig.7. Its sub-ADC and DAC have N¼ 16 quantization steps. The corresponding quantization step size is D¼ 2=15. It has a sampling frequency of fs and a

corre-sponding sampling period of Ts¼ 1=fs. The integrator in

Fig.7 is realized using the SC integrator of Fig.6 with a transfer function of (1). If the opamp has a dc gain of A0¼ 8, then a ¼ 0:8 and b ¼ 0:9. Assume the OSR of the

DSM is 64. Its theoretical maximum SQNR is 74 dB when A0¼ 1. We will apply the proposed calibration to recover

SQNR.

As shown in Fig.7, the calibration square wave c½k ¼ q½k  Vc is added to the sub-ADC input. Let c½k have a

frequency of fq, a corresponding period of Tq¼ 1=fq, and a

duty cycle of 50 %. The resulting d½k, as shown in Fig.9, is embedded in the sub-ADC output y½k. In each fq cycle,

the transient response of d½k is a step response of NTF1

triggered by c½k. It can be expressed as d½k ¼ Vc

2aðb  aÞkþ ð1  bÞ

aþ 1  b ð14Þ

This step response has an initial value of Vci of Fig. (12)

and then settles toward the Vcf of (13). Figure11 shows

several d½k waveforms with different b.

The d½k waveforms have settled near Vcf for k [ 5. We

choose Tq ¼ 16Ts and Dg¼ 1=4, so that, in each d½k

transient, d½k has a period of 6 clock cycles to settle before g½k is activated for 2 clock cycles. The frequency of the injected signal c½k is fq¼ fs=16. As long as OSR [ 8, the

frequency components of d½k in y½k is outside the signal band. It can be easily removed by the decimation filter following the DSM.

The injection of the calibration signal c½k degrades the DSM’s maximum SQNR, since c½k increases the input signal range of the sub-ADC input. The SQNR degradation is a function of the c½k amplitude Vc. Figure12shows the

simulated SQNR of the DSM design case. The injected c½k has a frequency fq¼ fs=16. In Fig.12, SQNR is plotted

against x½k input amplitude with different Vc. The x½k

frequency is fin¼ ð41=216Þfs. If Vc¼ 1D ¼ 2=15, the

maximum SQNR is 71 dB at 1:5 dBFS. If Vc¼ 3D ¼

6=15, the maximum SQNR is 67 dB at 3:0 dBFS. If Vc¼ 5D ¼ 10=15, the maximum SQNR is 66 dB at

4:5 dBFS. In this design example, we choose Vc¼ 1D.

Figure10 illustrates the transient response of b during the calibration. Consider the DSM shown in Fig.7. The averaged variation of s½k for one clock cycle is Ds¼ DgVcf=D. It takes Nth=Ds cycles for s½k to

accu-mulate from 0 toþNth (or Nth) so that T½k is changed by 1 and b is changed by Db. Thus, we have

2 3 4 5 6 7 8 9 10 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0 1 2 3 4 5 6 7 8 9 10 k 0.0 0.5 1.0 1.5 2.0 d[k] β=0.90 β=0.95 β=1.10 β=1.00 β=1.05

db dk¼ Db Nth=Ds DbDgVc aNthD ð1  bÞ ð15Þ

This calibration loop can be modeled as a single-pole feedback system. The transient response of b can be expressed as

b½k ¼ 1  ð1  b½0Þ  ek=s ð16Þ

The time constant s is

s¼Nth Dg  D Vc  a Db ð17Þ

From (17), a smaller Nth and a larger Db lead to a smaller s, yielding a faster calibration speed. However, as the calibration process converges, the behavior of b½k becomes a discrete random fluctuation around 1 [12]. Referring to Fig.8, both x½k and e½k induce this fluctua-tion. Their effects are diminished by the AAR operafluctua-tion. A larger Nth and a smaller Db lead to a smaller fluctuation in b, yielding the better SNDR performance for the DSM.

Figure13 shows the standard deviation of the b½k fluctuation from the system simulation of the DSM design

case. The standard deviation rðbÞ increases drastically for Nth\8. As Nth increases, the standard deviation of b fluctuation, rðbÞ, converges to an averaged value, that can be expressed as

rðbÞ ¼Db_ffiffiffi 6

p ð18Þ

From Fig.4, SQNRNTF is degraded by less than 1 dB if

3rðbÞ\0:015. Using (18), we need Db\0:0122. In this design case, we choose Db¼ 0:01 and Nth ¼ 24.

4.3 Simulation results

This 1st-order DSM design case is verified by using time-domain simulation. Calibration design parameters are fq ¼ fs=16; Dg¼ 0:25; Vc¼ 1D; Db ¼ 0:01, and Nth ¼ 24.

The resulting time constant s¼ 7680 sampling periods. It takes a calibration time of 3s for b to converge from 0.9 to 0.995, where the SQNR degradation due to a non-ideal b is less than 1 dB. Assume the DSM input bandwidth is 2 MHz and the sampling frequency is fs¼ 256 MHz. Then a

cal-ibration time of 3s is 0.09 m/s. Figure14shows the DSM output spectra before and after calibration. The input is a sine wave with a frequency ofð41=216_Þf

sand an amplitude

of 2 dBFS. The resulting SQNR is 58 dB before cali-bration, and is improved to 70 dB after calibration. The frequency components of c½k are visible in Fig.14. They are far away from the signal band.

5 Second-order DSM design case

Figure15 shows a 2nd-order DSM. It includes two inte-grators. The internal opamps of the integrators have a dc gain of 8.2 and 7.7 respectively, yielding a1¼ 0:804;

b1 ¼ 0:902; a2¼ 0:794, and b2¼ 0:897. The regular

sub-ADC1 following the 2nd integrator is single comparator.

-15 -10 -5 0 Input Amplitude (dBFS) 40 45 50 55 60 65 70 75 80 SQNR (dB) Before Cal. V_c=Δ V_c=0 V_c=_5ΔVc=3Δ 4dB 15dB

Fig. 12 SQNR of the 1st-order DSM design case with different Vc.

The opamp in the DSM is ideal

0 8 16 24 32 40 48 56 64 N_th 0 4 m 8 m 12 m 16 m 20 m 24 m σ(β) _Δβ=0.02 Δβ=0.01 Δβ=0.03

Fig. 13 rðbÞ versus Nth with different Db

Thus, for this 2nd-order DSM, N¼ 2 and D ¼ 2. If the integrators are ideal and OSR¼ 64, then the theoretical maximum SQNR is 79 dB.

The proposed calibration scheme adjusts b₁ and b₂ separately. Integrators with adjustable b are described in Sect.3. To calibrate b1, a calibration signal c1½k ¼ q1½k 

Vc1 is injected to the input of the 2nd integrator. A

cali-bration processor, CP1, takes the sub-ADC1 output y½k and generates a control signal T1½k to adjust b1 of the 1st

integrator. The calibration signal c1½k is a square wave

with fq1 frequency, Vc1 amplitude, and 50 % duty cycle.

The calibration processor CP1 is identical to the CP shown in Fig.8. In the CP1, its g1½k signal has a duty ratio of Dg1

and its BPD has a threshold of Nth1. Its output T1½k

controls the b1 of the first integrator such that

b1½k ¼ b0;1 þ Db1 T1½k. Figure16 shows the

calibra-tion signal flow diagram, where e1½k is the quantization

noise of sub-ADC1. We have

D Y ¼ STF1Xþ NTF1E1þ CTF1C1 ð19Þ STF1¼ H1H2 1þ z1_H 2þ z1H1H2 ð20Þ NTF1¼ 1 1þ z1_H 2þ z1H1H2 ð21Þ CTF1 ¼ H2 1þ z1_H 2þ z1H1H2 ð22Þ The sub-ADC1 output y½k is a summation of the input x½k shaped by the signal transfer function STF1, the sub-ADC1

quantization noise e1½k shaped by the noise transfer

function NTF1, and the calibration signal c1½k shaped by

CTF1. The sub-ADC1 has a conversion gain of 1=D. The

calibration signal c1½k go through the CTF1 filter, yielding

d1½k. Thus, embedded in y½k; d1½k is the step response of

CTF1triggered by c1½k. This step response settles toward a

final value of

Vcf 1¼ Vc1 CTF1jz¼1 Vc1

1 b1

a1

ð23Þ This Vcf 1 value is used to detect b1. The calibration

pro-cessor CP1 masks y½k with g1½k to extract only the valid

Vcf 1 information. It then uses the AAR processing to

diminish the calibration fluctuation caused by x½k and e1½k. The CP operation is identical to those described in

Sect.4. Following the design considerations outlined in Sect.4, we choose fq1 ¼ fs=32; Dg1¼ 7=16; Vc1¼ 0:1D;

Db1 ¼ 0:01, and Nth1 ¼ 96. The resulting time constant is

s1¼ 176421 sampling periods.

To calibrate b2, a calibration signal c2½k ¼ q2½k  Vc2

is injected to the input of sub-ADC1. The output of the 1st integrator is digitized by an extra ADC, sub-ADC2, yielding w½k. For this design case, sub-ADC2 is a single comparator. A calibration processor, CP2, takes w½k and generates control signal T2½k to adjust b2 of the 2nd

integrator. Design parameters are the calibration signal frequency fq2, the calibration signal amplitude Vc2, the g2½k

signal duty ratio Dg2, the BPD threshold Nth2, and the b2

control step size Db₂. Figure 17 shows the calibration signal flow diagram, where e1½k is the quantization noise

of sub-ADC1 and e2½k is the quantization noise of

sub-ADC2. We have D W ¼ E2þ STF2Xþ CTF2ðE1þ C2Þ ð24Þ STF2 ¼ H1þ z1H1H2 1þ z1_H 2þ z1H1H2 ð25Þ CTF2¼ z1_H 1 1þ z1_H 2þ z1H1H2 ð26Þ The sub-ADC2 output w½k is a summation of the input x½k shaped by the signal transfer function STF2, the sub-ADC1

quantization e1½k shaped by CTF2, the sub-ADC2

quanti-zation e2½k, and the calibration signal c2½k shaped by

CTF2. The sub-ADC2 has a conversion gain of 1=D. The

calibration signal c2½k go through the CTF2 filter, yielding

w[k] 2 c 1 c 1 T T1 1 z Vda 2 T 1 z z1 [k] [k] CP2 [k] [k] [k] DAC [k] 1 β 1 α 1 β 2 α 2 1 x[k] sub−ADC2 sub−ADC1 y[k] CP1

Fig. 15 A 2nd-order DSM with the proposed calibration scheme

g1 r1 c1 d1 e1 b1 s1 1 STF 1 NTF 1 CTF 1 [k] [k] [k] [k] [k] y[k] x[k] AAR [k] [k]

Fig. 16 Calibration signal flow diagram for b₁ calibration.

g2 r2 c2 d2 e1 e2 2 CTF2 CTF b2 s2 2 STF 1 [k] [k] [k] [k] [k] x[k] [k] w[k] AAR [k] [k]

d2½k. Thus, embedded in w½k; d2½k is the step response of

CTF2triggered by c2½k. This step response settles toward a

final value of

Vcf 2¼ Vc2 CTF2j_z¼1 Vc2 

1 b2

a2

ð27Þ This Vcf 2value can be used to detect b2. The CP2 operation

is similar to the CP1 operation. Note that Vcf 2 is negative,

while Vcf 1is positive. Thus, referring to Fig. 9, the polarity

of g2½k is inverted. To simplify design, c2½k is identical to

c1½k and CP2 is identical to CP1. The design parameters

fq2; Dg2; Vc2;Db2, and Nth2 are identical those for c1½k and

CP1.

Figure18 shows the DSM output spectra before and after calibration. The DSM input bandwidth is 2 MHz and the sampling frequency is fs¼ 256 MHz. The input is a

sine wave with a frequency ofð41=216_Þf

sand an amplitude

of 3 dBFS. The resulting SQNR is 52 dB before cali-bration, and is improved to 72 dB after calibration. The SFDR is improved from 57.71 to 87.25 dB by the cali-bration. The calibration time of 2 3s1¼ 4:1 msec is

required for both b₁ and b₂ to converge from 0.9 to 0.995.

6 Calibration of high-order DSMs

The proposed calibration can be applied to DSMs of any structure. Figure19 is a DSM containing P cascaded integrators with distributed feedback (CIFB). The j-th integrator, where j¼ 1; . . .; P, is modeled as

HjðzÞ ¼ aj 1 bjz1 or ajz 1 1 bjz1 ð28Þ The calibration corrects the b of the integrators one at a time. To calibrate the j-th integrator, HjðzÞ, a calibration

signal c½k is injected at the input of the ðj þ 1Þ-th

integrator, while the output of the ðj  1Þ-th integrator is digitized as w½k and send to the calibration processor (CP). The CP output T½k adjusts the b of the j-th integrator.

Figure20 shows the c½k-to-w½k signal flow, in which x½k and the quantization errors generated by the sub-ADCs are neglected. The function FðzÞ is the transfer function from y½k to w½k. It involves integrators from H1 to Hj1.

The function GðzÞ is the transfer function from c½k to y½k. It involves integrators from Hjþ1 to HP but without the

contribution from HjðzÞ. In the bottom half of Fig.20, the

signal flow is redrawn so that FðzÞ and GðzÞ are in the forward signal path and HjðzÞ and bjHjðzÞ are the feedback

paths. The c½k-to-w½k transfer function CTFjðzÞ

WðzÞ=CðzÞ is CTFjðzÞ ¼

FðzÞGðzÞ

HjðzÞFðzÞGðzÞ þ bjHjðzÞGðzÞ þ 1

ð29Þ Since the signal path of FðzÞ is a cascade of integrators, its dc gain FðzÞjz¼1¼ Fð1Þ is much larger than 1. Then, the dc

gain of CTFjðzÞ can be approximated by

CTFjð1Þ   1 Hjð1Þ ¼ 1 bj aj ð30Þ We design c½k as a square wave with an amplitude of Vc.

In each c½k cycle, the step response of CTFjðzÞ is

embedded in w½k. We design the c½k period to be long Fig. 18 Output spectra of the 2nd-order DSM design case

bj Vc b1 w[k] j+1 b Hj−1 H1 ADCj _CP Hj Hj+1 HP ADC1 DAC x[k] T[k] c[k] y[k] = q[k]

Fig. 19 Calibration of a CIFB DSM

bj bj Hj Hj Hj w[k] c[k] w[k] c[k] y[k] y[k] G F F G

enough so that the step response can settle toward its final value, which is Vcf;j¼ Vc ð1  bjÞ=aj. The CP extracts

Vcf;jto determine the polarity of 1 bj, and then adjusts bj

to make it approache 1.

To calibrate the 1st integrator, H1ðzÞ, the calibration

signal c½k is injected to the input of the 2nd integrator and the DSM regular digital output y½k is used as the CP input. The corresponding c½k-to-y½k signal flow is similar to those shown in 20, but without the FðzÞ block and the outer Hjfeedback path. The c½k-to-y½k transfer function is

CTF1ðzÞ ¼ YðzÞ CðzÞ¼ GðzÞ 1þ b1H1ðzÞGðzÞ ð31Þ Since b1H1ð1ÞGð1Þ 1, the dc gain of CTF1ðzÞ can be

approximated by CTF1ð1Þ  1 b1Hjð1Þ ¼1 b1 b1a1 ð32Þ When c½k is applied, the final value of the CTF1ðzÞ step

response is Vcf;1 þVcð1  b1Þ=ðb1a1Þ. The polarity of

Vcf;1 is different from that of Vcf;jwith j6¼ 1.

Figure21is a DSM containing P cascaded integrators with distributed feedforward summation (CIFF). Similar to the CIFB DSM shown in Fig.19, to calibrate the j-th integrator, HjðzÞ, a calibration signal c½k is injected at the

input of theðj þ 1Þ-th integrator, while the output of the ðj  1Þ-th integrator is digitized as w½k and send to the calibration processor (CP). The CP output T½k adjusts the b of the j-th integrator. Figure22 shows the c½k-to-w½k signal flow, where

F1ðzÞ ¼ H1ðzÞ  H2ðzÞ  . . .  Hj1ðzÞ

F2ðzÞ ¼ b1H1ðzÞ  b2H2ðzÞ  . . .  bj1Hj1ðzÞ

GðzÞ ¼ bjþ1Hjþ1ðzÞ  bjþ2Hjþ2ðzÞ  . . .  bPHPðzÞ

ð33Þ From Fig.22, it can be shown that CTFjð1Þ  1=Hjð1Þ

for j 2 and CTF1ð1Þ  þ1=H1ð1Þ.

The proposed calibration technique can correct the b of all integrators in a DSM. It calibrates each individual integrator one at a time. Although a square wave is injected into the DSM for calibration, its effect on the DSM is

minuscule. The calibration itself is robust. It can easily converge as long as the amplitude of the square-wave calibration signal c½k is sufficiently large. It does not require high-precision analog circuitry, and does not require cumbersome digital circuitry such as narrow-band filters. It can tolerate the non-linearity of the sub-ADCs. The design procedures for the proposed calibration scheme are similar to those described in Sects.4 and5.

7 Third-order DSM design case

A third-order CIFF DSM is simulated to demonstrate the proposed scheme. Figure23 shows the DSM, which is designed in a 65 nm CMOS technology with a 1 V supply voltage. The entire circuit is fully differential. ADC1 and DAC are 2-bit to increase system stability. ADC1 com-prises three comparators with thresholds of f0; 2=9 Vg. The output swing of DAC is1 V. Signal scaling and feed-forward paths are used to relax the linearity requirements of integrators. A passive SC adder preceding ADC1 com-bines the feed-forward paths. All of the integrators use single-stage inverter-based opamps [13]. Figure 24shows the opamp schematic. The channel lengths of the MOS-FETs are chosen to be 60 nm. The resulting dc gain is 8.4 and the gain-bandwidth is 3.9 GHz with a capacitive load of 4 pF. The DSM is operated at 640 MHz with OSR¼ 32. Its input bandwidth is 10 MHz.

To calibrate the first integrator H1, the calibration signal

c1 is injected into to the second integrator H2, and CP1

receives the data stream y from ADC1. To calibrate H2; c2

is injected to the input of the third integrator H3, and the

output u1from H1 is quantized by ADC2 and sent to CP2.

To calibrate H3; c3is injected to the input of ADC1, and the

output u2from H2 is quantized by ADC3 and sent to CP3.

Both ADC2 and ADC3 are 2-bit. The compensation

b1 bj w[k] Vc j−1 b bP H1 CP Hj Hj−1 ADCj Hj+1 HP ADC1 T[k] c[k] = q[k] x[k] DAC y[k]

Fig. 21 Calibration of a CIFF DSM

bj bj Hj 2 F F1 Hj Hj G 2 F F1 c[k] G w[k] y[k] w[k] y[k] c[k]

capacitor Cf 1 comprising a 5-bit capacitor bank can vary

from 0 to 837 fF. Capacitor Cf 2 comprising a 4-bit

capacitor bank can vary from 0 to 240 fF. Capacitor Cf 3

comprising a 4-bit capacitor bank can vary from 0 to 90 fF. The calibrations are performed sequentially and run in the background during the DSM operation. Calibration signals c1; c2, and c3are identical, with a frequency of 11.43 MHz

and an amplitude of 0.01 V. All CPs have Dg¼ 2=7 and

Nth¼ 96. The calibration time, for each b to converge, is around 15 msec.

Figure25shows the output spectra of the DSM from the Spectrer

circuit simulation. The input is a sine wave with a frequency of 1.035 MHz and an amplitude of 0.625 V. The standard variation of the outputs of all integrators is around 0.1 V. Before calibration, the quantization noise leaks into the input band and the SNDR is 73 dB. After calibration, the noise floor drops and a notch appears at 8 MHz. The SNDR is increased to 87.3 dB and the SNR

The power consumption of this DSM excluding CPs is 21 mW. The integrators consume 14.7 mW. ADC1, DAC, and the adder consume 4.1 mW. ADC2 and ADC3 con-sume 2.2 mW. This design reveals that the proposed

technique can correct the NTF whether their zeros are placed at dc or not.

8 Conclusions

Lossy integrators in a DSM degrade the SQNR. This paper proposes a calibration technique to correct the integration leakage of the SC integrators in a DSM of any form. Although the integrators are embedded in a DSM, they can be calibrated one at a time without interrupting the normal DSM operation. Since each integrator is calibrated sepa-rately, the design parameters of the corresponding calibra-tion signal and calibracalibra-tion processor can be easily optimized. This calibration technique has been used to design a 81-dB dynamic range 16-MHz bandwidth DSM chip [14]. This chip was fabricated using a 65 nm CMOS technology. It can operate at 1.1 GHz clock rate under a 1-V supply. To maximize speed, all MOSFETs in the opamps are sized with the minimum channel length of 60 nm, resulting in an opamp dc voltage of 10. 2 1 Cs1 u1 2 2 u3 2 c 2 2 1 u2 2 1 1 c u2 2 Cs2 2 u2 w1 u1 w2 1 u1 2 3 c 1 1 2 Cg Cu3 Cu1 Cu2 Cs3

Ci1 Ci2 Ci3

Cf2 Cf3 Cf1 1 2 1 1 2 1 2 1 1 1 DAC CP3 CP2 CP1 ADC1 x y y ADC2 ADC3 Cs1 Ci1 Cs2 Ci2 Cs3 Ci3 Cg Cu1 Cu2 Cu3 3.981 pF 10.179 pF 976 fF 595 pF 354 fF 1013 fF 16 fF 140 fF 90 fF 80 fF Fig. 23 A third-order CIFF

DSM with local resonator feedback

Vi,p _Vo,nVo,p Vi,n _Vcm 2 Vo,p Vo,n 1 1 2 2 1 Vcmf M1 M3 M4 M5 M6 M2 VDD

Fig. 24 Inverter-based opamp with common-mode feedback

The proposed calibration technique enables the use of low-gain opamps in wide-band high-resolution discrete-time DSMs. It is especially suitable for ultra-high-speed DSMs in advanced nanoscale CMOS technologies. It facilitates the use of amplifiers optimized for speed regardless of their dc gain.

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Su-Hao Wuwas born in Tainan, Taiwan. He received the B.S. degree in electrical engineering from National Tsing Hua Uni-versity, Hsinchu, Taiwan, in 2002, and the M.S. degree in communication engineering from National Chiao Tung Uni-versity, Hsinchu, Taiwan, in 2004. He received the Ph.D. degree in electronics engineering from National Chiao Tung Uni-versity, Hsinchu, Taiwan, in 2013. He is currently a Senior Engineer in the division of ana-log circuit design with MediaTek Inc., Hsinchu, Taiwan. His current research interests include high-performance analog and mixed- signal integrated circuits, with special focus on delta-sigma modulators.

Jieh-Tsorng Wu was born in Taipei, Taiwan. He received the B.S. degree in electronics engi-neering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Stanford Uni-versity, Stanford, CA, in 1983 and 1988, respectively. From 1980 to 1982 he served in the Chinese Army as a Radar Technical Officer. From 1982 to 1988, at Stanford University, he focused his research on high-speed analog-to-digital conversion in CMOS VLSI. From 1988 to 1992 he was a Member of Technical Staff at Hewlett-Packard Microwave Semiconductor Division in San Jose, CA, and was responsible for several linear and digital giga-hertz IC designs. Since 1992, he has been with the Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan, where he is now a Professor. His current research interests are high-performance mixed-signal integrated circuits. Dr. Wu is a member of Phi Tau Phi. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits. Since 2012, he has served on the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC).