bandgap reference. Due to design of a buffer stage, a system can have better bandwidth and phase margin, and thus, the tran-sient response and driving capability can be improved. Besides, the dual-phase control can reduce the output voltage ripple by means of only one closed-loop regulation in order to improve the power conversion efficiency. Besides, the proposed automatic body switching (ABS) circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. Usu-ally, the regulated charge pump circuit needs a bandgap refer-ence circuit to provide a temperature-independent referrefer-ence volt-age. The switched-capacitor-based bandgap reference circuit is uti-lized to regulate the output voltage. This chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm 3.3 V/5 V 2P4M CMOS technology. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that the charge pump can provide 48 mA maximum load current without any oscillation problems.
Index Terms—Bandgap reference, charge pump, dual-phase
power stage, fast transient response, output ripple, system-on-chip (SoC).
I. INTRODUCTION
A
T THE PRESENT, portable electronic devices such as mobile phones or digital cameras are the emerging market of electronic devices, even called the daily essentials. The demand for the portable electronic devices makes the power supply circuit more and more important. In general, the oper-ating time or standby time of the portable devices all depends on the battery capacity. Efficient power distribution is the main concern in the portable device [1]–[4]. On the other hand, the size and weight of these power devices are also important for the designers. The miniaturization of the power modules and the reduction of the external components are essential in portable devices. Besides, the size of the power supply circuit is the major design consideration, no matter whether the circuit is fabricated as a single chip or integrated into a system-on-chip (SoC) chip. For the portable electronic devices, the reduction of the area on Manuscript received June 9, 2008; revised October 26, 2008. Current version published April 17, 2009. This work was supported by the National Science Council, Taiwan, under Grant NSC 96–2221-E-009-240. Recommended for publication by Associate Editor Y. C. Liang.The authors are with the Department of Electrical and Control Engi-neering, National Chiao Tung University, Hsinchu 30099, Taiwan (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2008.2010546
silicon and printed circuit broad (PCB) means lower fabrication cost and tinier size. In other words, a compact power supply sys-tem is necessary for the power management of the SoC syssys-tems. Therefore, the trend is to focus on the CMOS implementation of power converters and insert the power modules into any portable device. Table I shows the different implementation techniques that can be used to supply different applications. For today’s de-signers, how to find an optimum solution has become an urgent issue.
In dc/dc power converters, the charge pump needs less ex-ternal components than the inductive switching converter. The advantages of the charge pump are that it is small, quiet, and moderately efficient. The small board size and small silicon area are the special competitive advantages of the power con-verters. The charge pump circuits can boost or buck voltage using only two external capacitors without the need of an exter-nal inductor. The size of the inductor is larger and its height is hard to be shrunk. Therefore, the size and height of the external components will limit the layout on the PCB, and hamper the minimization of portable devices. Thus, the power supplying system implemented by charge pump circuits is a good solution compared to the inductor-based switching circuits. The charge pump is a good selection under these concerns [5]–[8]. The charge pump provides an efficient approach to transfer different supply voltage levels. The use of energy in an electronic system more efficiently by means of the charge pump circuits can ex-tend the employing time of a battery-powered electronic system. Furthermore, the silicon area of the charge pump and the size of the external components on PCB turn economic [9]–[13]. 0885-8993/$25.00 © 2009 IEEE
Fig. 1. Basic operation of the compact charge pump circuit.
Under the consideration for the chip area, the switched-capacitor-based bandgap reference circuit is used instead of the conventional bandgap reference circuit so as to integrate into the charge pump [14]. In general, the charge pump referred to the bandgap reference circuit determines the value of the out-put voltage. This structure can effectively reduce the quiescent current and chip area. The load capacity always concerns de-signers of the charge pumps because the size and quantity of the power switches will degrade the advantages in the small sili-con area. So, simplifying the sili-control circuit to reserve the space for the large power switches is an important goal in the charge pump circuit design. However, a regulation problem exists in the charge pump design with the built-in bandgap. The output voltage is regulated for only one phase, and thus the output voltage ripple is large. Thus, the proposed method describes a new regulated charge pump circuit with dual-phase regulation, which uses the new proposed output dual-phase power stage. Due to the buffer stage design, the regulated charge pump can provide a maximum of 48 mA load current and regulates output voltage at 5 V for the LED module in the portable devices. The input voltage range is 2.9–5.5 V for the lithium battery.
In this paper, the basic behavior analysis of the proposed charge pump circuit is shown in Section II. Section III describes the circuit implementation. Experimental results are shown in Section IV. Finally, conclusions are provided in Section V.
II. BASICBEHAVIOR ANDANALYSIS OF THECHARGEPUMP In particular, the low quiescent current and small chip area de-sign are used to achieve high conversion efficiency and low cost in converters, a combinative scheme, as follows, of charge pump not only providing the temperature-independent reference, but also regulating and stabilizing the output voltage.
A. Basic Behavior of Combinative Charge Pump
In order to reduce the chip size and quiescent current, the combinative scheme of bandgap reference circuit and regula-tion circuit in Fig. 1 is reasonable. It has the charging (ϕ1) and
discharging (ϕ2) phases. During the charging phase, the
charg-ing current IC H is switched to charge the pumping capacitor
Fig. 2. Emitter-base voltages at the different biasing currents.
Cpum p and the output load is supplied by the output capacitor
CL simultaneously. The value of IC H can be defined as (1),
where Gm is the transconductance of voltage control current
source (VCCS) circuit
IC H = Gm(VR EF− VO U T) . (1)
Besides, during the discharging phase, the capacitor Cpum p
delivers energy to the load and capacitor CL. Thus, the value
of IC H can also be defined as (2). Based on (1) and (2), the
expression of the output voltage VO U T can be derived as (3).
Furthermore, this circuit is regulated with a fixed switching frequency since it is easy to filter out the noise
IC H = 2ILOA D (2)
VO U T = VR EF− 2
IOA D
Gm
. (3)
B. Switched-Capacitor-Based Bandgap Reference
The conventional bandgap reference circuit in Fig. 2 is used to explain the basic operation. The base–emitter voltage VBE of
the bipolar junction transistor (BJT) has a negative temperature coefficient and the thermal voltage VT has a positive
tempera-ture coefficient [15]. The expression for the reference voltage without the influence of temperature is expressed as follows:
VR EF = VBE + VT ln N and ∂VR EF ∂T = ∂VBE ∂T + VT T ln N = 0. (4)
The factor N is the multiple of the bias current on the BJT with the same junction area [16]. The term ln N should be kept at a constant value to minimize the temperature coefficient of the reference voltage. According to the concept of conven-tional bandgap reference circuit, the switched-capacitor-based bandgap reference circuit is used to integrate into the charge pump. As shown in Fig. 3 [13], this circuit generates two base– emitter voltage levels with negative temperature coefficient in the single p-n junction by biasing different current sources. This structure could save much area and power consumption. The BJT is biased by current I during phase ϕ1 and by the
Fig. 3. Schematic of the switched-capacitor bandgap reference in [13].
voltage difference ∆VBE can be derived as follows:
∆VBE= VBE2− VBE1 = VT ln N I IS − VT ln I IS = VT ln N. (5) The operation of this reference circuit is by a switched-capacitor network. During phase ϕ2, VBE2 of BJT is biased
by NI and stored by C2. The circuit is switched to “reset” mode.
When the switches are changed to phase ϕ1, the capacitor C1
is used to store the value of VEB1. The circuit is set to the
“amplify” mode. It generates the reference voltage from the summation of the two different voltages with different temper-ature coefficients. The reference voltage can be obtained by (6) according to the charge balance principle in (7). After several charge distributions, the potential on every capacitor comes off its initial state and the charge at the inverter terminal of the operation transconductance amplifier (OTA) stabilizes
VR EF= C2 C3 VBE2+ C1 C2 VT ln N (6) ∆Q1+ ∆Q2 = ∆Q3 (7)
where ∆Q1 = C1∆VEB1 = C1VT ln N , ∆Q2 = C2∆VEB2,
and ∆Q3 = C3∆VR EF.
Therefore, the parameter ln N (C1/C2) is fine-tuned to
deter-mine the zero temperature coefficient of the reference voltage. The parameter C2/C3is used to determine the scale of the
refer-ence voltage. Besides, a drawback in Fig. 3 is that the produced reference voltage appears only during the “amplify” mode since the charge pump needs the reference voltage to determine the output voltage during phase ϕ1.
As shown in Fig. 4, the bandgap reference circuit is integrated into the charge current controller. The terminal of the capacitor C3 is connected to the output terminal of this charge pump.
The charge at the inverter node of the OTA should be balanced during phase ϕ1. The output voltage of the OTA directly
con-trols the gate voltage VG S of the MOSFET and determines the
charging current IC H, which is called the voltage-mode control
methodology. During the charging phase ϕ1, the current ID S
may exceed the average load current since the drain current ID S
of the MOSFET is the square function of gate voltage in Fig. 5.
Fig. 4. Schematic of the compact charge pump circuit.
Fig. 5. Gate voltage and drain current of the gm amplifier.
Thus, the nonlinear drain current of MOSFET finds it difficult to stabilize the controlling loop and hence to increase the reliability in the voltage-mode control methodology. Therefore, the goal of this paper is not only to drive the white LED by a constant current of 20 mA with a compact solution, but also improve the reliability of the whole charge pump circuit. The proposed circuit increases the load current driving capability and still uses the compact switched-capacitor-based bandgap reference. The specification is defined for an LED driver with high load current driving capability and low output ripple.
C. Loop Gain of the Voltage-Mode Control Methodology The charge pump with a fixed switching frequency deter-mines the output voltage by controlling the ON-resistance of the switching transistors, as shown in Fig. 6. Varying the ON -resistance of the transistor, the voltage mode could determine the drop voltage between the two terminals of the switching transis-tor. Besides, it also determines the voltage across the pumping capacitor. According to the operation of the voltage mode, the value of the output resistance may become smaller than that of the load resistance at the heavy loads. Thus, it may lead to a serious problem at the heavy load. The pole at the output node is defined as (8). Since a large value of CO U Tis selected as the
output capacitor, the output pole is the dominant pole at light loads ωp = 1 (rO//RLOA D) CO U T ≈ 1 RLOA DCO U T at heavy loads (8)
Fig. 6. Current-mode control replaces the ON-resistance with the current source.
Fig. 7. Frequency response of the loop gain by means of the dominant pole compensation.
where RLOA D is the load resistance and rO is the output
resis-tance of the switching transistor. However, at heavy loads, the output pole is smaller than the pole at the drain of transistor M4and becomes the first nondominant pole, i.e., there are two
low-frequency poles leading to serious stability issue at heavy loads. The simplest compensation method is the dominant pole compensation that is used to stabilize the system. Thus, an addi-tional fixed dominant pole is inserted at low frequency, and the frequency response is shown in Fig. 7. However, it deteriorates the bandwidth and results in slow transient response. Besides, it has the minimum load requirement. At light loads, the output pole is moved toward the origin and results in a phase margin smaller than 60◦. Thus, it has a minimum load requirement after using the dominant pole compensation.
D. Proposed Current-Mode Control Methodology
The proposed current-mode control replaces the ON -resistance control device by the current source in Fig. 6, i.e., the transistor M1 operates in saturation and works as a current
source. At this time, the dominant pole is located at the output node since the output resistance of transistor M1 is larger than
the equivalent resistance of the switched capacitor, which is as follows:
rO =
1 fC LKCpum p
. (9)
Fig. 8. Current mirror buffer is used as the output stage of the regulation circuit.
Fig. 9. Small signal model of the charge pump.
Thus, the impedance of the pumping capacitor must be set much smaller than the output impedance of the transistor M1.
In order to make sure that transistor M1 operates in saturation
region, the maximum voltage across the pumping capacitor must be defined as (10). The value of the charge pump capacitor can be decided by (11) ∆VCp u m p, M A X = (VO U T− VSD ,M4)− (VIN − VSD ,M3) (10) Cpum p= ILOA D , M A X fC LK∆VCp u m p, M A X . (11)
Consequently, the output stage of the regulation circuit can be implemented in Fig. 8. This output stage provides a constant cur-rent to ensure that transistor M1operates in the saturation region.
The current I1 is transferred by the voltage-to-current (V –I)
converter that is composed of a transistor MC1 and a resistor RC1. The degenerated resistor RC1makes the transconductance Gm (buff er)(= IO U T/VR EG) more linear. The transconductance
of the current mirror buffer is determined by Gm (buff er)= IO U T VR EG = gm (MC 1) 1 + gm (MC 1)RC 1 K≈ K RC 1 , where K = WM 1/LM 1 WMC 2/LMC 2 . (12)
The value of K should not be set too large because the ca-pacitance at the gate of transistor M1 may generate an
addi-tional low-frequency pole. The small-signal model is shown in Fig. 9. The locations of the pole and zero can be derived as (13)
Fig. 10. Scheme of the proposed method with multiphase output.
Fig. 11. Proposed dual-phase charge-pump circuit that is used to extend to multiphase charge pump. and (14). The dominant pole is located at the output node as
expressed in (13). The output of the first stage has a pole-zero pair (fndp and fz), as shown in (14). The dc gain of the loop is
described in (15) fdp = 1 2πCO U T(rO 2//RLOA D) (13) fndp= 1 2πCC (rO 1+ RC) and fz = 1 2πCCRC (14) AA LL= A1A2 = gm 1rO 1Gm (buff er)(rO 2//RLOA D) . (15)
The strategy of stability is that the dominant pole is the output pole and the nondominant pole is located at the output of the OTA. The additional zero here is generated to compensate the effect of the first nondominant pole. The output impedance rO 1
is too large to locate the additional zero close to that of the nondominant pole. However, the compensation zero is still set at least three to five times higher than the first nondominant pole. Since the nondominant pole and the additional zero are fixed, the dominant pole can be moved to higher frequency in case
of load variations, i.e., the driving capability can be improved compared to that of the voltage-mode control methodology. E. Proposed Multiphase Power Stage
As depicted in Fig. 10, the multiphase output is an effective way to reduce the output voltage ripple. The different voltage waveforms are summed on the output capacitor. If the wave-forms have different phases to each other, the output ripples can be reduced. The dual-phase circuit is proposed to be finally extended to the multiphase output. The dual-phase circuit can provide twice the driving current to the load, and the output volt-age ripple can be expressed as (16) when the equivalent series resistance (ESR) is considered
Vripple =
ILOA D
2fC LKCO U T
+ 2ILOA DESRCO U T. (16)
Since the conventional voltage-mode control charge pump exports only the output current over half period, the charging or discharging current on the output capacitor is very drastic. Thus, the transient dip voltage is very large in case of load
Fig. 12. Equivalent circuits of the power stage at the steady state (a) during phase ϕ1and (b) during phase ϕ2.
variations. However, if the dual-phase method is utilized, the output current from the charge pump to the output load is con-tinuous, and thus, the output ripple can be reduced effectively. The proposed dual-phase design is illustrated in Fig. 11. Dur-ing phase ϕ1, the closed-loop regulation is built up. Module 1
delivers charge to load and module 2 stores the same energy on the pumping capacitor C2 at the same time. During phase ϕ2,
module 2 delivers the stored charge to load and module 1 stores energy via the supply voltage. During both phases, the output load can be driven by one of two charge pump modules, and that the output ripples can be reduced effectively is an advantage of the proposed dual-phase charge pump. Fig. 12(a) and (b) shows the equivalent circuits of steady state during phases ϕ1and ϕ2,
respectively. During phase ϕ1, transistor M2of module 2 works
as the VCCS circuit, as shown in Fig. 12(a). The VCCS circuit provides the same current IC Hwith the transconductance equal
to Gm2. Meanwhile, the load current ILOA Dis drawn from
mod-ule 1. During phase ϕ2, the load current is driven by module 2.
The following equations (17) and (18) stand for the equivalent charging current IC Hduring the two phases, respectively
IC H = Gm 2(VR EF− VO U T) during ϕ1 (17)
IC H = ILOA Dduring ϕ2. (18)
According to (17), (18), and (19) can demonstrate the output voltage that can be regulated to the reference voltage
VO U T= VR EF−
ILOA D
Gm 2
≈ VR EF. (19)
III. IMPLEMENTATION OF THEPROPOSEDDUAL-PHASE CHARGEPUMP
In Fig. 10, the completely compact charge pump circuit with multiphase current-mode control is illustrated. It mainly con-sists of the sensor stage, the buffer stage, the power stage, the
Fig. 13. Sensor stage.
Fig. 15. VE Band ∆VB Eversus temperature.
Fig. 16. Ratio of C1/C2versus temperature.
automatic body switching (ABS) circuit, and the nonoverlap circuit. The function of each stage is describes as follows. A. Sensor Stage
The proposed sensor circuit shown in Fig. 13 is composed of the current source, capacitors, switches, a BJT, and an error amplifier. The sensor stage is used to sense the feedback signal VFBand the bandgap reference to produce a control signal VR EG
to the next stage. In order to reduce the effect of charge injection, the switches are designed by using minimum size. Moreover, the sensor circuit is designed to operate at a very small current. Thus, the voltage drop on the minimum size switches can be ignored. A high-gain error amplifier is needed to make sure that the difference voltage generates the output voltage VR EG
without being affected by the offset voltage of the error amplifier. The error amplifier of the sensor stage is shown in Fig. 14. Because of the autozeroing technique, the offset voltage of the
error amplifier can be canceled in the switched-capacitor circuit [17]. Therefore, this error amplifier is designed by just a simple common-source cascode amplifier with gain-boosting technique for getting a high dc gain. Transistors MO 3and MO 4constitute a
feedback loop to boost the output impedance and high gain. The feedback loop controls the value of the drain–source voltage of MO 1. The drain–source voltage of MO 1is equal to the difference
between the gate–source voltages of MO 3 and MO 4 by the
following equation: VD S(MO 1)≈ 2 µnCOX I4 (W/L)MO 4 − I3 (W/L)MO 3 . (20) Fig. 15 shows the temperature coefficient of VEB during two
different phases. The variation of temperature is from−40◦C to 140◦C. At the temperature equal to 75◦C, the temperature coefficient of VEB is about−1.85 mV/◦C and that of VEB is
Fig. 17. Waveforms of the switched-capacitor bandgap reference circuit. (Temp =−25◦C–125◦C and VIN= 2.5–5.5 V under all process corners).
C1/C2 is used to cancel the negative temperature coefficient
of the voltage VEB. Fig. 16 shows four sets of capacitor ratio
(C1/C2) under different supply voltages. The ratio that makes
the reference voltage be almost constant at high temperature is the better choice since the operating temperature of the chip is often hotter than the room temperature when the chip is deliv-ering the load current. Thus, the ratio C1/C2 = 8.4 is selected.
Certainly, the trimming circuit is also used to compensate the process variations.
Fig. 17 shows the reference voltage of the switched-capacitor-based bandgap reference circuit. It is obvious that the reference voltage is only produced during phase ϕ1. The absolute
vari-ation of the reference voltage is 11.87 mV, which is equal to 64.86 ppm/◦C. The absolute value of the result is not good due to variations in the process. However, the absolute value of the reference voltage can be fine-tuned by trimming the value of the capacitor C3 in (7). It can improve the accuracy due to
pro-cess variations without affecting the characteristic of the zero temperature coefficients.
B. Buffer Stage
The buffer stage is proposed in Fig. 18 [18]. Transistors M2− M8 function as the current mirrors for driving the power
MOSFETs at the power stage. The input consists of the tran-sistor M1and the resistor RG mas a V –I converter. Transistors
MW1 − MW3are the switches that make the current buffer stage
turned off during phase ϕ2, since the output stage is driven by
the dual-phase power stage. The potential HVD D is the highest
potential in the whole charge pump circuit. This potential also supplies to the bulk terminal of the power MOSFETs. Transistor MP is the power MOSFET of the power stage. In this design, the variation of VR EG is 1.5 V at the minimum supply voltage
2.9 V, and the most heavy output current is 100 mA. Then, the transconductance of the current buffer stage has to be larger than that defined as
Gm (buff er) ≥
100 mA
1.5 V = 66.67 mS. (21)
Fig. 18. Current buffer stage.
There is a current mirror with a ratio of 100, which is com-posed of M7and MP for driving the power MOSFET transistor.
The output current on MP is 800 times than that flowing through transistor M1. The overall transconductance from (22) is
domi-nated by the resistor RG m
Gm (buff er)= 800s gm ,M 1 1 + gm ,M 1RG m ≈ 800 RG m . (22) The gate capacitance of the power MOSFETs in the next stage is huge. In order to speed up the transient response of the power MOSFETs, the transistor M9is used to precharge the gate
capacitance of the power transistors. When the output current is exported during phase ϕ1, M9 is turned on to precharge the
gate of the power MOSFET until M7 can fully control MP.
C. Dual-Phase Power Stage
The dual-phase power stage is depicted in Fig. 19. The circuit consists of two charge pump modules. Transistor M7 is in the
Fig. 19. Proposed dual-phase power stage.
buffer stage, and it mirrors K times current to the power MOS-FETs M14 and M24. During phase ϕ1, module 1 charges the
energy on capacitor C1 by M14. Meanwhile, transistor M24 in
module 2 delivers the charge on the capacitor C2 to the output
load. During phase ϕ2, module 1 delivers energy to the output
load and module 2 stores the energy on the capacitor C2from the
voltage supply. In order to set the frequency of the output pole in a controllable range, the transistors M14and M24in Fig. 19
are operated in the saturation region. The output resistance of the transistor in the saturation region is almost constant and rel-atively large. Therefore, the location of the output pole will be dominated by the load resistance. The stability of the system is easy to guarantee. The bulk terminals of the power MOSFETs are connected to the highest potential (HVD D) in the chip to
eliminate reverse current. But the large source-bulk voltage will increase the threshold voltage of the power MOSFETs M14and
M24 because of the body effect. Fig. 19 shows the additional
bulk bias circuit at the power stage. The bulk terminals of tran-sistors M14 and M24 are biased to their source terminal when
M14 and M24 are turned on. Therefore, the smaller size of the
power MOSFETs has the sameON-resistance due to the smaller VT H in (23). When M14 and M24 are turned off, their bulk
terminals are biased to HVD D to eliminate the reverse current
RO N =
1
µCOX(W/L) (VG S− VT H)
. (23)
D. ABS Circuit
The low-voltage ABS circuit is necessary to drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. In order to bias the body of p-MOSFET with the max-imum voltage to fully turn off p-MOSFET, Fig. 20(a) shows the schematic of an ABS circuit. The gate of the transistor M7 is
clamped to VBAT. If the value of VBAT is larger than that of
VO U T, then the drain of the transistor M7 will be pulled low.
After the operation of the inverter chain and level shifter, HVD D
can be rapidly switched to VO U T. As shown in Fig. 20(b),
ex-perimental results demonstrate that power dissipation is better than that of the previous design [19] by about 54% after the test of triangular and square waveforms. There are two output
nodes, HVD D and HVC LK, in this circuit. HVD D supplies the
power MOSFETs and HVC LKsupplies the driver circuit.
E. Nonoverlap Circuit
Fig. 21 shows the nonoverlap circuit for the driver of power MOSFETs, also called the dead-time controller. It is used to avoid the shoot-through current in the power MOSFETs. The NAND gates ensure that there is no overlapping between the phases ϕ1 and ϕ2. The transmission gate TG0is used to ensure
the same delay time as that of the inverter INV0. Hence, the
size of TG0 should be equal to the size of INV0. The
mini-mum delay time can be achieved by using the optimini-mum fan-out value “e” (=2.71) for each stage in the driving chain. How-ever, the minimum delay time is not essential to this charge pump circuit [20], [21]. The rising/falling and the nonover-lapping time are required to be determined in this circuit. In general, long delay time may cause the accuracy problem of the switched-capacitor circuit at the sensor stage. The larger fan-out will cause the longer delay time in the driving chain [22]–[24]. Fig. 22 shows the delay time between the phases ϕ1and ϕ2at all
corners when the minimum battery and output voltages are 2.9 and 5 V, respectively. The different corners may produce the dif-ferent rising/falling times and cause difdif-ferent delay times. The maximum delay time does not exceed 3.61 ns. The maximum rising time is 0.9 ns at the SS corner.
IV. EXPERIMENTALRESULTS
The proposed dual-phase charge pump circuit was fabricated in TSMC double-poly quadruple-metal 0.35-µm CMOS tech-nology. The threshold voltages of nMOSFET and pMOSFET are 0.55 and 0.65 V, respectively. The chip micrograph is shown in Fig. 23 and the total silicon area is about 1615 µm× 1520 µm, including the testing pads. The dual-phase charge pump circuit can operate from 2.9 to 5.5 V with a regulated output voltage of 5 V. The summary of the performance is shown in Table II. Fig. 24 shows the regulated output voltage. The waveforms of the two terminals of the charge pump capacitor demonstrate the correctness of the proposed circuit. Due to the large parasitic resistance, the regulated output voltage is about 5.1 V. Fig. 25 shows the load transient response when load current changes
Fig. 20. Comparator is used to select the maximum potential for driving the bulk of the power p-type MOSFETs. (a) Schematic of the ABS circuit. (b)Experimental results demonstrate the low-power and high-accuracy characteristics of the ABS circuit.
from 4 to 48 mA or vice versa. The output ripple is smaller than 7mVP-P, which is effectively reduced by the proposed
dual-phase charge pump circuit. The measured output ripple of the charge pump with voltage-mode control methodology is about 60mVP-P. Thus, the output ripple of the dual-phase charge
pump is much smaller than that of the voltage-mode charge pump. The response time is about 20 µs, which is smoothly ris-ing and fallris-ing in relation to regulated output voltage. It means that the phase margin is enough during the transient load condi-tion since the current-mode control methodology is applied to the proposed dual-phase charge pump. Furthermore, the over-shoot and underover-shoot voltages in the proposed charge pump disappear during load transient, when it compares with the load transient in the voltage-mode charge pump. The drop voltage is about 60 mV due to the large parasitic resistance of the bonding and PCB wires. Fig. 26 demonstrates the driving capability of the proposed circuit to be about 48 mA. When the load current
Fig. 21. Driver with nonoverlapping clocks for turning on/off the power MOSFETs.
is higher than 48 mA, the output voltage drastically decreases due to the unregulated results. When the load current is smaller than 48 mA, the efficiency decreases and is proportional to the increase in the input voltage, which is described by the charge pump theory. The efficiency is shown in Fig. 27.
Fig. 22. Nonoverlapping time between phase ϕ1and ϕ2at all process corners.
Fig. 23. Chip micrograph.
TABLE II
SUMMARY OF THEPERFORMANCE
Fig. 24. Measured waveforms of VO U Tand the two terminals of the
charge-pump capacitor. (VB AT= 3 V, IO U T = 20 mA).
Fig. 25. Load transient waveform when VB AT = 3.0 V and IO U T change
from 4 to 48 mA, or vice versa.
Fig. 26. Output voltage versus load current at different supply voltages (VB AT= 2.9–5.5 V).
Fig. 27. Efficiency versus input voltage at different load currents (IL O A D=
4–48 mA).
V. CONCLUSION
A dual-phase charge pump circuit by using switched-capacitor-based bandgap reference and current-mode control
ABS circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that this charge pump can provide 48 mA maximum load current without any oscillation problem.
ACKNOWLEDGMENT
The authors would like to thank Chunghwa Picture Tubes, Ltd., for their help.
REFERENCES
[1] T. Simunic, “Dynamic management of power consumption,” in Power
Aware Computing. Norwell, MA: Kluwer, 2002, pp. 101–125. [2] F. Bedeschi et al., “A low-ripple voltage tripler,” in Proc. IEEE Int. Symp.
Circuits Syst., 2006, pp. 2753–2756.
[3] H. Lee and P. K. T. Mok, “Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler,” IEEE J.
Solid-State Circuits, vol. 40, no. 5, pp. 1136–1146, May 2005.
[4] T. R. Ying, W.-H. Ki, and M. Chan, “Area-efficient CMOS charge pumps for LCD drivers,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1721– 1725, Oct. 2003.
[5] K.-S. Min, Y.-H. Kim, J.-H. Ahn, J.-Y. Chung, and T. Sakurai, “CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits,” in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 5, pp. V-545–V-548.
[6] J. A. Starzyk, Y.-W. Jan, and F. Qiu, “A DC–DC charge pump design based on voltage doublers,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 350–359, Mar. 2001.
[7] C.-C. Wang and J.-C. Wu, “Efficiency improvement in charge pump cir-cuits,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 852–860, Jun. 1997.
[8] J.-Y. Lee, S.-E. Kim, S.-J. Song, J.-K. Kim, S. Kim, and H.-J. Yoo, “A regulated charge pump with small ripple voltage and fast start-up,” IEEE
J. Solid-State Circuits, vol. 41, no. 2, pp. 425–432, Feb. 2006.
[9] LTC1733: Monolithic Linear Lithium-Ion Battery Charger with Thermal
Regulation. (2001). Linear Technology, Milpitas, CA. [Online]. Available:
http://www.linear.com/
[10] E. Bayer, H. Schmeller, and G. Sporer, “Charge pumps become differen-tiated,” in Proc. Wireless Symp. Portable Des., 2000, pp. 1–8.
[11] TPS6012X: Regulated 200-mA High Efficiency Charge Pump DC/DC
Converter. (2000). Texas Instruments, Inc., Dallas, TX. [Online].
Avail-able: http://www.ti.com/
[12] E. Bayer and H. Schmeller, “Charge pump with active cycle regulation-closing the gap between linear and skip modes,” in Proc. IEEE 31st Annu.
Power Electron. Spec. Conf., 2000, vol. 3, pp. 1497–1502.
[13] G. Thiele and E. Bayer, “Current mode charge pump: Topology, modeling and control,” in Proc. IEEE 35th Annu. Power Electron. Spec. Conf., 2004, vol. 5, pp. 3812–3817.
[14] B. R. Gregoire, “A compact switched-capacitor regulated charge pump power supply,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1944– 1953, Aug. 2006.
[15] R. J. Widlar, “New developments in IC voltage regulators,” IEEE J.
Solid-State Circuits, vol. SC-6, no. 1, pp. 2–7, Feb. 1971.
Electron., vol. 23, no. 1, pp. 180–188, Jan. 2008.
[22] A. Cabrini, L. Gobbi, and G. Torelli, “A theoretical discussion on perfor-mance limits of CMOS charge pumps,” in Proc. Eur. Conf. Circuit Theory
Des., 2005, vol. 2, pp. II/35–I/38.
[23] A. Cabrini, A. Fantini, and G. Torelli, “High-efficiency regulator for on-chip charge pump voltage elevators,” Electron. Lett., vol. 42, pp. 972–973, Aug. 2006.
[24] C. Boffino, A. Cabrini, O. Khouri, and G. Torelli, “High-efficiency control structure for CMOS flash memory charge pumps,” in Proc. IEEE Int.
Symp. Circuits Syst., May 2005, vol. 1, pp. 121–124.
Ming-Hsin Huang was born in Kaohsiung, Taiwan,
in 1978. He received the B.S. degree from the Depart-ment of Industrial Education and Technology, and the M.S. degree from the Department of Electrical Engi-neering, National Changhua University of Education, Changhua, Taiwan, in 2000 and 2002, respectively. He is currently working toward the Doctorate degree in the Department of Electrical and Control Engi-neering, National Chiao Tung University, Hsinchu, Taiwan.
His current research interests include power IC and switching power supply.
Po-Chin Fan received the B.S. degree from the
De-partment of Power Mechanical Engineering, National Tsing Hua University, Hsinchu, Taiwan, in 2004, and the M.S. degree from the Department of Electrical and Control Engineering, National Chiao Tung Uni-versity, Hsinchu, in 2007.
He is currently with the Department of Electrical and Control Engineering, National Chiao Tung Uni-versity. His research area includes many projects of LED driver ICs and power management ICs at the Low-Power Mixed Signal Laboratory. His current re-search interests include power management circuit designs, LED driver ICs, and analog IC designs.
Ke-Horng Chen (M’04) received the B.S., M.S., and
Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC Designer at Philips, Taipei. From 1998 to 2000, he was an Ap-plication Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was engaged in designing power manage-ment ICs. He is currently an Associate Professor in the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 70 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display (LCD) TV, red, green, and blue (RGB) color sequential backlight de-signs for optically compensated bend (OCB) panels, and low-voltage circuit designs.
