新式非揮發性記憶體元件之研究(I)

新式非揮發性記憶體元件之研究(I)

計畫類別： 個別型計畫

計畫編號： NSC94-2215-E-009-086-

執行期間： 94 年 08 月 01 日至 95 年 07 月 31 日

執行單位： 國立交通大學電子工程學系及電子研究所

計畫主持人： 荊鳳德

報告類型： 精簡報告

處理方式： 本計畫可公開查詢

中 華 民 國 95 年 8 月 4 日

行政院國家科學委員會專題研究計畫 成果報告

新式非揮發性記憶體元件之研究(I)

計畫類別： 個別型計畫 計畫編號： NSC 94-2215-E-009-086-執行期間： 94 年08 月01 日至95 年07 月31 日 執行單位： 國立交通大學電子工程學系暨電子研究所 計畫主持人： 荊鳳德 報告類型： 完整報告 處理方式： 本計畫可公開查詢

中 華 民 國 95 年8 月2 日

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新式非揮發性記憶體元件之研究(I)

計畫類別：■ 個別型計畫

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計畫編號：NSC

94-2215-E-009-086-執行期間： 94 年 8 月 1 日至 95 年 7 月31 日

計畫主持人：荊鳳德

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中 華 民 國 九十五 年 七 月 二十七 日

行政院國家科學委員會研究計畫成果報告

新式非揮發性記憶體元件之研究(I)

計畫編號: NSC

94-2215-E-009-086-執行期限：94年8月1日至 95年7月31日

主持人：荊鳳德 教授 執行單位：交通大學電子工程系 中文摘要 使用具有高捕陷能力的新穎材料 AlN (k=10), 利用在高介電值層有較低壓降以及 使 用 高 功 函 數 的 IrO2 來 降 低 漏 電 流 , SiO2/AlN/HfAlO(k=17)/IrO2 元件, 在 85 。 C 時展現了良好的記憶體特性，以及 100us 的 erase 速度, 在 13V 的 program/erase 低操作 電壓下, ΔVth可達 3V, 利用外插的方式, 經 過十年的保持, 記憶體的 window 仍可維持 1.9V, 若將 erase 的速度降低為 1ms, 則 ΔVth 可達到 5.5V, 在 85。 C 十年的保持情況下, 記 憶體的 window 將增加為 3.4V。 一、簡介

Fundamental challenges for advanced non-volatile memory are the continuous down-scaling program/erase (P/E) time and operation voltage, while still maintaining good 10 years data retention. Although the MONOS memory provides a potential solution for down-scaling the gate oxide beyond conventional floating gate memory, further performance improvements with larger ΔVth of charge-tapping in nitride and faster erase time at low voltage are required [1]-[4]. Of the known high-dielectrics, AlN has a better charge-trapping capability than Si3N4

and Al2O3 as well as unique P/E memory

characteristics [5]. In this paper, we report the memory performance of novel IrO2

-HfAlO-AlN-SiO2-Si MONOS device. At ±13V and

fast 100us P/E, we found a large ΔVth of 3.7V that extrapolated to 1.9V for 10-year retention at 85。C. The 85。C initial ΔVth and 10-year retention window further increase to 5.5V and 3.4V for 1ms erase. Such fast P/E also gives large 105-cycled ΔVth window due to small stress on tunnel SiO2. The good retention is

due to the strong Al-N ionic bond related higher trapping capability. The very fast 100us erase is owing to the high electric field (E) over tunnel SiO2from D (0E) continuity

of high-HfAlO (=17) barrier and AlN (=10) trapping layer. The low P/E voltage is from the efficient charge-trapping AlN, very high 3.5fF/um2capacitance density for charge storage, large E field in SiO2 and high

workfunction IrO2metal gate [6] for low gate

carrier injection during erase. These results are among the best reported data [1]-[4] summarized in Table 1.

二、實驗步驟

The IrO2-HfAlO-AlN-SiO2-Si devices were

formed by first growing a 2.8 nm thermal SiO2, depositing 12 or 16 nm AlN by PVD [5],

13 nm HfAlO by ALCVD, 50nm IrO2

metal-gate [6], followed by gate definition, self-aligned ion-implantation and 85。C RTA. The fabricated devices were characterized by P/E, cycling and retention tests at 85。C.

of SiO2/AlN/HfAlO/IrO2 devices. The strong

trapping AlN can reduce the P/E voltage even for thin AlN. The 5.1eV high workfunction [6] is important to scale down the HfAlO thickness and erase voltage. This is evidenced from the 1 order of magnitude lower Jg in Fig. 2 than a previous report of a similar structure [3] also under -10 to -15V erase. This is consistent with the >10X lower Jg in IrO2/high-pMOS than mid-gap metal-gate

device [6]. The C-V hysteresis curves, in Fig.3, show very large ΔVth shifts of 7-10V. The capacitance further increases to 3.5 fF/um2 for 12nm AlN MONOS to give large charge storage at low voltage. The detailed P/E characteristics from Id-Vg are shown in Figs. 4-5 for thicker 16nm AlN MONOS. A fast P/E time of 100us-1ms are measured at ±13V, with a large ΔVth shift. The ΔVth and P/E speed are improved using the thinner 12nm AlN MONOS. As shown in Figs. 6-7, the 13V 100us program gives 3.3V ΔVth change and the -13V 100us erase has -3.7V ΔVth. Even a ΔVth shift of 2.1V and -1.8V is obtained at 10us and ±13V P/E. Such very fast erase is ~10X better than published data [1]-[4] with larger ΔVth. It arises from the higher electric field in thin 2.8nm SiO2due to

a smaller voltage drop in small EOT high- HfAlO (=17) barrier and trapping AlN (=10) from0E continuity. The high work-function

IrO2 gate [6] also helps the erase by largely

reducing charge injection from gate with thin HfAlO.

B. Retention & Cycling:

Figs. 8-10 show the retention data. The

was obtained for 100us or 1ms erase and 100us program at ±13V. This is above the best reported data [1]-[4] in Table 1. Besides, the 85oC highand low-level retention decay rate of 120 and only 64mV/dec are comparable with published data [1]-[4], with added merit of the largest initial ΔVth of 5.5V (3.7V) at 1ms (0.1ms) -13V erase. This large memory window arises form the strong Al-N ionic bond to give better trapping capability than Al2O3and Si3N4. Good endurance is also

obtained in Figs. 11-12. At 85oC and ±13V, big 105-cycled memory window of 2.9 or 4.6V and 10k-cycled 10-year retention window of 1.6 or 2.7V are obtained at 0.1ms or 1ms erase. Such excellent endurance is due to the fast P/E time with less stress to tunnel SiO2. Table 1 summarizes the important

memory data. At 85oC and ±13V P/E, good memory integrity of fast 100 to 1000us erase time, large ΔVth of 3.7 or 5.5V, big 105-cycled ΔVth of 2.9 or 4.6V, and good retention of large 10-year memory window of 1.9 or 3.4V are obtained at the same time in this MONOS device.

四、結論

Fast erase, large ΔVth, good retention and cycling are simultaneously obtained in SiO2/AlN/HfAlO/IrO2devices.

五、參考文獻

[1] M. Specht et al, Symp. On VLSI Tech Dig. (2004), p.244.

Fig.1. Band diagram of IrO2-HfAlO-AlN-SiO2-Si MONOS

memory in erase state. The higher work-function IrO2allows

thinner HfAlO w/o large electron injection into AlN.

-4 -2 0 2 4 6 8 0 1 2 3 V_thShift Initial V_th -15V 15 V -14V 14 V -13V 13 V -12V 12 V -11V 11 V C a p a c it a n c e D e n s it y (f F /  m 2 ) Bias (V)

Fig.3. C-V hysteresis curves of MONOS capacitor with 16nm

AlN for various Vg. The capacitance density increases to

3.5fF/μm2_{for 12nm AlN device.}

10-7 ₁₀-6 _{1 0}-5 _{1 0}-4 ₁₀-3 ₁₀-2 _{1 0}-1 ₁₀0 -3 -2 -1 0 1 2 3 4 5 Vers= -9V V er s= -10V V er s= -11V Ver s= -12V Vers=-13V V er s= -14V Ver s= -15V Vth ( V ) E ras e T im e (s ec)

Fig.5. Erase characteristics of MONOS memory with 16nm

AlN.Thedevicewasinitially programmed at13V for100μs.

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 -3 -2 -1 0 1 2 3 4 5 6 V ers = -9V V e rs= -10 V V ers =-11V V ers =-12V V ers =-13V V ers =-14V V ers =-15V Vth ( V )

E ras e Tim e (sec)

Fig.7. Erase characteristics of MONOS memory with 12nm

AlN.Thedevicewasinitially programmed at13V for100μs.

0 -5 -1 0 -1 5 -2 0 1 0-1 0 1 0-8 1 0-6 1 0-4 1 0-2 1 00 1 x 1 0-6 A /c m2 @ -1 0 V fo r 1 6 n m 1 x 1 0-5 A /c m2 @ -1 0 V fo r 1 2 n m 2 x 1 0- 4 A /c m2 @ -1 5 V B ia s (V ) L e a k a g e C u rr e n t (A /c m 2 ) M O N O S w ith 1 2 n m A lN 1 6 n m A lN 2 50 C 2 50 C 8 50_{C 8 5}0_C

Fig.2. Jg-Vgcurves of MONOS memory with 12nm and 16nm

AlN at 25 and 85℃ The Jgis 1 order of magnitude lower than

the data from [3] due to higher ΦBof IrO2.

10-7 10-6 10-5 10-4 10-3 1 0-2 1 0-1 100 2 3 4 5 6 7 8 9 In itial V_th V_{p ro g}= 9 V V_{pro g}= 14V V_{p ro g}= 10 V V_{pro g}= 15V V_{p ro g}= 11 V Vp ro g= 12 V V_{p ro g}= 13 V Vth ( V )

P rog ra m Tim e (se c)

Fig.4. The measured program characteristics from Id-Vg for

16nm AlN MONOS devices. The Lgis10μm.

10-7 1 0-6 1 0-5 10-4 10-3 10-2 10-1 1 00 2 3 4 5 6 7 8 9 In itia l V_th Vprog= 9V Vp rog=1 4V V prog= 1 0V Vp rog=1 5V Vprog= 1 1V Vprog= 1 2V V prog= 1 3V Vth ( V ) P ro g ra m T im e (se c)

Fig.6. The measured program characteristics of MONOS with 12nm AlN. 1 00 _{1 0}1 _{1 0}2 _{1 0}3 _{1 0}4 _{1 0}5 _{1 0}6 _{1 0}7 _{1 0}8 _{1 0}9 0 1 2 3 4 5 6 2 .8 V L o w le ve l H ig h le ve l 2 2 m V /d e c 7 2 m V /d e c 3 .8 V 1 0 y e a rs P ro g ra m : 1 3 V 1 0 0s E r a s e : -1 2 V 1 m s P ro g ra m : 1 3 V 1 0 0s E r a s e : -1 3 V 1 m s Vth (V ) R e te n tio n T im e (s e c )

Fig.8. Retention of MONOS devices with 16nm AlN at 25℃. The P/E decay rates are only 72/22 mV/dec.

100 1 01 1 02 103 1 04 105 106 107 108 109 -1 0 1 2 3 2.4V P ro gra m : 13V 10 0s E ra se: -13V 1m s 4 9m V /de c 4 .1 V 10 years Vth (V )

R ete ntio n T im e (s ec)

Fig.9. Retention of MONOS devices with 12nm AlN at 25℃ The P/E decay rates are 92/49 mV/dec.

Fig.11. Endurance of MONOS memory with 12nm AlN at

85℃.High ΔVth can bemaintain up to 105_P/E. 100 101 102 103 104 105 106 107 108 109 -2 -1 0 1 2 3 M O N O S w ith 16nm AlN 13V 100s/-13V 1m s 2.3V 1.9V 13V 100s/-13V 100s 13V 100s/-13V 1m s

Retention Tim e (sec)

Vth

(

64m V /dec 3.4V

10 years

Fig.10. Retention of MONOS devices with 12nm and 16nm AlN at 85℃. The P/E decay rates are 120/64 mV/dec.

1 00 1 01 1 02 1 03 1 04 105 106 1 07 1 08 1 09 0 1 2 3 4 5 6 15 6 m V /d e c 90 m V /d ec 2.7 V 1.6 V 1 0 ye a rs P ro g ra m : 1 3 V 1 0 0s E ra s e : -13 V 10 0s P ro g ra m : 1 3 V 1 0 0s E ra s e : -13 V 1m s Vth (V ) R e te n tio n T im e (s e c )

Fig.12. Retention of 10k P/E-cycled MONOS devices with 12nm

AlN at 85℃.LargeΔVth of1.6 and 2.7V arestillobtained.

P/E condition for retention & cycling

InitialΔVth (V) @85℃ ΔVth (V)for10-year retention @85℃ 85℃-P/E decay rate (mV/dec) ΔVth @Cycles & 85℃ ΔVth (V)for10-year after 10k cycles @ 85℃ 13V 100μs/ -13V 100μs 3.7 1.9 120 / 52 2.9 @ 105 _1.6 This Work 13V 100μs/ -13V 1ms 5.5 3.4 120 / 64 4.6 @ 105 2.7 Tri-gate [1]

SiO2/Si3N4/SiO2/poly

11.5V 3ms/ -11.5V 100ms 1.2 1.1 (@25℃ only) 12.5 /12.5 (@25℃ only) 1.5 @ 104 (@25℃) No data FinFET [2]

SiO2/Si3N4/SiO2

13V 10μs/ -12V 1ms 5 2.9 60 / 150 4.2 @ 104 _{No data} SiO2/Si3N4/ Al2O3/TaN [3] 13.5V 100μs/ -13V 10ms 4.4 2.07 140 / 75 4 @ 105 _1.36