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Fabrication of Novel Three-Step Drift-Doped Low-Temperature Polycrystalline Silicon Lateral
Double-Diffusion Metal–Oxide–Semiconductor Using Excimer Laser Crystallization
View the table of contents for this issue, or go to the journal homepage for more 2009 Jpn. J. Appl. Phys. 48 031204
(http://iopscience.iop.org/1347-4065/48/3R/031204)
Fabrication of Novel Three-Step Drift-Doped Low-Temperature
Polycrystalline Silicon Lateral Double-Diffusion
Metal–Oxide–Semiconductor Using Excimer Laser Crystallization
Jyh-Ling Lin, Huang-Jen Chen, Fang-Long Chang1, and Huang-Chung Cheng1 Department of Electronic Engineering, Huafan University, Shintin, Taipei 223, Taiwan1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan Received September 1, 2008; accepted December 6, 2008; published online March 23, 2009
Low-temperature polycrystalline silicon (poly-Si) thin-film transistor lateral double-diffusion metal–oxide–semiconductor field-effect transistors (LTPS TFT LDMOSFETs) and lateral insulated-gate bipolar transistors (LIGBTs) were fabricated by combining a thin-film transistor with a power structure, three-step drift doping, and excimer laser annealing. The maximum breakdown voltage of the three-step drift-doped LTPS-LDMOS after excimer laser annealing is 286 V with a 35 mm drift region length (Ldrift). The specific on-resistance is low (approximately 9 cm2) and the ON/OFF current ratio is about 1:28 106with L
drift¼15 mm. The subthreshold swing (SS) is about 1 V/ decade. Comparing the three-step drift-doped LDMOS with the three-step drift-doped LIGBT under the same processing conditions clearly indicates that the breakdown voltage and current capacity of LIGBT exceeds those of LDMOS.
#2009 The Japan Society of Applied Physics
DOI: 10.1143/JJAP.48.031204
1. Introduction
Recently, power devices and related products have been continuously studied and improved for applications in many fields. In particular, lateral power devices are continuously being developed to improve system-on-chips (SOCs) and to facilitate integration with other circuits in the complemen-tary metal–oxide–semiconductor (CMOS) process. Lateral power devices include conventional lateral double-diffusion metal–oxide–semiconductors (LDMOSs), super-junction LDMOSs, and lateral insulated-gate bipolar transistors (LIGBTs), among others.1–5)LDMOS is a voltage-controlled
device with a gate control circuit that is simple and suitable for integration. LIGBT has the high input impedance of an MOS-gate structure and a higher overall current density during forward conduction than power MOS field-effect transistors (MOSFETs).
In recent years, low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been widely studied and discussed for devices such as active-matrix liquid crystal displays (AMLCDs), active-matrix organic light-emitting displays (AMOLEDs), and plasma display panels.6–9) Accordingly, the requirement for high-voltage
circuits in these devices has increased. Thus, low-temper-ature poly-Si high-voltage TFTs (LTPS HVTFTs) will become increasingly important in the future as system-on-panel (SOP) and three-dimensional (3D) circuits are inte-grated.
In this investigation, LTPS-LDMOS and LTPS-LIGBT were implemented in three steps of doping and by combin-ing silicon-on-insulator (SOI), low-temperature thin-film transistor technology and a power device, with the structure shown in Fig. 1. A linear doping profile in the drift region is necessary to provide a more uniform electrical field distribution and to yield a high breakdown voltage. To obtain a linear doping profile in the drift region, a sequence of small opening oxide slits, called the variation in lateral doping (VLD) technology, is used. However, this technology has some shortcomings: for example, it requires a complex
mask layout and a long annealing time to ensure linear doping.10,11) In 1995, Sunkavalli et al. used the distinct
doping region along the lateral direction to replace the linear profile in the drift region.12) Subsequently, some numerical analyses (including that performed by our group) yielded models that can optimize the doping profile, step-doping number, and thermal process time.13,14)
A structure with a step doping profile in the drift region shows a high performance in LDMOSFETs.15)Thus, in this
work, three doping steps in the drift region were designed and excimer laser crystallization (ELC) and solid phase crystallization (SPC) were performed to crystallize amor-phous silicon (a-Si) in an LDMOSFET and an LIGBT fabricated on the same oxide substrate. ECL is the most promising technique for growing large poly-Si grains and it cannot cause damage to the glass substrate because of a large
(a)
(b)
Fig. 1. Structure of (a) LTPS-LDMOS and (b) LTPS-LIGBT.
absorption coefficient for a-Si in the UV light region (optical absorption coefficient > 106cm1).16–19)The grain boundary
causes many defects, which act as trap states in the band gap and degrade the electrical characteristics of devices, such as threshold voltage, mobility, and subthreshold swing. In this work, we focused on the study of LTPS-LDMOSFETs and compared LDMOS with LIGBT.
2. Device Fabrication
The key processes in the fabrication of LTPS-LDMOS are as follows. Step 1: grow a 1-mm-thick layer of thermal oxide on a (100) silicon wafer, replacing the glass substructure. Step 2: deposit amorphous silicon to a thickness of 1000 A˚ on the oxide with pure silane (SiH4) by low-pressure
chemical vapor deposition (LPCVD) at 550C to form the
device active layer. Step 3: use ion implantation to produce the p-well and n-buffer to increase the size of the depletion region, using a boron dose of 3:0 1013cm2at 60 keV and a phosphorous dose of 3:0 1013cm2 at 60 keV. In the drift region, three doping steps were adopted to produce a linearlike doping profile, reducing drift region resistance. The implantation phosphorus doses are 2:3 1011, 7:0
1011, and 1:3 1012cm2at 50 keV. The n-buffer layer, the
drift region, and the p-well form the punch-through diode, reducing the surface-field (RESURF) effect and increasing the integration area of the electric field. Step 4: crystallize the 1000-A˚ -thick layer of amorphous silicon using a KrF excimer pulse laser ( ¼ 248 nm) with an optimal laser energy of 430 mJ/cm2 and 100 shots per cm2with substrate
heating at 400C in a vacuum chamber of 103Torr. It was
found that a large grain size could be realized by controlling the solidification of silicon under these conditions.19,20)
Figure 2 shows a scanning electron microscopy (SEM) image of poly-Si. Step 5: deposit a 3000-A˚ -thick layer of tetraethylorthosilicate (TEOS) as the field oxide (FOX) by LPCVD. FOX can reduce the surface electric field between the gate and the anode edge in the drift region. Step 6: deposit a 1000-A˚ -thick layer of TEOS as the gate oxide by LPCVD and a 2000-A˚ -thick layer of amorphous silicon as the gate electrode by LPCVD at 550C. Step 7: implant
phosphorus at 5:0 1015cm2 and 60 keV to form the n+
source and drain, and improve the conductivity of the gate. Step 8: deposit a 5000-A˚ -thick TEOS layer as a passive oxide layer by LPCVD and then activate all dopants by furnace annealing at 600C for 12 h. Finally, deposit four
metals (Ti/TiN/AlSiCu/TiN) on the passive oxide as
contact metals by metal-CVD. The thickness of the metal layer should be fixed at 6000 A˚ .
3. Results and Discussion 3.1 Electrical characteristics
Figure 3 shows the basic output characteristics of ELC LTPS-LDMOS. The drain current is about 0.35 mA at Vds ¼50 V and Vgs¼25 V. The device dimensions and
doping concentration are W ¼ 600 mm, Lch¼9 mm, Ldrift¼
15 mm, Ndrift-step¼2:3 1011, 7 1011, and 1:3 1012
cm2, Tsi¼0:1 mm, and Tbox¼1 mm. Figure 4 shows the
breakdown voltages of uniform and step doping in the drift region as a function of drift region length with Lch¼15 mm
at Vg¼0 V. The breakdown voltage varies with the length
of the drift region. When the drift region was extended, the breakdown voltage of uniform doping increased from about 160 to 280 V at a fixed channel length (Lch) of 15 mm,
following a linearity of about 4.8 V/mm. The breakdown voltage of step doping also increased from about 180 to 300 V. This phenomenon is also clearly observed with other channel lengths. The results clearly show that devices with three-step doping provide a more uniform electrical field distribution along the drift region with higher breakdown voltages than uniformly doped devices.
Fig. 2. SEM of excimer laser-crystallized poly-Si at laser density of 430 mJ/cm2with substrate heating at 400C.
0 10 20 30 40 50 0.0 0.1 0.2 0.3 0.4 0.5 W/Lch=600um/9um Ldrift=15um TSi=0.1um Tbox=1um
step doping condition
Step1=2.3 1011cm-2 Step2=7 1011cm-2 Step3=1.3 1012cm-2 Drain Current, Id (mA) Drain Voltage, Vds (V) Vgs=35V Vgs=30V Vgs=25V Vgs=20V
Fig. 3. Output characteristics of ELC LTPS-LDMOS with three-step doping. 15 20 25 30 35 40 140 160 180 200 220 240 260 280 300 320 Step Doping: Step1=2.3 1011cm-2 Step2=7 1011cm-2 Step3=1.3 1012cm-2 Uniform Doping: Ndrift=7 1011cm-2 Breakdo wn V olta g e (V)
Drift Region Length (μm) Uniform Doping
Step Doping
W/Lch=600um/15um Tsi=0.1um Tbox=1um
Fig. 4. Breakdown voltages of uniform and three-step doping drift regions versus length of drift region.
Figure 5 shows specific on-resistances (Ron,sp) for various
drift lengths and doping profiles. The specific on-resistances were defined as Ron,sp ¼ Vds Id ½W ðLchþLdriftÞ;
where W, Lch, and Ldrift represent the device width,
channel length, and drift region length, respectively. Vds
and Id are the drain–source voltage and its corresponding
drain current in the triode region, respectively. The gate-source voltage was set at Vgs¼30 V. The specific
on-resistances of step doping increased from about 9 cm2 to 2.5 k cm2 when the drift region length ranged from 15 to 40 mm, and they were clearly lower than those of uniform doping.
Excimer laser annealing crystallizes silicon thin film from amorphous to single-crystal material within a very short time by melting the silicon. The amorphous thin film is heated to a temperature of about 1200C during laser
irradiation for approximately 10 ns. The thin film rapidly melts and solidifies, without thermal damage to the substrate, thermal compaction problems, or impurity diffu-sion from the substrate to the silicon thin film. Thus, this technology yields high-quality and large-grained poly-Si thin films for LTPS LDMOSs on glass substrates. The performance of poly-Si thin film has been shown to be related to the initial status of a-Si precursor film and the ELC conditions, such as laser energy density, laser pulse duration, laser shot number per area, ambient, and substrate temper-ature.20–23)If the process and excimer laser systems exhibit optimal conditions, the specific on-resistance of uniformly doped LTPS LDMOS may be reduced to about 0.54 cm2,
which is only five times higher than that of single-crystalline silicon LDMOS, with the same order of block capability.19)
In this study, uniformly doped and three-step-doped LTPS LDMOSs were manufactured by the same process within the same time. The performance of specific on-resistance is lower than that reported in our previous paper. However, three-step doping could clearly improve block capability and on-resistance even in LTPS LDMOSs. Thus, a high-performance LTPS-LDMOS with a low specific on-resist-ance of less than 0.54 cm2 can be realized.
Figure 6 shows four gate transfer curves of TFT-LDMOS between SPC and ELC for uniform and three-step doping. The SPC process temperature was maintained at 600C in
N2 ambient and the process time was about 24 h. The drain
current of the TFT-LDMOS fabricated by ELC and step doping was about 0.8 mA at Vds ¼30 V and Vgs¼50 V. The
negative gate bias current was almost constant even as the drain voltage was increased to 30 V, because the extended gate and drift region design effectively reduced the junction electric field in the p-well and the n-drift region.14)The ON/
OFF current ratio of step doping was 2:06 105 higher than
that of uniform doping after laser treatment. The subthres-hold swing (SS) of the three-step drift-doped LTPS-LDMOS was about 1 V/decade, showing a low number of deep states in polysilicon.24)
3.2 Uniformity
In this section, the uniformity of excimer laser treatment for three-step drift-doped LTPS LDMOSFETs is discussed. Figure 7 shows the percentage distribution of variation voltage for maximum transconductance under different drift region lengths. For each length, five devices were taken from different regions (A, B, C, D, and E) of the same wafer. The devices were fixed at 15 mm channel length. The trans-conductance is defined as
gm¼
@Id
@Vgs
;
where Vdsis fixed at 10 V. The corresponding voltage of gm
maximum is Vgs,max¼Vgs @gm @Vgs ¼0 : The percentage of variation voltage is taken from
% ¼Vgs,maxVgs,ave Vgs,ave
ð%Þ;
where Vgs,ave is the average voltage of Vgs,max for a fixed
drift region length. In Fig. 7, the variation in maximum transconductance is less than 5% for a 25 mm channel length. 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Specific On-Resistance ( K Ω cm 2 )
Drift Region Length (μm)
Step Doping Uniform Doping Step Doping: Step1=2.3 1011cm-2 Step2=7 1011cm-2 Step3=1.3 1012cm-2 Uniform Doping: Ndrift=7 1011cm-2 W/Lch=600um/15um Tsi=0.1um Tbox=1um
Fig. 5. Specific on-resistances of uniform and three-step doping drift regions versus length of drift region.
-40 -20 0 20 40 10-9 10-8 10-7 10-6 10-5 10-4 10-3 SPC After Laser Treatment
W/Lch=600um/9um Ldrift=25um Tsi=0.1um Tbox=1um Vds=30V step doping uniform doping step doping uniform doping
Drain Current, Id (A)
Gate Voltage, Vgs (V)
Fig. 6. LTPS-LDMOS transfer characteristics of SPC and ELC for uniform and three-step doping with Ldrift¼25 mm and Lch¼9 mm.
Figure 8 shows the corresponding breakdown voltage distribution. The breakdown voltage variation is small when the drift region length is 15 mm. However, the variation clearly increases when the drift region length exceeds 25 mm. Although excimer laser crystallization has the potential to improve the crystallinity of poly-Si thin films, the narrow excimer laser crystallization process window and the uniformity of the crystallized poly-Si thin films are serious problems. In addition, the shot-to-shot laser energy of the excimer laser is insufficiently stable and the seeds of crystallization distribute randomly during laser recrystalli-zation. These phenomena cause the excimer laser crystal-lization to result in a poor device-to-device uniformity, particularly for large-area devices. Therefore, the uniformity is a problem when the drift region length exceeds 25 mm and the variation in breakdown voltage is large. These phenom-ena were also observed for specific on-resistance. The distributions of specific on-resistance for various drift region lengths are shown in Fig. 9. The drift region lengths of less than 15 mm have low specific on-resistance and low variation. The variation range increases with drift region length extension.
Regarding the issues mentioned above, many laser crystallization technologies have been proposed to produce
large grains with more uniform distribution, such as phase-modulated ELC, dual beam ELA, continuous-wave laser lateral crystallization, and selectively enlarging laser crys-tallization.25–28) Low-temperature poly-Si thin-film power
devices combining the new technology and new structure that produce large grains to promote uniformity and high performance will be our next topic for investigation. 3.3 Comparison of LDMOSFETs and LIGBTs with
three-step doping
In this section, we compare the performance characteristics of the LTPS-LDMOS and LTPS-LIGBT fabricated on the same wafer. The on current of LTPS-LIGBT exceeds that of LTPS-LDMOS, as shown in Fig. 10, clearly indicating that LIGBT has a high current density. Figure 11 shows the corresponding ON/OFF current ratios for 15, 25, and 35 mm drift region lengths. The ON/OFF current ratios of LTPS-LDMOS are smaller than those of LTPS-LIGBT. The on current of LIGBT with Ldrift¼15 mm is limited by the
measurement system. Figure 12 shows the average break-down voltage and specific on-resistance of LDMOS and LIGBT with Ldrift¼25 mm and Lch¼15 mm. The
break-down voltage and specific on-resistance of LIGBT are improved by about 7 and 90% compared with those of
15 20 25 30 35 40 -40 -30 -20 -10 0 10 20 30 40 A B C D E V ariation V o lta g e P e rcenta g e (%)
Drift Region Length (μm)
Step Doping V
ds=10V Lch=15μm
Fig. 7. (Color online) Percentage distribution of variation voltage for transconductance maximum versus drift region length.
15 20 25 30 35 40 160 180 200 220 240 260 280 300 320 Breakdo wn V olta g e (V)
Drift Region Length (μm)
A B C D E W/Lch=600um/15um Tsi=0.1um Tbox=1um
Fig. 8. (Color online) Statistics and uniformity of breakdown volt-age. Five ELC LTPS-LDMOSs with three-step doping were measured at a fixed drift region length.
15 20 25 30 35 40 0 5 10 15 20 25 30 Specific On-Resistance (K Ω cm 2)
Drift Region Length (μm)
A B C D E minimum: ~9 Ωcm2
Fig. 9. (Color online) Statistics and uniformity of specific on-resist-ance. Five ELC LTPS-LDMOSs with three-step doping were meas-ured at a fixed drift region length.
-80 -60 -40 -20 0 20 40 60 80 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2
Drain, Anode Current (A)
Gate Voltage (V) V drain= 10V at LTPS-LDMOS Vdrain= 30V at LTPS-LDMOS Vanode= 10V at LTPS-LIGBT Vanode= 30V at LTPS-LIGBT 0.01 0.1 1 10
Drain, Anode Current Density (A/cm
2 ) N drift-step=2.3 10 11, 7 1011, 1.3 1012 cm-2 W/Lch=600um/15um Ldrift=35um Tsi=0.1um Tbox=1um
Fig. 10. Transfer characteristics of three-step doped LTPS-LDMOS and LTPS-LIGBT using ELC.
LDMOS, respectively. As we know, insulated-gate bipolar transistors possess superior on-state characteristics, an excellent safe operating area, and a reasonable switching speed. They have replaced bipolar power transistors in medium power applications. However, LDMOS is a unipolar device, so it has a high inherent switching speed. The results presented in this paper reveal that the total DC performance of the LTPS-LDMOS and LTPS-LIGBT using thin films supports integration with other driving circuits on the panel. 4. Conclusions
In this work, we investigated the three-step doping drift region of LTPS-LDMOS and LTPS-LIGBT following excimer laser annealing. The step-doping drift region treated by excimer laser annealing was herein linearly doped instead. The breakdown voltage of LTPS-LDMOS depends on not only the drift region length but also the doping profile. Our research conclusions are summarized as follows:
(1) The maximum breakdown voltage of LTPS-LDMOS reaches about 220 – 300 V when the drift region lengths of the devices are designed to exceed 25 mm. The specific on-resistance is low (about 9 cm2) with
Lch¼15 mm and Ldrift¼15 mm.
(2) The ION=IOFF ratio for three-step doping exceeds that
for uniform doping and the subthreshold swing (SS) is about 1 V/decade.
(3) Comparing the three-step doped LDMOS with the three-step doped LIGBT under the same processing conditions clearly indicates that the breakdown voltage of LIGBT exceeds that of LDMOS.
Acknowledgments
The authors wish to thank the National Nano Device Laboratories (NDL) and National Science Council of the R.O.C., Taiwan for financially supporting this research under Contract no. NSC 95-2221-E-211-021.
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15 20 25 30 35 101 102 103 104 105 106 107 108 be limited 1.42 105 2.93 105 1.28 106 1.59 106 4.69 106 6.12 106 Ndrift-step=2.3 1011, 7 1011, 1.3 1012 cm-2 ELC-LDMOS ELC-LIGBT W/Lch=600um/15um Tsi=0.1um Tbox=1um Vanode&drain=30V
ON/OFF Current Ratio
Drift Region Length (μm)
Fig. 11. ON/OFF current ratios for three-step doped LTPS-LDMOS and LTPS-LIGBT using ELC at Vdrain,anode¼30 V.
200 220 240 260 280 300 Improvement 120% Improvement 7% LIGBT LIGBT LDMOS Breakdo wn V olta g e (V) LDMOS 0 2 4 6 Specific On-Resistance (k Ω cm 2 )
Fig. 12. Breakdown voltage and specific on-resistance improve-ment of three-step doping LDMOS and IGBT with excimer laser crystallization.
