IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 9, SEPTEMBER 1997 417
Thin Oxides with in situ Native Oxide Removal
Albert Chin,
Senior Member, IEEE, W. J. Chen, T. Chang, R. H. Kao, B. C. Lin, C. Tsai, and J. C.-M. Huang
Abstract— We have studied the inversion layer mobility of n-MOSFET’s with thin-gate oxide of 20 to 70 ˚A. Direct relationship of electron mobility to oxide/channel interface roughness was ob-tained from measured mobility of MOSFET’s and high-resolution TEM. By using a low-pressure oxidation process with native oxide removed in situ prior to oxidation, atomically smooth interface of oxide/channel was observed by high-resolution TEM for oxide thicknesses of 11 and 38 ˚A. The roughness increased to one to two monolayers of Si in a 55- ˚A oxide. Significant mobility improvement was obtained from these oxides with smoother interface than that from conventional furnace oxidation. Mobility reduction with decreasing oxide thickness was observed in the 20-and 35- ˚A oxide, with the same atomically smooth oxide/channel interface. This may be due to the remote Coulomb scattering from gate electrode or the gate field variation from poly-gate/oxide interface roughness.
I. INTRODUCTION
B
Y continuously scaling the thickness of gate oxide, both the current drive capability and the transconductance of MOSFET’s increase [1]–[5]. Current drive more than 1.0 mA/ m and transconductance over 1000 mS/mm are re-ported for deep submicrometer MOSFET’s with a 15- ˚A direct-tunneling oxide [4]. This performance can ensure the transis-tors to operate at low battery voltage for portable wireless communication [4], [6]. However, the most important issues for MOSFET made by ultrathin gate oxide are thickness uni-formity and interface smoothness. The interface roughness can strongly affect the carrier transport that can be characterized by measuring the electron mobility in the inversion layer of MOSFET’s [7]–[9]. Furthermore, electron mobility is an important parameter for device modeling and design, and the speed of MOSFET is dependent on the mobility at the low electric field near source. In this letter, we have measured the electron mobility with different interface roughness. Very smooth interface of oxide/Si is achieved by desorbing the native oxide in situ in a low-pressure oxidation system be-fore thermal oxidation. Atomically smooth interface between oxide and Si is observed by high-resolution TEM for oxide thicknesses of 11 and 38 ˚A. The electron mobility dependence on oxide thickness of 20 to 70 ˚A was also measured, and a mobility reduction is observed in thinner oxide.Manuscript received January 17, 1997; revised May 29, 1997.
A Chin, T. Chang, R. H. Kao, B. C. Lin, and C. Tsai are with the Institute of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
W. J. Chen is with the Department of Mechanical Materials Engineering, National Yun-Lin Polytechnic Institute, Huwei, Taiwan, R.O.C.
J. C.-M Huang is with ERSO, ITRI, Hsinchu, Taiwan, R.O.C. Publisher Item Identifier S 0741-3106(97)06675-5.
II. EXPERIMENTAL
To reduce the interface roughness of oxide/Si, we have de-signed a low-pressure oxidation system that can desorb native oxide in situ before oxidation. A leak-tight reactor design and a high flow rate of hydrogen are used to avoid further growth of native oxide after wafer loading. Similar leak-tight technique and native oxide desorbing process have been used for low-pressure chemical vapor deposition (LPCVD) to grow high quality Si epitaxy at 550 C [10]. P-type 4-in [100] Si wafers with typical resistivity of 10 cm are used in this study, and the oxide is grown at 900 C using N O under a reduced pressure of 4.5 torr. The advantages of the low-pressure oxidation are slow oxidation rate for precise thickness control and good thickness uniformity due to increased N O migration length. Ultrathin oxide of 11 ˚A [Fig. 1(b)] can be reproduced and thickness variation less than 1 ˚A is obtained across 4-in wafer for a 20- ˚A oxide. More detailed growth of ultrathin oxide and process flow will be published elsewhere. High-resolution TEM and 100- m wide MOSFET are used to characterize the interface roughness and mobility behavior. To avoid the drain voltage bias dependence, the electron mobility was determined from the drain conductance and the gate-channel capacitance at a low of 50 mV [8]. The effective normal field can be expressed as
(1) where is the inversion layer charge, is the bulk depletion-layer charge and is the permittivity of Si.
III. RESULTS AND DISCUSSION
Fig. 1(a) and (b) show the atomic image of a 38- and 11- ˚A oxide grown in the low-pressure oxidation system with native oxide removed in situ. Atomically smooth interface of oxide/Si can be observed in Fig. 1, and only one atomic layer of Si, just beneath the oxide, is disturbed from its original crystal structure. It is noticed that there are only two Si-atomic layers oxidized to form the ultrathin oxide of 11 ˚A.
We have also grown oxide from conventional furnace for comparison. Fig. 2(a) presents a 55- ˚A oxide grown by a conventional furnace, where both interface waving and roughness up to four to five layers of Si are observed. In contrast, as shown in Fig. 2(b), the interface of oxide/Si is much smoother for the same oxide thickness grown in our system with native oxide removed in situ. The local thickness variation up to one to two Si-atomic layers observed in Fig. 2(b) may be due to the increased thermal stress of the thicker oxide than that shown in Fig. 1.
Based on the smooth oxide/Si interface, we have therefore studied the electron mobility improvement due to reduced
418 IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 9, SEPTEMBER 1997
(a)
(b)
Fig. 1. Cross-sectional TEM images of (a) 38- ˚A oxide and (b) 11- ˚A oxide grown at 900C using N2O under a low-pressure of 4.5 torr. Native oxide is desorbed in situ prior to oxidation.
interface roughness. Wafers with low concentration of impurity doping are used to reduce the ionized impurity scattering in the inversion layer, which dominates the low-field mobility. Fig. 3 shows the measured mobilities with 70- ˚A oxide from con-ventional furnace oxidation and from low-pressure oxidation with native oxide removed in situ, respectively. The measured electron mobility from conventional furnace oxidation follows the universal mobility-field dependence reported in previous papers [7]–[9]; however, significant improvement of mobility is measured from our low-pressure oxidation with a clean surface free of native oxide. It is important to note that both wafers from conventional furnace oxide and low-pressure oxide were fabricated at the same time, and they have the same thickness of poly-gate and doping concentrations at source and drain. Therefore the higher electron mobility measured from low-pressure oxide is not process-related. The improved mobility is due to the reduced interface roughness scattering
(a)
(b)
Fig. 2. Cross-sectional TEM images of 55- ˚A oxide from (a) conventional furnace oxidation at 800C and (b) from low-pressure oxidation with native oxide desorbed in situ.
shown in Figs. 1 and 2, and similar mobility improvement to interface roughness was also reported for the comparison of thermal and deposited oxide [7].
We have also measured the effective mobility as a func-tion of gate oxide thickness, for oxide thicknesses of 20-, 35-, and 70- ˚A, respectively. As shown in Fig. 4, a mobility decrease in the low gate-field region is observed for the 20-and 35- ˚A oxide as compared to the 70- ˚A one. It is well know that the total electron mobility is governed by indi-vidual contributions from phonons, channel doping impurities and interface roughness, where the Coulomb scattering from doping impurities dominates the low-field mobility and the interface roughness dominates the high-field mobility [8], [9]. Therefore interface roughness scattering limits the mobility of modern deep submicrometer devices even though the channel doping is higher than that used in this work [7]. Because the same resistivity of substrates are used, the reduction in low-field mobility is not due to the different concentrations of impurities. Although the decay of mobility as decreasing
CHIN et al.: THIN OXIDES WITH IN SITU NATIVE OXIDE REMOVAL 419
Fig. 3. Electron mobilities of MOSFET’s with 70- ˚A oxide from conventional furnace oxidation and from low-pressure oxidation with native oxide desorbed
in situ.
Fig. 4. Electron mobilities of MOSFET’s as a function of effective field of (a) 70 ˚A, (b) 35 ˚A, and (c) 20 ˚A oxide from low-pressure oxidation with native oxide desorbed in situ.
oxide thickness is generally explained by the over-estimation of inversion carrier concentrations in thin oxides [2], [11], other possibilities such as Coulomb scattering from remote charge at poly-gate or the poly-gate/oxide interface roughness may also be responsible to the mobility degradation. The remote charge scattering is due to poly-gate depletion [12] and is well known in III–V modulation-doped FET and was also predicted in [13] and [14]. The interface roughness of poly-gate and oxide, shown in Figs. 1 and 2, may also contribute local gate field variation [15], [16] and provide additional scattering mechanism to reduce the mobility at thin oxide.
IV. CONCLUSION
In conclusion, we have shown direct relationship of electron mobility to oxide/channel interface roughness. Significant mo-bility improvement is obtained from a smoother interface with
in situ removing native oxide prior to oxidation. Atomically
flat interface of oxide/channel can be obtained by this method for oxide thickness in the range of 11–38 ˚A. Mobility reduction with decreasing oxide thickness was observed in the 20- and 35- ˚A oxide, with the same atomically smooth oxide/channel interface. This may be due to the remote Coulomb scattering from gate electrode or the gate field variation from poly-gate/oxide interface roughness.
ACKNOWLEDGMENT
The authors would like to thank Prof. K. C. Hsieh, De-partment of Electrical Engineering, University of Illinois, for helpful discussion. They also thank Prof. T. F. Lei.
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