High Charge
Storage
Characteristics of
CeO2
Nanocrystals for Novolatile
Memory
Applications
Shao-Ming Yanga), Jiun-Jia Huanga), Chao-Hsin Chiena), Pei-JerTaeng b),Lurng-Shehng Leeb), Ming-Jinn Tsaib), andTan-FuLeia) a)Department of Electronics Engineering& Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
b)Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan. Tel: 886 3-5712121ext 54179 Fax: 886 3-5724369 E-mail:
ABSTRACT
This paper presents the formation of CeO2 nanocrystals on SiO2 tunneling layer and its annealing effect to the nonvolatile memory device. The characteristics including the program/erase behaviors, dataretention, and endurance of Silicon-Oxide-Nitride-Oxide-Silicon type memories embedded with cerium oxide (CeO2) nanocrystals were studieded to demonstrate its advantages as a nonvolatile memorydevice.
I
INTRODUCTION
Si and metalnanocrystals (NCs) arewidely studiedaspotential solutions to overcome the scaling limitations of the conventional flash memories for future nonvolatile, high density, and low power memory devices1. Cerium dioxide (CeO2) has been extensively studied as an electrolyte material of solid oxide fuel cells2. The properties of CeO2 such as lattice nearly matched to silicon (a=0.541 Inm) and sufficiently high dielectricconstant
(-26)3
leadto the high thermal stability on silicon and high scaling capacity. Recently, high-K dielectric NCs on the SiO2 tunnel layer for SONOS-typememories have beenproposed. Linetatt. reported amethod of co-sputtering Hf and Si in oxygen followed with high-temperature annealingto form thehigh-K NCs for SONOS-type memory devices. However, theHfO2 nanocrystal memory exhibit saturation windows in channel-hot-electron (CHE) program mode. You et al5. have proposed the sol-gel spin-coating method to form the high-K NCs. This method may increase thickness of tunnel oxide and results in high operation voltage.Inthis work, the CeO2 NCswereformed by thermal annealing indifferent ambients. SONOS-type memories were fabricated, and the electrical properties, includingthe P/E speed and data retention characteristicswereinvestigated.
II.
EXPERIMENT
AnnMOSFETwithCeO2nanocrystal flash memorystructureis schematicallyshown inFig. 1.Athin CeO2layerwasthendeposited onSiO2tunneling layer byanelectron-beam evaporatorat10-6Torr. The samples subsequently underwent RTA at 900 °C for 1 min in either02orN2ambienttoform CeO2NCs(RTOandRTNsamples), respectively. Finally, the CeO2 NC memory deviceswere completed after the substratecontactpatterning and metallization. The electrical properties of such devices were measured using HP 4156B semiconductor parameteranalyzer andHP 41501Apulse generator. The charge pumping measurement was performed with Keithley 4200 semiconductor parameteranalyzer andHP81 10pulse generator.
Imf.
RESULTS
ANDDISCUSSION
The cross-sectional transmission electron microscopy (TEM) images of the CeO2 NCs embedded in the SiO2 matrix for RTO and RTN samples are shown in Fig. 2. No obvious different in microstructure in terms of NC size and disturbution are formed between annealedsamples. TheyshowedaNCdensity of
3-7x1011
/cm2.
The average NC size was 8-10 nm. Crystallized NCs with obviouslyvisible latticefringeswereevident in the insets.Figure 3 shows the Ids-Vgscurves ofCeO2 nanocrystal memory cell with differentprogramminganderasingconditions. The device is programmed byCHEinjection and erasedbyband-to-band hot-hole
(BBHH) injection. The programming speed of the CeO2 NCs memory devices with RTN and RTO annealing is shown in Fig. 4. When the programvoltage increasesto 10 V, the Vth shift increases rapidly and a memory window greater than 5 V is achieved within 1 ms. This large memory window make the multilevel operation possible. The fact the programming speed is indepentent of annealing condition of the charge trapping centers, indicating that the programming speed is primarily dependent on the tnunneling oxide. Figure 5 shows the erasing speeds characteristics at different voltages withafixed Vd of 10V.Asobserved,anincrease in thenegative gate bias resulted inahigh erasing speed duetothehigher electrical field forBBHHinjection. Afully erasedstate was fulfilled within 1ms at Vg=-7Vand Vd= 10V.
Figure 6 shows the data retention characteristics of the CeO2 NC memory devices at two programming states. The RTN sample showed a smaller amount of charge loss than the RTO at room temperaturefor retention time upto
104
S. Itisconjectured that the bulk traps ofRTN sample is deeper than RTO sample sothat the charge loss ofRTN sample is less than RTO sample. The electrons canbe eithertrapped in these bulk defectsorstayinthe conduction band of the CeO2 NCs and/or in the interfacestatesbetween the CeO2 NCs and SiO26. Figure 7 shows the endurance characteristics of the CeO2 NC memory devices after104
P/Ecycles. Itis found that the memorywindow of the NC devices is notnarrowing even after104
P/Ecycles. The narrowing mainly comes from charge gain when the electron distribution does not completely match that for the hole. Each P/Ecycle will leave a few electrons in the trappinglayer5.
The charge-pumping7 mesurementby change base voltage atfixedpulse amplitude
wasconductedtodetermine the defectdensity
andstates shown inFig. 8. The RTNsample haslarger
charge-pumping
currentthan theRTOsample,whichcanbe attributedto themoretrappingdefectstatesintheRTNsample.This is consistent with the better data retention of theRTNsampleobserved inFig.6.IV. CONCLUSION
We have demonstrated P/E window (5V within Ims atVg 1OV) of CeO2 NCs memory devices. The RTNCeO2 NCstrapping layers have a larger charge storage capacity and a longer retention time than the RTO sampleduetodeepertrap center.Itis concluded that CeO2 NCs canbe usedas discretecharge trapping sites for the SONOS-type memories.
REFERENCES
[1]K.I.Han etal.,IEEETrans.ElectronDevices, 2007, vol. 54, pp. 359 -362.
[2]M.Mogensenetal.,Solid StateIonics. 2000, vol. 129, pp. 63-94. [3]N. V. Skorodumovaetal.,inPhysicalReview B, 2001,vol.64,pp. 115108-9.
[4]Y. H.Linetal.,IEEETrans.ElectronDevices, 2006, vol.53 , pp. 782 -789.
[5] H. C. You et al., IEEE Electron Device Lett.,2006, vol. 27. pp.653-656.
[6]Y. H.Shihetal.,IEDMTech.Dig.,2004, pp. 881-884.
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Fig. 1. Schematicstructureof CeO2 nanocrystal Fig.2.Cross-sectionalTEMimage of the CeO2 nanocrystals embedded
memorycell. in SiO2 dielectric matrix: (a) withN2annealing
900°C
for1min
and(b)with 02annealing 900°C for 1min.
1 2 3 4 6 7
Gatevoftage (V)
Fig. 3. Ids-Vgscurvesof thememorycell with
differentprogramming conditions. Vth is definedastheapplied voltageatwhich the draincurrentis 0.1pIA.
'10 lo! l10
Retention timeIs)
Fig. 6. Data retention of CeO2 nanocrystal
memory devices with different RTA
treatments.
l0o 10o
-lo" lo" 10Pg ra to l
Progranmmingtilme(s)
Fig. 4. Programming speed characteristics of
CeO2 nanocrystal memory devices with
differentprogramming conditions.
1o0 10
NumberofPIEcycles
RO RTN VI=vVIMov Asq ' Vs9VAVOAV Al O'.. , l;;li A3 ."A InV - -6 -10 10a4 1a 104 10 i0i Erasing tim {ss
Fig. 5. The erasingspeed characteristics of theCeO2nanocrystalmemorycellat differenterasing voltages.
4AxI0"
4xl
3EOx10
XlO-Fig. 7. The endurancecharacteristics of CeO2nanocrystalmemorydeviceswith
two differenttreatmentdevices.
-1 1
Basevoltage(V) 2
Fig. 8. Chargepumpcurrent
(Icp)
of CeO2 NC deviceas afunction of basevoltageat fixedpulse amplitude.i10
I10-j
10-4 10.1 10.1 104 10-0 0 C3 0 RTO RTN B V 10VV 910V 4_
I
A9v3!
2,
F h P V VG6 01Al P VmVz7V.t1, m pPV* V 8Vj-01lma P VNV 9VtQIO! 4 E V 4-v"v 1ovltmlm iSli~~~~~~~~~~~~~"o fji~~~~~~~~~~~~~~~EHighV., V U U ms 1 . 5 RTN aRTO4 LowV~(po~V=,= =Olr RTN ...FM0 2r 4 RTO £ P VV
