超大型積體電路連線的解析模型與最佳化設計

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(1)國立交通大學電子工程學系電子研究所. 博士論文. 超大型積體電路連線的解析模型與最佳化設計 The Analytical Models and Optimization Designs for VLSI Interconnection. 研究生: 李國暥指導教授: 曾俊元鄭晃忠中華民國 96 年 7 月. 教授教授.

(2) 超大型積體電路連線的解析模型與最佳化設計. The Analytical Models and Optimization Designs for VLSI Interconnection 研究生 : 李國暥. Student : Gwo-Yann Lee. 指導教授 : 曾俊元博士. Advisor : Dr. Tseung-Yuen Tseng. 鄭晃忠博士. Advisor : Dr. Huang-Chung Cheng 國立交通大學. 電子工程學系電子研究所博士論文. A Dissertation Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical Engineering and Computer Science National Chiao-Tung University In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering 2007 Hsinchu, Taiwan, Republic of China 中華民國九十六年七月.

(3) 超大型積體電路連線的解析模型與最佳化設計研究生: 李國暥. 指導教授: 曾俊元博士鄭晃忠博士. 國立交通大學電子工程學系. 電子研究所博士班. 摘要隨著的積體電路複雜程度不斷增加，其金屬連線對電路特性的影響越來越重要. 在本論文中，我們發展了一系列完整的超大型積體電路金屬連線電容模型。這些電容模型包含三種結構 1) 平行的金屬線在一平板之上，2) 平行的金屬線在上下兩平板之間， 3) 不同金屬層之間的連線交錯所組成的三維電容結構。利用這些電容模型計算所得到的解和 Poisson 方程式的數值解及量測資料一致。有了這些電容模型，我們接著推導一系列的延遲及串音雜訊模型。其包含了 1) 單一金屬連線，2) 雙線交聯的金屬連線，以及 3)多線交聯的金屬連線系統。我們也提出了考慮電感效應的延遲模型。我們發現在較慢的操作頻率及長度較長的金屬線其電感效應並不明顯。本論文提出一種新的準則可以判別電感的重要與否。這個準則可以讓晶片設計工程師減少需要考慮模擬電感的時機進而減少晶片設計的時間。這裡所提出的模型皆用 SPICE 模擬驗證並得到良好的準確性。根據以上的模型，這裡提出針對延遲及串音雜訊的表現進行金屬連線最佳化設計的方法。我們發現 1) 對於沒有上層金屬板的連線而言，最佳化的製程結構為薄的介電質層厚度，2) 對於上層有金屬板的連線，較厚的介電質層及較厚的 i.

(4) 金屬線可以提供比較好的設計容許範圍，以及 3)在較小的線寬及線距之下將，設計容許範圍會大幅度縮小。在進入奈米級的製程時，不管是元件 (前段製程) 或金屬連線 (後段製程)，製程變動對其特性以及產品良率的影響將是關鍵性因素。因製程變動越來越明顯，設計的不確定因素越來越大，如動態/靜態功率消耗、延遲及串音雜訊的不確定。本文採取機率統計的方式來計算金屬連線寄生參數(如電容及電阻)，延遲及串音雜訊來取代傳統的 corner-based 的方法。使用這種方法可以幫助設計工程師及製程工程師找到高良率的晶片設計及製造方法。使用機率統計的分析，我們發現 1) 較厚的介電質層厚度(H)及較厚的金屬線厚度(T)可以提供對製程變異比較好的抵抗力。2) 對於信號延遲分析，水平間距 (pitch) (P) 和介電質層厚度有一最佳的關係(P/H=2.5)，此一最佳結構讓延遲對製程變異不敏感。 3) 對於串音雜訊而言，P/(T+H)=0.77 的結構對製程變異敏感度最大。設計或製程工程師應該避免此一結構。所以針對串音雜訊，我們建議佈局的範圍為 P < 0.77*(T+H) 或 P > 0.77*(T+H)。本文的內容相信對超大型積體電路的設計以及最佳化有很大的助益。. ii.

(5) The Analytical Models and Optimization Designs for VLSI Interconnection Student: Gwo-Yann Lee. Advisors: Dr. Tseung-Yuen Tseng Dr. Huang-Chung Cheng. Department of Electronics Engineering & Institute of Electronics National Chiao Tung University. Abstract Increasing complexity in very large scale integration (VLSI) circuits makes metal interconnection a significant factor affecting circuit performance. The dramatically increased amount of interconnection line in chip makes the interconnect delay and crosstalk noise more dominant factors in the overall circuit speed. In this thesis, we first develop new closed-form capacitance formulas for three major structures commonly happened in VLSI, namely, 1) parallel lines in a plane, 2) parallel lines between two planes and 3) inter-layer wire crossings which are three-dimensional (3-D) nature. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson`s equation as well as measurement data. We then further derive closed-form solutions for the delay and crosstalk noise for several interconnect structures. The structures include, 1) interconnect system which iii.

(6) has only one line, 2) interconnect system which has two parallel coupled wires and 3) interconnect system which has multiple wires coupled with each other. We also propose analytical models considering the effects of interconnect inductance. We found the effect of inductance is not significant for lower frequency operation conditions and longer line. Hence, another contribution of this thesis is that we propose criteria to help the designer to answer the question, “when does the interconnect inductance become important?”. It is helpful to reduce the efforts of performing full chip simulation with inductance. The delay and crosstalk models proposed in this thesis all agree well with SPICE simulations. Based on the models, interconnect delay and crosstalk performance is optimized over the range of process and design dimension of interest. In specified, we find 1) for wire without top wiring, the optimal dielectric thickness is relatively small, this agree with process concept nowadays 2) for lines with top wiring, larger dielectric thickness and wire thickness give better performance, and 3) the range of allowable wire thickness and dielectric thickness reduces seriously as the design pitch reduces. The variations in the process, whether device (front-end) or interconnect variations (backend), is becoming critical issue for nano-era chip designs. Along with increased process variations, the design uncertainty is increasing such as dynamic power consumption, delay and crosstalk noise. Traditional corner-based analysis provides pessimism or optimism design; hence, we propose the statistical parasitic (ex. capacitance and resistance), delay and crosstalk analysis methodology which help design or process engineer to deliver the robust chip design and enhance the product yield. In this study, we find 1) the thicker dielectric thickness (H) and metal thickness (T) provide better process variation immunity. 2) For delay analysis, horizontal pitch (P) and dielectric thickness has one optimum relationship (P/H=2.5) to achieve designs that could reduce performance impact due to variability. 3) For crosstalk analysis, P/(T+H)=0.77 is iv.

(7) the structure most sensitive to process variation and both process and design engineer should prevent to use the structure. Hence, we recommend to use small horizontal pitch (P) so that P < 0.77*(T+H) or large pitch so that P > 0.77*(T+H) to minimize the impact due to process variation. These results are believed to be helpful in VLSI design and optimization.. v.

(8) 誌. 謝. 僅以此論文獻給我敬愛的父母-李興男先生與朱秀琴女士，感謝你們多年來辛苦的培育我，教育我，有了你們持續的支持與付出，才能讓我得以全心投入學業，完成博士學位。感謝我的論文指導教授鄭晃忠博士及曾俊元博士，老師在研究上的熱心指導以及謙恭溫和的待人處事，都讓我獲益良多，也使我能順利完成博士學位。感謝實驗室的學長、同學及學弟們，謝謝你們在學術研究或是生活上都能夠給予我支持與關心，使得我的研究能夠順利完成，其中包含了黃全洲學長、史德智同學、王志良學弟。有了你們在我的研究生生涯一路不斷的相互扶持，才能順利完成論文。感謝宋美雅女士在我研究生生涯中默默的在背後支持我，在我低落的時候，可以陪伴著我，使我能再次打起精神面對下一個挑戰，由衷的感謝妳。最後感謝所有曾經幫助過我的朋友們，謝謝你們一路上給我的支持與關心，我今天才可以完成博士學位。. vi.

(9) Contents. Abstract (in Chinese)………………………………………………………………………...i Abstract (in English)……………………………………………………………………….iii Acknowledgments……………………………………………………………………….vi Contents……………………………………………………………………………………vii Table Lists…………………………………………………………………………………..x Figure Captions……………………...……………………………………………………xi. Chapter 1. Introduction and Motivation for This Research. 1. 1-1. Overview of VLSI Interconnects…………………………………………………...1. 1-2. Interconnect Integration and Process Variation Issues………………………………2. 1-3. Theory Background and Motivation of This Thesis…………………………………4. 1-4. Thesis Organization…………………………………………………………………. 5. Chapter 2. Methodologies and Modeling Developments. 13. 2-1. Methodologies and Modeling Developments………………………………… 13. 2-2. Summary……………………………………………………………………………... 15. Chapter 3. Interconnect Parasitic Component Modeling. 20. 3-1. Two-Dimensional Interconnect Capacitance Model and Extraction………………20. 3-2. Three-Dimensional Interconnect Capacitance Models and Extraction………………25. 3-3. Interconnect Resistance Model………………………………………………………37. 3-4. Interconnect Inductance Model………………………………………………………37 vii.

(10) 3-5. Summary…………………………………………………………………………….. 40. Chapter 4. Interconnect Delay and Crosstalk Modeling. 52. 4-1. One-Line Interconnect System Delay Modeling…………………………….. 55. 4-2. Dual Parallel Coupled Interconnect Delay and Crosstalk Modeling……………… 57. 4-3. Multiple Parallel Coupled Interconnect Delay and Crosstalk Modeling…………... 65. 4-4. Crosstalk-Induced Delay Time Model…………………………………………... 67. 4-5. Worst Crosstalk Modelings…………………………………………………………76. 4-6. Interconnect Models Considering Inductance Effects………………………………... 79. 4-7. Summary...…………………………………………………………………………... 96. Chapter 5. Interconnect Optimization Design. 127. 5-1. Interconnect Optimization Design Method…………………………………………..127. 5-2. Process Optimization………………………………………………………………128. 5-3. Design Optimization……………………………………………………………….. 132. 5-4. Summary……………………………………………………………………………. 135. Chapter 6. Statistical Analysis and Optimization for VLSI Interconnection. 148. 6-1. Variation Source and Impact on Performance……………………………………... 150. 6-2. Modeling of Variation Source………………………………………………………153. 6-3. Model Approximation Method and Characterization………………………………153. 6-4. Statistical Capacitance, Delay and Crosstalk Model…………………………………158. 6-5. Optimization Design of Interconnect Considering Process Variations……………..165. viii.

(11) 6-6. Summary…………………………………………………………………………….169. Chapter 7. Summary and Conclusions……………………………………...190. Chapter 8. Future Prospects………………………………………………... 192. References…………………………………………………………........………………….193 Vita Publication List. ix.

(12) Table Lists Chapter 1 Table 1.1. MPU interconnect technology requirements of SIA roadmap—near-term years.. Chapter 3 Table 3.1 Comparison of capacitance model with measurement data. Table 3.2 Error table of the capacitance model of parallel lines on one plane compared with numerical solutions Table 3.3 Error table of the capacitance model of parallel lines between two planes compared with numerical solutions Table 3.4 Error table of the capacitance model for crossover structure compared with numerical solutions. Table 3.5 Comparison between measurement data and the model.. Chapter 6 Table 6.1 Comparison between measurement data and the model for crossover structure.. x.

(13) Figure Captions Chapter 1 Figure 1.1. Copper metallization characteristic of a six-level structure. Figure 1.2. Circuit delay as a function of the feature size (low K=2). Figure 1.3. CMP tool.. Figure 1.4. Copper CMP pattern dependencies. Figure 1.5. Mechanisms of electropolishing and ECMP.. Chapter 2 Figure 2. 1. General interconnect structure plot with driver and receiver.. Figure 2. 2. Interconnect could be categorized into three structures (Region A, B and C). Region A represents interconnect surrounded by metal line at the same layers (intra-layer) and with many dense coupled wire of different layer (inter-layer) inter-wires run across it. Region B represents interconnect surrounded by intra-layer wires and without inter-layer wire run over it. Region C represents interconnect surrounded by intra-layer metal line and with single wire (or a set of loosely coupled wires) run across it. The dash wire represents the wire need to calculate the capacitance. Decomposition of interconnect structure into a series of 3-D and 2-D segments. The total capacitance (Ctotal) of dash line Ctotal=CRegion_B+CRegion_C+CRegion_B+CRegion_A.. Figure 2. 3. Methodology for interconnect capacitance model development. Figure 2. 4. Methodology for interconnect statistical analysis. xi.

(14) Chapter 3 Figure 3. 1 (a) Cross-section diagram of parallel lines on one plane. (b) Cross-section diagram of parallel lines between two planes Figure 3. 2. (a) Verification of model accuracy of various capacitance components [(1)-(2)]; symbols: Raphael, solid line: our model, dashed line: model in [2]. W=0.2μm and T=0.64μm, H=0.89μm. (b) Verification of model accuracy of various capacitance components [(3)-(4)]; symbols: Raphael, solid line: our model, dashed line: calculated by adding up the one-plane model based on formula in [2]. W=0.5μm and T=0.64μm, H1=H2=0.89μm.. Figure 3. 3. Metal wiring crossover structure and cross sections along cut lines A, B, and C. H1, H2, and H3are dielectric thickness, T1, T2, and T3are metal wire thicknes, W1, W2 , and W3are wire width, and S1, S2, and S3are interwire spacing.. Figure 3. 4. Crossover capacitance variation versus dielectric thickness. Symbols denote Raphael simulation, and dashed and solid lines denote our model calculation.. Figure 3. 5. Crossover capacitance and total capacitance variation versus intralayer wire spacing. Symbols denote Raphael simulation, and lines denote our model calculation. The left graph and right graph are correlated to each other by sharing the common axis of C cr for comparing the different C cr variation versus S1 and. S 2 .. Figure 3. 6. Crossover capacitance variation versus top-level wire dielectric thickness and intralayer wire spacing. Symbols are Raphael simulation, and lines denote model calculation. xii.

(15) Chapter 4 Figure 4. 1. (a) Schematic diagram of isolated one-line system. (b) Schematic diagram of two coupled lines. (c) Schematic diagram of three coupled lines. (d) The symmetry of the interconnection structure in (c) can be represented by the asymmetric interconnection.. Figure 4. 2. Comparison of SPICE simulation, new ramp model and Sakurai’s model for an isolated one-line system of various driver resistances and loading capacitances. Input ramping rate independent delay time is observed in Sakurai’s model.. Figure 4. 3. (a) Model accuracy of RC line delay model. (b) model accuracy of RC line crosstalk model.. Figure 4. 4. Delay times in SPICE simulation (symbols) and the new ramp model (lines) for the two-line system [Fig. 4.1(b)] are compared.. Figure 4. 5.. Normalized crosstalk noises in SPICE simulation (symbols) and the new ramp model (lines) for the two-line system [Fig. 4.1(b)] are compared. The crosstalk noise shows input rise time dependence.. Figure 4. 6. Delay times in SPICE simulation (symbols) and new ramp model (lines) for the multiple coupled line system [Fig. 4.1(c)] are compared.. Figure 4. 7.. Normalized crosstalk noises in SPICE simulation (point) and the new ramp model (line) in the multiple coupled line system [Fig. 4.1(c)] are compared. The crosstalk noise shows input rise time dependence.. Figure 4. 8. (a) Schematic diagram of crosstalk-enhanced delay time case and (b) worst crosstalk case for coupled interconnect.. Figure 4. 9. Comparison of the output waveforms calculated from SPICE. xiii.

(16) simulation and new models. (a) a1 ＞ a2. (b) a1 ＜ a2. Figure 4. 10. Comparison of SPICE simulation (symbols) and new model (lines) for crosstalk-induced delay times in the system of Fig. 1(a), where RT= Rs/R and CT= CL/(Caf+3Cll).. Figure 4. 11. Comparison. of. SPICE. simulation. and. new. model. for. crosstalk-enhanced delay time case in the system of Fig. 1(a). The rise time in the simultaneously switching case is 1ps, where RT= Rs/R and CT= CL/(Caf+3Cll). Figure 4. 12. Comparison of SPICE simulation (symbols) and new model (lines) for worst crosstalk noise in the system of Fig. 1(b), where RT= Rs/R and CT= CL/(Caf+3Cll).. Figure 4. 13. Maximum routing length is limited by the crosstalk for small driver resistance and by the delay time for large driver resistance.. Figure 4. 14. Interconnect modeled as distributed r-l-c.. Figure 4. 15. Waveform, at the end-terminal of the wire in Fig. 4.14, calculated from SPICE simulation and herein analytical model.. Figure 4. 16. RLC models and RC and RLC SPICE simulation and corresponding percentage error for 50% delay time at RT=CT=1, z=1000um.. Figure 4. 17. RLC models and RC and RLC SPICE simulation and corresponding percentage error for 90% delay time at RT=CT=1, z=1000um.. Figure 4. 18. SPICE simulation data (point) versus new model (line) and percentage error plot. The plot gives 50% delay time vs. input rising time for various combinations of driving and loading conditions. Wire length is 1000um.. Figure 4. 19. SPICE simulation data (point) versus new model (line) and percentage error plot. The plot gives 90% delay time vs. various input rising time xiv.

(17) for various combination of driving and loading conditions. Wire length is 1000um. Figure 4.20. 50% Delay time vs. wire length for various driving and loading conditions. The input rising time in this plot is 50pS. The legend of this plot is the same as Figure 4.19.. Figure 4. 21. (a) 50% Delay time (point: RC, solid line: RLC and data are from SPICE simulation) vs. wire length for various driving and loading conditions for a=50pS. (b) Percentage error plot for RC model with respect to RLC SPICE simulation. (c) calculated inductance critical length (zc) vs wire length for various driving/loading conditions. The dash line (. ) represents the condition that wire length is equal to. the critical length (z=zc). The dot line (. ) represents the critical. length calculated from the two criterions in [4.24] and [4.25]. The legend of point symbols for this figure is the same as Figure 4.19. Figure 4. 22. Overshoot voltage vs. wire length for various driving and loading conditions. The legend of point symbols for this figure is the same as Figure 4.19.. Figure 4. 23. Critical length (zc) and inductance effect window changing with loading conditions.. Chapter 5 Figure 5. 1. Interconnect schematic for optimization design.. Figure 5. 2. Design contour analysis of delay and crosstalk.. Figure 5. 3. Design contour analysis of delay and crosstalk for structure T=H=0.7 μm.. xv.

(18) Figure 5. 4. Design target and Ad analysis for lines on one plane, td=30ps. circle:T=0.7, triangle: T=0.6, square: T=0.5, diamond: T=0.4, cross: T=0.3, plus: T=0.2, star: T=0.16.. Figure 5. 5. Design target and Ad analysis for lines on one plane, td=70ps. circle: T=0.7, triangle: T=0.6, square: T=0.5, diamond: T=0.4, cross: T=0.3, plus: T=0.2, star: T=0.16.. Figure 5. 6. Design target and Ad analysis for lines between two planes, td=70ps. circle: T=0.7, triangle: T=0.6, square: T=0.5, diamond: T=0.4, cross: T=0.3, plus: T=0.2, star: T=0.16.. Figure 5. 7. Comparison of design target for lines on one plane and between two planes, td=30ps. circle:T=0.7, triangle: T=0.6, square: T=0.5, diamond: T=0.4, cross: T=0.3, plus: T=0.2, star: T=0.16.. Figure 5. 8. Process contour analysis of delay and crosstalk for structure W=0.4μ m and S=0.4μm.. Figure 5. 9. Process contour analysis of delay and crosstalk for structure W=0.4μm and S=0.6μm.. Figure 5. 10. Process target and Ap distribution for lines on one plane, td=30ps. circle: W=0.7, triangle: W=0.6, square: W=0.5, diamond: W=0.4, cross: W=0.3.. Figure 5. 11. Process target and Ap distribution for lines on one plane, td=70ps. triangle: W=0.6, square: W=0.5, diamond: W=0.4, plus: W=0.3, cross: W=0.16.. Figure 5. 12. Process target and Ap distribution for lines between two planes, td=70ps. circle: W=0.7, triangle: W=0.6, square: W=0.5, diamond: W=0.4, plus: W=0.3, cross: W=0.16.. xvi.

(19) Chapter 6 Figure 6.1. General design flow hierarchy from process to SOC.. Figure 6.2. Process variation plus model error caused variation.. Figure 6.3. The effect of X on Y. The variation of Y (σ1) depend on the nominal value (t1) of X. The relationship between standard deviation and X is derived by the variation transmission method.. Figure 6.4. (a) cross-section of interconnect over one plane and (b) cross-section of interconnect between two planes.. Figure 6.5. The capacitance distribution calculated from Monte Carlo simulations and statistical capacitance model.. Figure 6.6. Error in statistical model of total capacitance (Ctotal) as a function of interconnect process (T, H,ρand εeff ) and design parameters (W and S).. Figure 6.7. (a) Delay statistical distribution and (b) crosstalk statistical distribution calculated from Monte Carlo simulations and statistical capacitance model.. Figure 6.8. Error in statistical model of delay (td) as a function of interconnect process (T, H,ρand εeff ) and design parameters (W and S).. Figure 6.9. Error in statistical model of crosstalk voltage (Vp) as a function of interconnect process (T, H,ρandεeff ) and design parameters (W and S).. Figure 6.10. Capacitance values and corresponding standard deviation for line-to-line capacitance (Cll) and area-fringe capacitance (Caf) for one-plane (structure-A) in Fig.6.4.. Figure 6.11. Capacitance components breakdown comparison for two planes structure (structure-B) in Fig.6.4.. xvii.

(20) Figure 6.12. Capacitance variation breakdown plot.. Figure 6.13. RC components breakdown corresponding std. variation comparison.. Figure 6.14. Standard deviation of delay contour plot at T=1.2/H=1μm.. Figure 6.15. Interconnect crosstalk noise variation.. Figure 6.16. (a) delay for different technology node (b) the standard deviation of delay of 2-Planes structure for different technology node. The interconnect structure is calculated based on table 6.1. The symbol marked by dash-cycle is the minimum pitch dimension for different technology node mentioned in Table 6.1. IMD+ represents interconnect (n-th layer) has no metal plates at (n+1 & n-1-th layer) interlayer. IMD++ represents interconnect (n-th layer) has no metal plates at (n+1, n+2 & n-1 and n-2-th layer) interlayer.. Figure 6.17. Percentage variation for the delay of 2-Planes structure for different technology node. The symbol marked by dash-cycle is the minimum pitch dimension for different technology node mentioned in Table 6.1. IMD+ represents interconnect (n-th layer) has no metal plates at (n+1 & n-1-th layer) interlayer. IMD++ represents interconnect (n-th layer) has no metal plates at (n+1, n+2 & n-1 and n-2-th layer) interlayer.. Figure 6.18. (a) crosstalk for different technology node (b) the standard deviation of crosstalk of 2-Planes structure for different technology node. The interconnect structure is calculated based on table 6.1. IMD+ represents interconnect (n-th layer) has no metal plates at (n+1 & n-1-th layer) interlayer. IMD++ represents interconnect (n-th layer) has no metal plates at (n+1, n+2 & n-1 and n-2-th layer) interlayer.. Figure 6.19. Percentage variation for the crosstalk of 2-Planes structure for different technology node. IMD+ represents interconnect (n-th layer) has no metal plates at (n+1 & n-1-th layer) interlayer. IMD++ represents interconnect (n-th xviii.

(21) layer) has no metal plates at (n+1, n+2 & n-1 and n-2-th layer) interlayer.. xix.

(22) Chapter 1. Introduction and Motivation for Research. This chapter presents the introduction and motivation for the modeling of Very-Large-Scale-Integrated circuit (VLSI) interconnection. It is well known that the interconnect is becoming an important bottleneck in Ultra-Large-Scale-Integrated circuit (ULSI) performance. Accurate interconnect modeling methods are required to evaluate interconnect parasitic and it’s impact on the interconnect performance and the optimization interconnect design. In Section 1.1, we first present an overview and background for multilevel copper metallization. Section 1.2 reviews the basic interconnect process for CMP, and Section 1.3 reviews the basic interconnect design method. In Section 1.4, we discuss the motivation for this thesis, including previous related work and a brief summary of the contributions of this thesis. Finally, Section 1.5 presents the organization of the rest of the thesis.. 1.1 Overview Of VLSI Interconnects. The standard aluminum-copper alloy has been the choice for interconnects in integrated circuits for over three decades. However, with severe dimension shrinkage and transistor performance improvements in integrated circuits, the interconnect delay, crosstalk and the geometry variation during fabrication are becoming an important bottleneck in Ultra-Large-Scale-Integrated circuit (ULSI) performance and fabrication, especially at the gate lengths of 0.25 μm and below as shown in Fig. 1.2 [1.1]. The substitution of copper for the standard aluminum-copper alloy for interconnects is an big step in this transition. IBM and Motorola each announced their revolutionary. 1.

(23) transition to copper interconnect technology at the 1997 IEEE International Electron Devices Meeting Fig. 1.1 [1.2, 1.3]. The migration to new alternatives material for metal and dielectric, interconnects design has bring-up many process integration issues as well as design challenge. The new technology gave more promising on smaller wire spacing and thinner wire thickness; hence, the signal integrity issue now draws more and more attention due to advanced wire technology.. 1.2 Interconnect Integration and Processes Variation Issues It is well known that multilevel topography, or surface height variation, resulting from pattern dependencies in various processes, especially Chemical-Mechanical Planarization (CMP) in Fig.1.3, is a major problem in interconnects. CMP induced copper dishing and erosion that would cause the deviations of interconnect resistance and capacitance as shown in Fig. 1.4. With scaling of the trench thickness, erosion and dishing have to be minimized correspondingly to meet performance requirements. It is a major challenge to reach the requirements set by the International Technology Roadmap for Semiconductors (ITRS), 2005 edition, which is increasingly stringent at 65 nm and below, Table 1.1.. Process approach to improve the CMP erosion and dishing. In order to improve polishing performance and compatibility with low-κ dielectrics, cost-efficient low down force CMP polishing techniques have to be further developed. Several potential technologies, such as ACM’s electropolishing technology and Applied Materials’ electrochemical-mechanical polishing (ECMP). ACM Research proposes that electropolishing can be the solution for the next generation copper planarization [1.4]. Electropolishing can be looked at as the reverse 2.

(24) process of electroplating. The surface copper on the wafer, acting as an anode under external applied voltage, is converted to copper ions by losing electrons, which then dissolve into the electrolyte. The voltage will determine the current density, and the copper removal rate is proportional to the current density. This stress-free, non-contact process is friendly to low-K dielectrics. However, the price is low planarization capability due to nearly equal removal rates at field, protruding, and recessed locations [1.5]. There is no dielectric loss or erosion problem, however, since electropolishing is inert to nonconductive materials. Thus an initially flat topography is necessary to limit dishing due to low planarization ability. The use of conventional CMP to remove steps in the bulk copper prior to electropolishing is a potential solution, although this appears to require two equipment sets and steps. Another approach is to place dummy fill in wide structuresto flatten the post-plating topography [1.4]. However, the problem of low planarization ability still limits the application of electropolishing in manufacturing. Applied Materials’ electrochemical-mechanical planarization, or ECMP, is seeking to solve the problems of CMP and electropolishing, while keeping the advantages of these two processes by combining electrochemical copper removal with conventional CMP [1.6]. The wafer with an applied voltage is submerged in an electrolyte, as in electropolishing. A specially designed chemical is added into the electrolyte that passivates the surface of copper to block copper dissolution. A rotating polishing pad then softly removes the contacted copper-complex passivation layer only on raised copper areas to open the path for copper dissolution under the applied voltage. The recessed areas are protected by the passivation layer and remain untouched. Figure 1.5 compares the differences in polishing mechanism between electropolishing and ECMP. However, ECMP still has some limitations in its application to current 3.

(25) semiconductor technology. Conventional CMP steps are stilled required, following the bulk copper removal by ECMP, in order to achieve copper clearance and then barrier removal. However, the over-polishing using conventional CMP required to clear the copper from field regions to account for both chip-scale topography and wafer-scale, nonuniformity can still introduce significant dishing and erosion.. Design approach to improve the CMP erosion and dishing. In order to further improve the polishing productivity and planarity to compete with ECMP, dummy filling, slotting will likely be required in conjunction with CMP process improvements. Design method to modeling these geometry variation and corresponding performance impact is also important to prevent under-design or over design which both cases will decrease the yield of the chip.. 1.3 Theory Background and Motivation Of This Thesis. Many works have been devoted to calculating line capacitance, e.g., [3.2]-[3.4]. Sakurai and Tamaru [3.2] derived formulas, both for parallel lines on a large plane. Choudhury et al. [3.3] gave models for several layout primitives but only for one set of technology parameters. Chern et al. [3.4] gave a general capacitance formula for three-dimensional crossing lines assuming the same dielectric and wire thickness for all layers. For delay and crosstalk modeling, Sakurai [4.15] derived a good simple solution of the partial differential equation of a single isolated line under the assumption of step input waveform. This model is good for its intended applications such as two coupled lines and high input impedance gates. However, it overestimates or underestimates the amount of crosstalk signal for more general structures. Moreover, no general closed-form solution of the delay time and crosstalk noise voltage was 4.

(26) shown in Sakurai’s paper in the case of two coupled lines. Cases and Quinn [4.16] discussed the transient response of single RLC transmission lines but the closed-form solution was omitted from their work. The coupled interconnect structure, which is very important in VLSI circuits, was not discussed. Davis and Meindl [4.17], [4.18] gave the closed-form solution for coupled RLC transmission lines but the step input, infinite length line and open load were assumed in their work. The yield loss will worsen in future technologies due to increasing process variations. This is because as the feature sizes decrease, the ability to control the manufacturing spread or accuracy of a given feature size or doping concentration is also decreasing. Along with increased process variations, the uncertainty caused by design is also increasing such as interconnect coupling noise and delay. The impact of these process variations on performance has been increasing with each process technology generation. These is no any method so far for the optimization design of interconnect by considering the process variation. Thus, the main goals and objectives of this thesis are as follows: 1. Develop comprehensive and accurate interconnect capacitance formulas for delay, crosstalk and optimization design 2. Develop an generalized accurate delay and crosstalk modeling for optimization design 3. Provide the interconnection optimization method considering both the delay and crosstalk noise; and 4. Provide the statistical modeling and interconnection optimization method considering the process variation 1.4 Thesis Organization. This thesis is organized into eight chapters. Chapter 2 gives a brief summary of the plan and procedure for this thesis. 5.

(27) In Chapter 3, the comprehensive capacitance, resistance and inductance modeling methods are discussed. Chapter 4 introduces the comprehensive interconnect delay and crosstalk analytical modeling for various interconnect structures. Chapter 5 presents the interconnect optimization method based on the analytical formulas derive from chapter 3 and chapter 4. Chapter 6 presents the statistic capacitance, delay and crosstalk models and optimization design based on the model is discussed. Chapter 7 summarizes the major results and contributions of this thesis. Finally, Chapter 8 discusses potential topics for future research in this area.. 6.

(28) Figure 1.1. Copper metallization morphology of a six-level structure.. 7.

(29) Figure 1.2 Circuit delay as a function of the feature size (low K=2).. 8.

(30) Figure 1.3 CMP tool.. 9.

(31) Cu. Dielectric Large Line Fine Space. Fine Line Large Space. Large Line Large Space. Fine Line Fine Space. After copper CMP process. Erosion. Field Oxide Loss. Dishing. Erosion. Cu Dielectric Large Line Fine Space. Fine Line Large Space. Figure 1.4 Copper CMP pattern dependencies.. 10. Large Line Large Space. Fine Line Fine Space.

(32) Table 1.1 MPU interconnect technology requirements of SIA roadmap—near-term years.. 11.

(33) Figure 1.5 Mechanisms of electropolishing and ECMP [1.6].. 12.

(34) Chapter 2. Methodologies and Modeling Developments. Before discussing the details of interconnect analytical models and optimization design, it is necessary to introduce the overall methodology and formulas development plan. Figure 2.1 is the general interconnect structure which is driven by the drivers and terminated with receiver. The parasitic R, L and C are distributed across the interconnect. Two important performance parameters for interconnect are the delay and crosstalk noise which are correlated to the value of R/L/C parasitics. First, an accurate interconnect parasitic models are must-have information to discuss the overall performance of interconnect. Based on the capacitance models, a set of new generalized delay and crosstalk model are derived and verified. And then, we have the required formulas on hand, the optimization design is then discussed. In the presence of process variation, the study of the statistic analysis on delay and crosstalk are introduced. 2-1. Methodologies and Modeling Developments. The general interconnect layout is shown in Fig. 2.2. Interconnect could be categorized into three structures (Region A, B and C) based on the correlation between wire under discussion and near by interconnect layout. Region A represents interconnect surrounded by metal line at the same layers (intra-layer) and with many dense coupled wires of different layer (inter-layer) run across it. Region B represents interconnect surrounded by intra-layer wires and without inter-layer wire run over it. Region C represents interconnect surrounded by intra-layer metal lines and with single inter-wire (or a set of loosely coupled wires) run across it. In Region A, we could emulate the structure as lines with top plate. For any metal density equal 33% or greater (metal_spacing < 2*metal_width) can be approximated as a plate with negligible loss of accuracy due to the electric field shielding effect. Hence, we could model the dense-coupled wire as big plate [2.1]. Otherwise, 3-Dimensional effects need to be considered like interconnect crossover area as Region C. In Region B, the structure emulates lines without top wiring.. In Region C, the capacitance is of a 3-D nature due to. 13.

(35) fringe field in crossover section. The total crossover-area capacitance (Region C) can then be easily obtained by combining the crossover capacitance with the 2-D intralayer coupling capacitance. Then, we provide a systematic approach to decompose any structure into a series of 3-D plus 2-D segments. Therefore, the total capacitance (Ctotal) of dash wire in figure is calculated as Ctotal=CRegion_B+CRegion_C+CRegionB+CRegionA. The dash wire represents the wire B. need to calculate the capacitance in Fig. 2.2. Our assumptions are that any interconnect structures are the combination of the three basic structures and any interconnect capacitance could be extracted by dividing interconnect into the three capacitance elements. Hence, one of our goals of this thesis is to develop the capacitance models for all the three structures. The methodology to develop the capacitance formula is highlighted in Fig. 2.3. A set of accurate empirical capacitances for the three structures mentioned above will be provided in Chapter 3 along with the methodology. With capacitance models derived in Chapter 3, we develop analytical formulas of interconnect delay and crosstalk noise in Chapter 4. From Fig. 2.2, we could see that interconnect could be layout as single isolated wire or dense coupled wire. Hence, different delay and crosstalk noise model are developed for various interconnect structures. To this point in the thesis, we have the detailed analysis techniques and formulas for interconnect parasitic, delay and crosstalk model. In Chapter 5, we will use the formulas derived from Chapter 3 and Chapter 4 to drive the optimization studies. Two optimization methodologies, process and design optimization, are proposed in Chapter 5. The goal of the optimization is to find the maximum design or process window that meet the delay and crosstalk noise criterion simultaneously. The statistical analysis techniques are discussed in Chapter 6. We will propose the method for statistical capacitance, delay, crosstalk analysis. The proposed methodology is shown in Fig.2.4. Our plans, based on the methodology, are to develop (A) layout design techniques that can deal with variability, and (B) process parameters that reduce the 14.

(36) performance due to variability.. 2-2 Summary This research adopts an empirical modeling methodology for interconnect capacitance. Delay and crosstalk noise analytical models are proposed, too. By incorporating the capacitance, delay and crosstalk models presented in this thesis, the optimization design is presented. Finally, the statistical analysis method is given to consider the issue of process variations.. 15.

(37) A. W3 T3. H3 S3 B. Cll. Ccr. W1 T1. C. S1. Caf H1 Ground-Plane. T2 H2. S2. W2. Driver Figure 2. 1. Receiver. General interconnect structure plot with driver and receiver.. 16.

(38) Figure 2. 2 Interconnect could be categorized into three structures (Region A, B and C). Region A represents interconnect surrounded by metal line at the same layers (intra-layer) and with many dense coupled wire of different layer (inter-layer) inter-wires run across it. Region B represents interconnect surrounded by intra-layer wires and without inter-layer wire run over it. Region C represents interconnect surrounded by intra-layer metal line and with single wire (or a set of loosely coupled wires) run across it. The dash wire represents the wire need to calculate the capacitance. Decomposition of interconnect structure into a series of 3-D and 2-D segments. The total capacitance (Ctotal) of dash line Ctotal=CRegion_B+CRegion_C+CRegion_B+CRegion_A.. 17.

(39) Caf ∈ox. Caf ∈ox. Figure 2. 3. =. W S ⎛ ⎞ + 2.217⎜ ⎟ H ⎝ S + 0.702H ⎠. 3.193. S ⎛ ⎞ + 1.171⎜ ⎟ ⎝ S + 1.51H ⎠. ?. =?. 0.7642. T ⎛ ⎞ ⎜ ⎟ ⎝ T + 4.532H ⎠. 0.1204. Methodology for interconnect capacitance model development. 18. ?. W ⎛ S ⎞⎛ T ⎞ ⎛ S ⎞ + ?⎜ ⎟ ⎟⎜ ⎟ + ?⎜ ? H S + H ⎝ S +?H ⎠ ⎝T +?H ⎠ ⎠ ⎝. ?.

(40) 0.08. Monte Carlo Statistical captitance model. 0.07 0.06. probability. 0.05 0.04 0.03 0.02 0.01 0.00 0.484. 0.486. 0.488. 0.490. 0.492. 0.494. 0.496. 0.498. Capacitance or td or vp (V). Figure 2. 4. Methodology for interconnect statistical analysis 19. 0.500.

(41) Chapter 3. Interconnect Parasitic Component Modeling. 3-1 Two-dimensional Interconnect Capacitance Model and Extraction With the increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this thesis, we first develop new closed-form capacitance formulas for two major structures in very large scale integration (VLSI), namely , 1) parallel lines in a plane and 2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately . We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson’s equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations. In modern very large scale integration (VLSI) technology, efforts have been devoted to reduce metal wiring pitch to increase chip density and to save silicon budget [3.3]-[3.5]. This makes metal wiring line resistance and line-to-line capacitance, thus the resistance-capacitance delay (RC delay) and interline crosstalk noise, increase. The huge amount of interconnection line in VLSI makes the interconnect delay and crosstalk noise more dominant factors in the overall circuit speed [3.6]-[3.8]. Many works have been devoted to calculating line capacitance, e.g., [3.2]-[3.4]. Sakurai and Tamaru [3.2] derived formulas, both for parallel lines on a large plane. Choudhury et al. [3.3] gave models for several layout primitives but only for one set of technology parameters. Chern et al. [3.4] gave a general capacitance formula for three-dimensional crossing lines assuming same dielectric and wire thickness for all layers. In delay and crosstalk modeling, Sakurai [3.5] gave equations of distributed RC line, but solutions were not obtained in closed-form. In this thesis, we give a new model of metal interconnection, where closed-form formulas are derived for the wiring capacitance, delay and crosstalk noise, all as explicit functions of the wire thickness, dielectric thickness, inter-wire spacing and wire width. New capacitance formulas are 20.

(42) first developed for two major structures in VLSI: 1) parallel lines on a plane and 2) wires between two planes; combinations of them can cover any given layout. The developed capacitance formulas then in turn lead to closed-form formulas for the delay, crosstalk noise, optimization design and statistic analysis: Chapter 3 derive the capacitance model, Chapter 4 gives the delay and crosstalk models, Chapter 5 gives the optimization of interconnect and Chapter 6 provide the statistic analysis of interconnect. We define two capacitance structures: 1) parallel lines on one plate as shown in Fig. 3.1(a), and 2) parallel lines between two plates as shown in Fig. 3.1(b). The first structure emulates lines without top wiring, and the second structure emulates lines with top wiring. In VLSI, that a line in a given layer is not (is) underneath a line can be covered by the first (second) structure. Developing formulas for the two fundamental structures is useful for simulating arbitrary integrated circuit layouts. The interconnect capacitance is decomposed into two capacitance components; 1). C ll is the flux to adjacent wire which affects both wiring. delay and crosstalk noise and 2) C af is the area and fringe flux to the underlying plane which determines wiring delay only. Physical approach requires analytical solution of Poission`s equation, which often results in lengthy and complicated equations, often nonsolvable. Thus, we adopt a semi-empirical approach here [3.2]-[3.5]. We use rations functions to give simple and explicit observations of field line variations with geometry parameters. The derived formulas model the field flux from different portions of an electrode separately, so that unique dimensional dependence of each electrical flux can be taken care of independently. A.. Parallel Line on a Ground Plane As shown in Fig. 3.1(a), wire thickness is denoted by T, dielectric. thickness by H, inter-wire spacing by S and wire width by W. The range of dimension is chosen as 0.15 < T <1.2, 0.16 < H < 2.71, 0.16 < S < 10, and 0.16 < W < 2, all in unit of micrometers. The ranges of these parameters are selected based in applications in deep submicron VLSI. Although our models [(1)-(4) below] are tested and verified only over these selected ranges, they should prove to hold for parameters outside the above ranges. It is simply because the 21.

(43) solutions to Poisson’s equation are majorly affected by the relative values of the dimensional parameters, not their individual ones. This is exactly the rationale behind the derivation of our models in what follows. First, C ll is modeled as the summation of three rational functions which simulate three flux components, and is obtained explicitly via the least-square fitting as. C ll T⎛ H ⎞ = 1.144 ⎜ ⎟ ∈ox S ⎝ H + 2.059 S ⎠. W ⎛ ⎞ + 1.158⎜ ⎟ ⎝ W + 1.874S ⎠. 0.0944. 0.1612. W ⎛ ⎞ + 0.7428⎜ ⎟ ⎝ W + 1.592 S ⎠. H ⎛ ⎞ ⎜ ⎟ ⎝ H + 0.9801S ⎠. 1.144. 1.179. , (3. 1). where ∈ox = 3.9 × 8.85 × 10−14 F/cm and it could change to ∈eff easily by considering multi-layer effective dielectric in modern VLSI technology. The first term on the right-hand side of (3.1) models side-wall flux, which linearly proportional to T and decrease as H/S decrease (i.e., as ground flux increases), because more flux originated form side wall now gets attracted to ground. The second term gives the upper-surface flux contribution, which increases as W increases or as S decrease, and which is independent of the ground flux. The third term models the lower surface flux, which is heavily inversely proportional to the ground flux. The power-law dependence in these functions has been a good approximation to the field strength between adjacent non-overlapping perpendicular surfaces [3.2] and [3.5].. C af is similarly modeled as the summation of three rational functions to simulate three flux components, and is obtained explicitly via the least-square fitting as. C af ∈ox. =. W S ⎞ ⎛ + 2.217⎜ ⎟ H ⎝ S + 0.702 H ⎠. 3.193. S ⎛ ⎞ + 1.171⎜ ⎟ ⎝ S + 1.51H ⎠. 0.7642. 0.1204. T ⎛ ⎞ ⎜ ⎟ ⎝ T + 4.532 H ⎠ .. (3. 2) The total capacitance of the wire M b is Ctotal = C af + 2C ll . The first term. 22.

(44) in the right-hand side of (3.2) models bottom plate-to-ground flux, which is simply the plate-to-plate capacitance. The second term and the third term model the upper surface and side-wall flux contributions, respectively; in the both terms, that the flux reduces with reduced S is because more coupling flux is attracted to the adjacent electrode M a and M b . B.. Parallel Lines Between Two Planes As shown in Fig. 3.1(b), the thickness of top dielectric layer and. bottom dielectric layer are denoted by H 1 and H 2 , respectively. The range of dimension is as in the previous case, expect that 0.16 < H1 < 2.71 and 0.16 < H 2 < 2.71 . By similar rational function approach and similar reasoning as. before, C ll is modeled to simulate the side-wall flux and upper lower planes flux. C af is modeled to simulate the upper and lower surface flux and the side-wall flux. Again, using least-square fitting, we have. ⎛ C ll T 2S 2S = 1.4116 exp⎜⎜ − − ∈os S ⎝ S + 8.014 H 1 S + 8.014 H 2. ⎞ W ⎛ ⎞ ⎟⎟ + 1.1852⎜ ⎟ ⎝ W + 0.3078S ⎠ ⎠. 0.7571 0.7571 ⎧⎪⎛ ⎫⎪ ⎞ ⎛ ⎞ ⎛ ⎞ H1 H2 2S ⎟⎟ ⎟⎟ ⎟⎟ × ⎨⎜⎜ + ⎜⎜ ⎬ exp⎜⎜ − ⎪⎩⎝ H 1 + 8.961S ⎠ ⎪⎭ ⎝ H 2 + 8.961S ⎠ ⎝ S + 3(H 1 + H 2 ) ⎠. (3. 3) and. ⎛W W ⎞ ⎛ ⎞ T ⎟⎟ + 2.04⎜⎜ ⎟⎟ = ⎜⎜ + ∈os ⎝ H 1 H 2 ⎠ ⎝ T + 4.5311H 1 ⎠. C af. ⎛ ⎞ T ⎟⎟ + 2.04⎜⎜ T + H 4 . 5311 2 ⎠ ⎝. 0.071. 0.071. 1.773. ⎛ ⎞ S ⎜⎜ ⎟⎟ ⎝ S + 0.5355 H 1 ⎠. 1.773. ⎛ ⎞ S ⎜⎜ ⎟⎟ S H + 0 . 5355 2 ⎠ . ⎝. (3. 4) Again, C total = C af + 2C ll .. C.. Model Validation The accuracy of our capacitance model is verified by numerical solutions. from Raphael [3.1] and measured data. We also include results from Sakurai`s 23. 0.25724.

(45) analytic model [3.2], [3.5] for comparison, Fig 3.2(a) gives the comparison results for wires on one plane. The accuracy of C ll , C af and the interaction between them are observed, and improvement of our model over Sakurai’s model [3.2], [3.5] is demonstrated. The comparison of our model for wires between two planes with Raphael is shown in Fig. 3.2(b). The detail error table for Fig, 3.2(a) and (b) are given as Table 3.2 and Table 3.3 respectively, which only displays a partial set of our data used for parameter fitting. Note that in Fig, 3.2(b). C ll1 p denotes the coupling capacitance obtained from Sakurai’s model 1p is the value by adding up the capacitances to top plate and to [3.2], and Ctotal. bottom-plate calculated using Sakurai’s model [3.2]. The root-mean-square error (rmse) for C af ( C ll ) is 3.68% (4.45%) and 1.05% (16.13%) for one- and two-plane cases, respectively. The number of data points used in calculating the root mean square error is 627. Our model is further compared with measured data, and the results are shown in Table 3.1. Five dies have been measured per wafer for six wafers, and the typical die around the distribution mean was used for comparison. Test structures were fabricated in two technologies: 1) a 0.5- μ m twin-well CMOS with SOG plannarized three-level metals and 2) a 0.35- μ m twin-well CMOS with chemical mechanical polished (CMP) three-level metals. All dielectric thicknesses used in model calculation are measured from large-plane capacitors on the same die as measured structures for accurate reflection of dielectric constant and dielectric thickness H. This thickness H is used for calculating all capacitance structures. The large-plane capacitors have been placed close to other capacitance structures in test key to eliminate intra-die dielectric thickness variations. Wire width W, inter-wire spacing S, and wire thickness T are determined from SEM bars of small inter-wire spacing on the same wager. The small spacing between SEM bars guarantees that horizontal dimension in dense array is adopted for capacitance calculation. All measurements are executed using a HP4284 impedance meter at 100 kHz, with all parasitic effects canceled using an open-pad calibration structure. Good agreement is observed, and this further demonstrates the accuracy of our capacitance model. Accurate closed-form models have been developed for wire capacitance. 24.

(46) The capacitance model gives line-to-line and line-to-ground capacitances separately, and lead to precise delay and crosstalk estimations provided in next chapter. These formulas allow for simple analytic prediction of capacitance for arbitrary interconnect dimensions. Our model is useful for VLSI design and process optimization. 3-2 Three-Dimensional Interconnect Capacitance Models and Extraction. We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance de-fined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16m and wire thickness down to 0.15m. The model is useful for VLSI design and process optimization. Deep submicrometer integrated circuit performance is influenced by interconnect RC delay [3.9]–[3.11]. Although the device delay decreases as the technology scales down, the inter-connect-induced delay, however, increases, because both line resistance and intralayer capacitance increase [3.9], [3.10], [3.12]. In VLSI circuits with multilevel interconnects, lines in adjacent metal layers are placed orthogonally to each other to minimize over-lapped capacitances and enhance routing flexibility. This procedure forms many wire crossings, inducing crossover capacitance, which becomes the major factor in affecting the circuit speed [3.10], [3.13]. An accurate model for the crossover capacitance is essential for estimating the interconnect circuit performance. Many previous works on interconnects exist in the literature. The works of [3.11], and [3.13]–[3.15] either considered two-dimensional (2-D) structures or approximated the three–dimensional (3-D) wirings by 2-D cross sections; both approaches cannot model 3-D fringe field. The models of [3.13]–[3.15] were based on numerical solutions, thus not allowing for closed-form estimation. The work of Chern [3.10] gave a crossover model for triple-level metal layers but with same thickness in all layers. The work of Pan et al. [3.16] derived an 25.

(47) analytical expression for crossover capacitance specifically for packaging geometries. The work of Kuhn et al. [3.17] gave an optimization study for delay time and power dissipation using combined device and interconnect capacitances; it, however, ignored both intralayer coupling and crossover capacitances that are important in deep submicron VLSI. The work of Vladimir and Mittra [3.18] gave improved boundary conditions for numerical solution of interconnect and packaging capacitances. Some other works focused on novel measurement methods for extracting interconnect capacitance on various layout structures. For instance, the work of Wee et al. [3.19] developed a complete set of structures for characterizing multilevel metal capacitances for both stack and crossing configurations; the impact of metal-edge slope and void was also extracted. The work of Nouet and Toulouse [3.20] characterized interlayer and intralayer capacitance novel test patterns, and compared on-chip and off-chip measurement. In [3.20], it was identified that the 3-D crossings (crossover) is a critical component in the total wiring capacitance, and a linear model with different components was then proposed with linear dependence on area, periphery length, and spacing. The work of Aoyama et al. [3.21] characterized coupling and ground capacitance using test patterns and numerical solutions, and it provided an optimization study by wire pitch to dielectric thickness ratio. The work of Chao et al. [3.22] presented a novel extraction method-ology and test pattern, with verifications on SOG and CMP processes. The work of Chen et al. [3.23] gave a novel on-chip measurement method for small wire capacitance. In [3.24], we developed models for 2-D wiring capacitance, wire delay, and inter-wire cross-talk noise. The capacitance model of in previous section gives accurate intralayer and line-to-ground capacitance estimation for both parallel lines on a plane and lines between two planes, with agreement with measurement data. In this thesis, we continue our work in previous section by focusing on the modeling of crossover capacitance for VLSI’s with multilevel metal interconnect of arbitrary dielectric and wire thickness, width, and spacing in all layers. The crossover capacitance is formed in any three adjacent layers of the multilevel metal interconnects and is of a 3-D nature. We derive closed-form formula for the crossover capacitance as a function of the wire geometry parameters of three adjacent layers, including the wire width, spacing, thickness, 26.

(48) and dielectric thickness of a line and of lines in the upper and lower layers. The total net capacitance on a wire passing many crossings can then be easily obtained by combining the crossover capacitance with the 2-D intralayer coupling capacitance defined on a same layer obtained in previous section. The result of our model shows agreement with the numerical field solver [3.25] and measurement data. This work extends the work of 2-D modeling provide in previous section to provide a complete solution for the modeling of interconnect capacitance for arbitrary multilevel interconnects. The complete model can be used in the delay and capacitance estimation in circuit design and process optimization. The crossover capacitance is formed in any three adjacent layers of the multilevel metal interconnect. Consider any triple-level wire crossings, as shown in Fig. 1, where the second-level metal lines ( M 2 ) cross the first-level ( M 1 , the lower level) and third-level ( M 3 , the upper level) metal lines. The line width, pacing, and thickness are denoted by, Wi , S i and Ti for the ith-level metal layer, i = 1,2,3 . The dielectric layer thickness is denoted by H 1 , H 2 , and H 3 for the dielectric between M 1 and the substrate (or the next lower layer, say, M 0 ), and M 2 , M 1 and M 3 and M 2 , respectively. For each M 2 line crossing. M1. line,. a. crossover. capacitance. C cr. exists.. Note. that M 1 and M 3 lines are not necessarily aligned to each other. This capacitance C cr is restricted within a neighborhood of the lines intersection. Outside the intersection neighborhood, M 2 line capacitance can be estimated by existing 2-D intralayer coupling capacitance models discussed in previous section. To derive the crossover model for C cr we adopt an empirical approach here, because the usual power series or numerical solutions for Poisson’s equation are not appropriate for VLSI simulation [3.25], [3.26]. In deriving these expressions, a rational function is first constructed to model each type of electrical flux variations with geometry variation. The rational functions are then multiplied to each other to form one flux component. Finally, all flux components are added, giving the lumped crossover capacitance C cr . Here, three flux components, C1 , C 2 , and, are involved. That is 27.

(49) C cr = C1 + C 2 + C 3 .. (3. 5). Capacitance C1 represents the area component from M 1 top surface to M 2 bottom surface. Capacitance C 2 represents the component from M 1 side wall to M 2 bottom surface. Capacitance C 3 represents the component from the M 2 side wall to M 1 top surface. To derive C1 , note that C1 is simply the plate-to-plate capacitance, and hence C1 WW = 1 2 ∈OX H2 ,. (3. 6). where ∈ox = 3.9 × 8.85 × 10 −14 F/cm and it could change to ∈eff easily by considering multi-layer effective dielectric in modern VLSI technology. The flux component C 2 is modeled as the product of rational functions in the following general form:. C2 ∈ OX. = c 1W. ⎛ × ⎜⎜ ⎝ H. 1. α1 2. H1 + c4S1. (S 1 × ⎞ ⎟⎟ ⎠. α 5. S2. ). α 2. ⎛ T1 ⎜⎜ ⎝ T1 + c 2 H. ⎛ − H 2 exp ⎜⎜ ⎝ c 3 (S 1 + c 6 H. 2. 2. ⎞ ⎟⎟ ⎠. α 3. ⎛ T1 ⎜⎜ ⎝ T1 + c 3 S 1. ⎞ ⎟⎟ ⎠. α 4. ⎞ ⎟ ) ⎟⎠ , (3. 7). where the ci ’s are constants and the α i ’s are the power coefficient, both to be determined later. We now explain the physical rationale behind each term adopted on the right-hand side of (3) for C 2 : 1) the W2 term follows from a power-law dependence of the capacitance on the line width [3.10], [3.11], [3.26]; 2) the S1 and S 2 terms are to catch the intrawire spacing dependence: Because the M 1 side wall to M 2 wire flux is reduced by intra- M 1 flux as shown in the. cross-section A of Fig. 3.3, C 2 decreases with reduced intra- M 1 spacing S1 ; similar impact can be induced by intra- M 2 spacing S 2 . Here, the same power 28.

(50) coefficient α 2 is used to reflect their same influence; 3) the term. (T1 / (T1 + c2 H 2 ))α 3. is adopted to model the fact that the flux originated from. side wall heavily relies on the wire side wall thickness with a power-law dependence [3.11]. The power-law dependence has been proved in [3.26] as a good approximation to the field strength between adjacent non-overlapping perpendicular surfaces. Note that this dependence will be weakened for large thickness (because such flux only exists at the side wall corner adjacent to the dielectric layer); the constant reflects this dependence weakening; 4) the terms. (T1 / (T1 + c3 S1 ))α 4. and (H 1 / (H 1 + c 4 S1 )). α3. are used to model the fact that C 2. decreases with reduced T1 / S1 as well as with reduced H 1 / S1 because of enhanced flux from M 1 to ground plane, as shown in the cross-section A of Fig. 3.3; and 5) the exponential term modifies the 1 / H 2 dependence constructed in (2), giving weakened H 2 impact with increased H 2 / S1 , because intra- M 1 flux prevents field lines from being pulled up to M 2 , electrode, as shown in the cross-section A of Fig. 3.1. To derive C 3 , we observe that C 3 is approximately a 180 0 turnover of C 2 . Therefore, similar mathematical patterns will be adopted to emulate the similar electrical flux distributions. Differences in C 2 and C 3 exist, however: C 2 has a larger plate next to (or under) the side wall flux, whereas C 3 has many narrower wirings ( M 3 wires) next to (or above) the side wall component. The consequence is that the side wall flux reduction induced by larger adjacent plane in C 2 and by adjacent wirings in C 3 will be different. C 3 is modeled in the following general form:. ⎛ ⎞ C3 T2 ⎟⎟ = d 1W1β 1 S 1β 2 S 2β 3 ⎜⎜ ∈ OX ⎝ T2 + d 2 H 2 ⎠ ⎛ H3 × ⎜⎜ H + ⎝ 3 d5S2. β4. ⎛ ⎞ − H2 ⎟⎟ exp ⎜⎜ ⎝ d 3 (S 2 + d 4 H 4 ) ⎠. ⎞ ⎟⎟ ⎠,. (3. 8) where the d i ’s are constants and the β i ’s are the power coefficients, both again to be determined later. 29.

(51) Now, similar physical explanation, as is the case with C 2 ,can be made for each term on the right-hand side of (4) for C 3 : 1) the W1 term shows the power-law dependence as be-fore; 2) the power terms of S1 and S 2 again catch the intra-wire spacing dependence, but here we use different power coefficients for them because their influence will be different. In fact, the influence of S 2 term in C 3 is weaker than in C 2 , for the impact in C 3 is weakened by the M 3 -to- M 2 flux; 3) the term (T2 / (T2 + d 2 H 2 )). β4. models the. fact that C 3 increases with increased T2 / H 2 ; 4) the exponential term further modifies the 1 / H 2 dependence constructed in (2), giving weakened H 2 impact with increased H 2 / S 2 , because intralayer flux prevents field lines from being pulled down to M 1 electrode; and 5) the last term (H 3 / (H 3 + d 5 S 2 )). β5. models. the impact of M 3 layer on C 3 , which gives reduced C 3 with reduced H 3 / S 2 , because the intralayer coupling flux between M 2 lines forms a shield that isolates the C 3 flux from the influence of the M 3 -to- M 2 flux. This shielding effect is very strong when S 2 is small, as shown.in the cross-section B of Fig. 3.3. This shielding effect is reduced with large S 2 , and hence, C 3 can be significantly reduced with reduced H 3 . Note that this effect is opposed to the phenomenon that C 3 increases with increased S 2 , as predicted by the power terms of. (S1 )β. 2. and. (S 2 )β. 3. . This term and the power-law term provide. contradictory influences by S 2 spacing, and our model can well describe these two opposing phenomena, which will later be demonstrated in Fig. 3.5. To determine all constants and power coefficients in (3) and (4) for C 2 and C 3 , we use the approach of least-mean-squares-errors fitting, and we obtain. 30.

(52) ⎛ C2 T1 0.2 = 3.73W20.6 (S1 × S 2 ) × ⎜⎜ cox ⎝ T1 + 0.035H 2 ⎞ ⎛ ⎞ ⎛ T1 H1 ⎟⎟ ⎟⎟0.12 × ⎜⎜ × ⎜⎜ ⎝ H 1 + 0.051S1 ⎠ ⎝ T1 + 0.851S1 ⎠ ⎞ ⎛ − H2 ⎟⎟ × exp⎜⎜ ( ) 0 . 7 S 0 . 4 H + 1 2 ⎠ ⎝. ⎞ ⎟⎟ ⎠. 0.64. 1.0. (3. 9) and ⎛ C3 T2 = 3.73W10.6 S10.2 S 20.1 ⎜⎜ cox ⎝ T2 + 0.035 H 2. ⎞ ⎟⎟0.64 ⎠. ⎛ ⎞ ⎛ H3 −H ⎟⎟ × ⎜⎜ × exp⎜⎜ ⎝ 0.7(S 2 + 0.4 H 2 ) ⎠ ⎝ H 3 + 0.015S 2. ⎞ ⎟⎟ ⎠. 3. . (3. 10). The root-mean-square error between the model and the numerical solutions is 6.71%, based on a total of 272 data points using the least-squares-error fitting approach. The 272 total data points were basically selected randomly, but with more dense data points chosen toward smaller dimension range (as the capacitance effect is more pronounced at smaller dimension range). A list of error distribution is shown is Table 3.4, which only displays a partial set of our data used for parameter fitting. The segments of M 2 outside the intersection neighborhood can be modeled by the 2-D capacitance formulas derived in previously section. The 1p , capacitance components here include 1) intralayer coupling capacitance C couple. which is the intra- M 2 flux in the wire region without M 3 wirings crossing above, 2p as shown in the cut-line C and cross section C of Fig. 3.3, 2) Ccouple , which is. the intra- M 2 flux in the M 2 region with M 3 wirings crossing above, as shown in the cut-line B and cross-sec-tion B of Fig. 3.3, and 3) line-to-ground capacitance C af in the region without M 3. wirings crossing above, as shown. in the cross section C of Fig. 3.3. These capacitances were obtained in previous section as. 31.

(53) C af cox. ⎛ W S2 = 2 + 2.217⎜⎜ H ⎝ S 2 + 0.702 H. ⎞ ⎟⎟ ⎠. 3..913. ⎛ ⎞ S2 ⎟⎟ + 1.171⎜⎜ S H + 1 . 51 ⎝ 2 ⎠. 0.764. 0.12. ⎛ ⎞ T2 ⎟⎟ × ⎜⎜ ⎝ T2 + 4.532 H ⎠ , (3. 11). Cll1 p T = 1.144 2 ∈ox S2. ⎛ H ⎜⎜ ⎝ H + 2.059S 2. ⎛ W2 + 1.158⎜⎜ ⎝ W2 + 1.874S 2. ⎞ ⎟⎟ ⎠. 0.1612. ⎞ ⎟⎟ ⎠. 0.0944. ⎛ W2 + 0.7428⎜⎜ ⎝ W2 + 1.592S 2. ⎛ H ⎜⎜ ⎝ H + 0.9801S 2. ⎞ ⎟⎟ ⎠. ⎞ ⎟⎟ ⎠. 1.144. 1.179. (3. 12) and ⎞ ⎛ C ll2 p T 2S 2 2S 2 ⎟⎟ = 1.412 2 exp⎜⎜ − − cox S2 ⎝ S 2 + 8.014 H 2 S 2 + 8.014 H 3 ⎠ 0.7371 0.25724 0.7371 ⎧⎪⎛ ⎫⎪ ⎞ ⎛ ⎞ ⎞ ⎛ H3 W2 H2 ⎟⎟ ⎟⎟ ⎟⎟ + ⎜⎜ × ⎨⎜⎜ + 1.1852⎜⎜ ⎬ ⎪⎩⎝ H 2 + 8.961S 2 ⎠ ⎪⎭ ⎝ W2 + 0.3078S 2 ⎠ ⎝ H 3 + 8.961S 2 ⎠ ⎞ ⎛ 2S 2 ⎟⎟ × exp⎜⎜ − ( ) S H H 3 + + 2 2 3 ⎠ . ⎝ (3. 13). where H = H1 + H 2 + T1 . In previous section, the above 2-D capacitance model provides accurate capacitance prediction, with a root-mean-quare error of 3.68, 4.45, and 16.13% for C af , C ll1 p , and C ll2 p ., respectively, compared with the numerical solutions. The total capacitance on a M 2 line of length L with nM 1 − M 2 crossings and another nM 2 − M 3 crossings can be calculated by combining the total intralayer coupling capacitance and the total crossover capacitance. The total intralayer coupling capacitance is easily determined as ( L − nW1 )C ll1 p + nW1C ll2 p + ( L − nW1 )C af .. The total crossover capacitance is calculated according to the following: 1) 32.

(54) each crossing of M 1 and M 2 gives a crossover capacitance Ccr ( M 2 − M 3 ) . To compute Ccr ( M 2 − M 3 ) , we need to view the triple-layer upside down before applying the above-developed formulas. That is, M 3 is now treated as the lower layer and M 1 the upper layer, which means that H 3 should be used as H 2 and H 2 should be used as H 3 in the formulas. H1 to be used in the formulas should be the spacing between M 3 and the next adjacent higher layer (say, M 4 if exists). If M 3 is the actual top layer, we have H1 = ∞ . Here, in such a case, we use the value H1 = 5μm as infinity. Combining the crossover and intralayer coupling capacitances, we have C total = n[C cr ( M1 − M 2 ) + C cr ( M 2 − M 3 ) ] + ( L − nW1 )C ll1 p + nW1C ll2 p + ( L − nW1 )C af. . (3. 14). Our model, which is derived based on three-metal layers, can be applied to a process with any number of metal layers. The crossover capacitance of a metal wire with the layer underneath it can be accurately predicted by our model, with or without above-passing wires. In the general multilayer case, any layer above the first layer or under the third layer is shielded from the second layer and, hence, does not affect the crossover capacitance. The agreement between our model and the numerical field solver [3.25] is shown in Table 3.4. In Table 3.4, the error is defined as Error = (model-Raphael/Raphael) × 100% . The final model has been tested based on 272 data points with a root-mean-square error of 6.71%. The valid ranges of the model. are. the. 0.16μm ≤ W1 , W2 ,W3 ≤ 2μm. following:. 0.16μm ≤ S1 , S 2 , S 3 ≤ 5μm 0.15μm ≤ T1 , T2 , T3 ≤ 1.2μm. ,. , ,. 0.16μm ≤ H1 , H 2 , H 3 ≤ 3μm. The valid ranges for our model were determined based on practical applications in integrated circuit (IC) technology. The upper bound for parameter S set at 5μm is to take care of both dense and sparse lines. The upper bounds for. and were set to match the practical dieletric and. metallization thicknesses. 33.