On-Chip ESD Protection Design With
Substrate-Triggered Technique for Mixed-Voltage I/O
Circuits in Subquarter-Micrometer CMOS Process
Ming-Dou Ker, Senior Member, IEEE, Kun-Hsien Lin, Student Member, IEEE, and Chien-Hui Chuang
Abstract—A new electrostatic discharge (ESD) protection
design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25- m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.
Index Terms—Electrostatic discharge (ESD), ESD protection
circuit, mixed-voltage I/O circuits, substrate-triggered technique.
I. INTRODUCTION
T
O IMPROVE circuit operating speed and performance, the device dimensions of MOSFET had been shrunk in the advanced deep-submicrometer integrated circuits. In order to follow constant-field scaling requirement and to reduce power consumption, the power supply voltages in CMOS ICs have been also scaled downwards. So, most microelectronic systems require the interfacing of semiconductor chips or subsystems with different internal power supply voltages. With the mix of power supply voltages, chip-to-chip interface I/O circuits must be designed to avoid electrical overstress across the gate oxide [1], to avoid hot-carrier degradation [2] on the output devices, and to prevent undesirable leakage current paths between the chips [3], [4]. For example, a 3.3-V I/O interface is generally required for ICs realized in CMOS processes with a normal internal power-supply voltage of 2.5 or 1.8 V. The traditional CMOS I/O buffer with of 2.5 V is shown in Fig. 1(a) with output and input stages. When an external 3.3-V signal is applied to the I/O pad, the channel of the output pMOS andManuscript received February 24, 2004; revised April 26, 2004. This work was supported by the National Science Council (NSC), Taiwan, R.O.C. under Contract NSC 93–2215-E-009–014. The review of this paper was arranged by Editor S. Kimura.
M.-D. Ker and K.-H. Lin are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).
C.-H. Chang is with the Intellectual Property Development Group, Faraday Technology Corporation, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TED.2004.835021
Fig. 1. Typical circuit diagrams for (a) the traditional CMOS I/O buffer, and (b) the mixed-voltage I/O buffer with the stacked-nMOS and the N-well self-biased pMOS.
the parasitic drain-to-well junction diode in the output pMOS cause the leakage current paths from the I/O pad to , as the dashed lines shown in Fig. 1(a). Moreover, the gate oxides of the output nMOS, the gate-grounded nMOS for input electro-static discharge (ESD) protection, and the input inverter stage are overstressed by the 3.3-V input signal.
To solve the gate-oxide reliability issue without using the additional thick gate oxide process (or referred to as dual-gate oxide in some CMOS processes [5], [6]), the stacked-MOS configuration had been widely used in the mixed-voltage I/O buffers [7]–[12], and in the power-rail ESD clamp circuits [13]. The typical 2.5/3.3 V-tolerant mixed-voltage I/O circuit is shown in Fig. 1(b) [8]. The pull-up pMOS, connected from the I/O pad to the power line, has the self-biased circuits for tracking its gate and n-well voltages, when the 3.3-V input signals enter the I/O pad. The maximum output voltage level of such a 2.5/3.3 V-tolerant I/O buffer is only (2.5 V).
ESD stresses on an I/O pad have four pin-combination modes: positive-to- (PS-mode), negative-to- (NS-mode), posi-tive-to- (PD-mode), and negative-to- (ND-mode) ESD
zapping conditions [14], [15]. To achieve high enough ESD ro-bustness of the CMOS output buffer, the CMOS buffer is gen-erally drawn with larger device dimensions and a wider spacing from the drain contact to the poly gate, which often occupy a larger layout area in the I/O cell. The -to- ESD clamp circuits across the power lines of CMOS ICs had been reported to effectively increase ESD robustness of CMOS I/O buffers [16]–[18]. Under the positive-to- ESD stress condition, the ESD current can be discharged through the parasitic diode of pMOS and the -to- ESD camp circuit to ground. There-fore, the traditional CMOS output buffer cooperating with the -to- ESD clamp circuit can sustain a much higher ESD stress [18]. But, due to the leakage current issue in the mixed-voltage I/O buffer, there is no parasitic diode connected from the I/O pad to power line in the mixed-voltage I/O buffer. Because of the limitation of placing a diode from the pad to in the mixed-voltage I/O circuits, the positive-to- ESD voltage zapping on the I/O pad cannot be discharged from the pad to power line, and cannot be discharged through the ad-ditional power-rail ( -to- ) ESD clamp circuit. Such pos-itive-to- ESD current on the I/O pad is discharged through the stacked-nMOS in the snapback breakdown condition. How-ever, the nMOS in stacked configuration has a higher trigger voltage ( ) and a higher snapback holding voltage ( ), but a lower secondary breakdown current ( ), as compared to the single nMOS [19]. Therefore, such mixed-voltage I/O circuits with stacked nMOS often have much lower ESD levels under the positive-to- ESD stress condition, as compared to the I/O circuits with a single nMOS [19], [20]. In addition, without the parasitic diode connected from the I/O pad to power line, the mixed-voltage I/O circuit also has a lower ESD level under the positive-to- ESD stress condition. Therefore, ESD pro-tection design for the mixed-voltage I/O circuits is mainly fo-cused on improving the ESD level under the positive ESD stress conditions.
To improve the turn-on uniformity among the multiple fingers of CMOS output buffer, the substrate-triggered design [21]–[24] had been reported to increase ESD robustness of the large-device-dimension nMOS. However, in the literature, the substrate-triggered technique was never reported to improve ESD robustness of the stacked-nMOS in the mixed-voltage I/O circuits. In this paper, the substrate-triggered stacked-nMOS device, which combines the substrate-triggered technique with the stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3 V tolerant mixed-voltage I/O circuit in a 0.25- m salicided CMOS process [25].
II. STACKED-NMOS WITHSUBSTRATE-TRIGGERED
TECHNIQUE
A. Stacked-nMOS Device
The finger-type layout pattern and the corresponding cross-sectional view of stacked-nMOS structure in the
Fig. 2. (a) Finger-type layout pattern, and (b) the corresponding cross-sectional view, of the stacked-nMOS device for mixed-voltage I/O circuit in a p-substrate CMOS process.
mixed-voltage I/O circuit are shown in Fig. 2, which in-cludes one pair of nMOS transistors connected in a stack configuration. The stacked-nMOS device is used as both of the pull-down device and ESD protection device for the I/O circuit. The nMOS transistor pair includes a first transistor (top nMOS transistor), having a drain connected to an I/O pad, and a gate ( ) connected to the power supply. A second nMOS transistor (bottom nMOS transistor) of the nMOS transistor pair is merged into the same active area of the first transistor, having a gate ( ) connected to the pre-driver of the mixed-voltage I/O circuit. The drain of the bottom nMOS transistor and the source of the top nMOS transistor are constructed together by sharing the common N+ diffusion region.
The independent control of the top and bottom gates of stacked-nMOS device allows the device to meet reliability limits during normal circuit operation. The voltage ( ) of the top nMOS is biased at the voltage (e.g., 2.5 V in a 2.5/3.3 V mixed-voltage I/O interface). The voltage ( ) of the bottom nMOS is at provided by the predrive to avoid leakage current through the stacked-nMOS structure, when the I/O circuit has a high-voltage input signal. With a high-voltage input signal at the pad (e.g., 3.3 V in a 2.5/3.3 V mixed-voltage I/O interface), the shared common diffusion region has ap-proximately a voltage level of - ( V). The ( V) is the threshold voltage of nMOS device. Therefore, the stacked-nMOS can be operated within the safe range for both dielectric and hot carrier reliability limitations.
Under the positive-to- ESD stress condition, the stacked-nMOS is operated in snapback breakdown, with
the bipolar effect taking place between the drain of the top nMOS and the source of the bottom nMOS. These two diffu-sions act as bipolar emitter and collector, respectively. Their spacing determines the base width and turn-on efficiency of the lateral bipolar transistor. The snapback mechanism of stacked-nMOS for conducting large amounts of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar transistor. The hole current ( ) generated from drain avalanche breakdown, drifting through the effective substrate resistance ( ) to ground, may elevate the substrate potential ( ) of the emitter–base junction in the lateral bipolar transistor. The voltage level, where the local substrate potential is elevated, depends on the relative proximity to the avalanching junction. When the emitter–base junction of bipolar transistor begins to weakly forward bias due to the increase of local substrate potential, additional electron current through the bipolar device is acted as “seed current” to drive a significant increase in the multiplication rate and avalanche current generation at the collector–base junction of the lateral bipolar transistor. Therefore, a “snapback” is seen, and the lateral bipolar transistor enters strong bipolar conduction to discharge ESD current.
B. Substrate-Triggered Stacked-nMOS Device
The snapback operation of stacked-nMOS devices de-pends on the substrate current ( ), which is created at the reverse-biased drain/substrate junction, to forward bias the source/substrate junction. Hence, the substrate resistance ( ) and substrate current ( ) are the important design parameters for ESD protection [26], [27]. However, the sub-strate-triggered technique can be used to generate the substrate current. With the substrate-triggered current, the trigger voltage ( ) of the stacked-nMOS device in mixed-voltage I/O circuits can be reduced for more effective ESD protection. In this paper, the substrate-triggered stacked-nMOS device, which combines the substrate-triggered technique with the stacked-nMOS de-vice, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs.
The finger-type layout pattern and the corresponding cross-sectional view of the new proposed substrate-triggered stacked-nMOS device are shown in Fig. 3(a) and (b), respectively. As shown in Fig. 3, a P+ diffusion is inserted into the center re-gion of stacked-nMOS device as the substrate-triggered point. The trigger current ( ) is provided by the special ESD de-tection circuit. An N-well structure is further diffused under the source region of this device to form a higher equivalent substrate resistance to improve turn-on efficiency of the parasitic lateral bipolar transistor in the stacked-nMOS device.
C. ESD Protection Circuit
The ESD protection design, which includes the substrate-trig-gered stacked-nMOS device and the substrate-trigsubstrate-trig-gered circuit for the mixed-voltage I/O circuits, is shown in Fig. 4. The sub-strate-triggered circuit is composed of the diode string, a pMOS device (P1), and an nMOS device (N1), to provide the sub-strate current for triggering on the parasitic lateral bipolar tran-sistor in the stacked-nMOS device, while the ESD voltage is
Fig. 3. (a) Finger-type layout pattern, and (b) the corresponding cross-sectional view, of the substrate-triggered stacked-nMOS device for mixed-voltage I/O circuit in a p-substrate CMOS process.
Fig. 4. Schematic circuit diagram of the substrate-triggered stacked-nMOS device with substrate-triggered circuit for the mixed-voltage I/O circuits.
applied on the I/O pad. The anode of the diode string in the sub-strate-triggered circuit and the collector of the parasitic bipolar transistor in the stacked-nMOS device are connected to I/O pad. The cathode of the diode string is connected to the source of P1. The emitter (the base) of the lateral bipolar transistor is con-nected to the power line (the drain of P1). The nMOS (N1) is connected between the base of the lateral bipolar transistor and the power line. The gates of P1 and N1 are connected together to the power line through a resistor. The resistor is realized by an N+ diffusion with a parasitic N+/P-sub diode to
Fig. 5. Cross-sectional view of the substrate-triggered stacked-nMOS device with substrate-triggered circuit for the mixed-voltage I/O circuits.
avoid the antenna effect during the CMOS process fabrication. The diode string including in the substrate-triggered circuit is composed of individual diodes formed by using P+ diffusion in the separated n-well structure. The total voltage drop across the diode string can be expressed as [28]
(1) where
= total voltage drop across the m diodes, = the number of diodes in the diode string, = ideality factor, and
= the beta gain of the parasitic vertical pnp bipolar transistor in the diode structure.
During the ESD stress condition, the pMOS (P1) device is used in conjunction with the diode string to provide the substrate current to trigger the parasitic lateral bipolar transistor in the stacked-nMOS device. Once the lateral bipolar transistor in the stacked-nMOS device has been turned on, the ESD current is discharged from the I/O pad to .
D. Operating Principles
Fig. 5 shows the cross-sectional view of the substrate-trig-gered stacked-nMOS device with the substrate-trigsubstrate-trig-gered circuit for protecting mixed-voltage I/O circuits. In the normal circuit operating condition, the substrate-triggered circuit should remain in a nonconductive state, so that it does not interfere with the voltage levels on the I/O pad. For the 2.5/3.3 V mixed-voltage IC application, 3.3 V tolerance was desired for normal circuit operation with a 2.5-V supply in the chip. The turn-on voltage of the substrate-triggered circuit roughly
equals to , where the is the
threshold voltage of the pMOS (P1). The turn-on voltage can be adjusted by varying the numbers of the diodes in the diode string. To satisfy the requirement in the 2.5/3.3 V mixed-voltage application, the number of the diodes in the diode string should
be adjusted to let the turn-on voltage greater than 3.3 V. When the I/O pad is applied with a high input voltage of 3.3 V, pMOS (P1) is still kept off, and the local substrate of the stacked-nMOS is biased at by the turned-on nMOS (N1). With the diode string to block the 3.3 V input voltage on the I/O pad, the pMOS (P1) with thin gate oxide has no gate-oxide reliability issue during the normal circuit operating condition.
The choice of a particular diode string is also determined by the specified pin leakage current at a fgiven temperature. If a lower input leakage is desired, the numbers of the diodes in the diode string should be increased. Since the diode string is not the main ESD current discharge path, its perimeter can be adjusted with less impact on ESD performance. The leakage current problem of the diode string comes from the parasitic vertical pnp bipolar transistor of each diode formed by the P+ diffusion in an n-well. The pMOS (P1) in conjunction with a diode string is used to reduce the leakage current at the I/O pad in the normal operating condition. Moreover, the nMOS (N1) with its gate biased at is always turned on to bypass any leakage current, which may trigger on the lateral npn bipolar transistor in the normal circuit operating condition.
Under the positive-to- ESD stress condition, the gate of the pMOS (P1) has an initial voltage level of V, while the pin is grounded but the pin is floating. The sub-strate-triggered circuit will provide the trigger current flowing through the diode string and the pMOS (P1) into the p-substrate,
when . For a given , the
sub-strate-triggered circuit must supply an enough trigger current ( ) to raise up the local substrate potential, so that
V for triggering on the parasitic lateral n-p-n bipolar transistor in the stacked-nMOS device. Once the lateral bipolar transistor is turned on, the ESD current is dis-charged from the I/O pad through the lateral bipolar transistor to the grounded . The provided by the substrate-trig-gered circuit is determined by the diode string and the size of pMOS (P1). With an appropriate trigger current ( ), the sub-strate potential is raised up to trigger on the lateral bipolar tran-sistor and to reduce the trigger voltage of the ESD protection circuit. Therefore, ESD robustness of the mixed-voltage I/O cir-cuits with the stacked-nMOS device can be effectively improved by this new proposed substrate-triggered design.
A modified connection on the ESD protection design with the substrate-triggered stacked-nMOS device to protect the mixed-voltage I/O circuits is shown in Fig. 6. The substrate-triggered circuit is connected from the self-biased n-well of the pull-up pMOS, where the parasitic drain-well diode between the I/O pad and the n-well essentially exists in the pMOS device structure. Under the positive-to- ESD stress condition, the trigger current flows through the parasitic diode and the sub-strate-triggered circuit to raise the local substrate potential for triggering on the lateral bipolar transistor in the stacked-nMOS device. The main purpose of this modified connection on the ESD protection circuit is to provide the mixed-voltage I/O buffer with a higher ESD robustness but no extra additional capaci-tance (generating from the ESD detection circuit) to the I/O pad. This modified design is more suitable for high-speed I/O appli-cations, which often require a lower input loading capacitance to the I/O pad.
Fig. 6. Modified design of the substrate-triggered stacked-nMOS device with substrate-triggered circuit for the mixed-voltage I/O circuits without generating extra additional capacitance to the I/O pad.
Fig. 7. (a) Measured I–V characteristics of the substrate-triggered stacked-nMOS device with different substrate-triggered currents (I ). (b) The relation between the trigger voltage of the stacked-nMOS device and the substrate-triggered current (I ).
III. EXPERIMENTALRESULTS
A. Characteristics of the Substrate-Triggered Stacked-nMOS Device
The measured current–voltage (I–V) characteristics of the substrate-triggered stacked-nMOS device with different sub-strate-triggered currents (measured by a Tek370 A curve tracer) are shown in Fig. 7(a). The relation between the trigger voltage
Fig. 8. TLP-measured I–V curves of the stacked-nMOS device with different substrate-triggered currents.
Fig. 9. Dependence ofI level on the substrate-triggered current (I ) under the different channel widths of substrate-triggered stacked-nMOS device.
and the substrate-triggered current ( ) is summarized in Fig. 7(b). As shown in Fig. 7, the trigger voltage of the para-sitic lateral bipolar transistor in the stacked-nMOS device is decreased while the substrate-triggered current is increased. The trigger voltage of the stacked-nMOS device without the substrate-triggered current is 8.5 V (by junction breakdown). However, the trigger voltage can be reduced to only 5.3 V when the substrate-triggered current is 8 mA.
To investigate the turn-on behavior of the stacked-nMOS device during high ESD current stress, transmission line pulse (TLP) generator with a pulse width of 100 ns is used to mea-sure the second breakdown current ( ) of the device. The TLP-measured I–V curves of the stacked-nMOS device with different substrate-triggered currents are shown in Fig. 8. The TLP-measured results are consistent with the measured I–V characteristics shown in Fig. 7. The trigger voltage of the stacked-nMOS device is decreased when the substrate-trig-gered current is increased. The dependence of level on the substrate-triggered current ( ) under the different channel widths of substrate-triggered stacked-nMOS device is shown in Fig. 9. The level of the substrate-triggered stacked-nMOS device can be improved while the substrate-triggered current is increased. For example, the level is increased from 2.5 to 3.4 A for the stacked-nMOS device with a channel width of 240 m, when the substrate-triggered current is increased from 0 to 2 mA. The level of the substrate-triggered stacked-nMOS device is saturated when the substrate-triggered current is high enough to fully trigger on the parasitic bipolar transistor in the stacked-nMOS device.
Fig. 10. Comparison of the leakage currents of the mixed-voltage I/O buffers with or without the proposed substrate-triggered circuit. The mixed-voltage I/O buffer in this measurement has a channel width of 240m in the stacked nMOS and a channel width of 480m in the pull-up pMOS.
Fig. 11. Leakage currents of the mixed-voltage I/O buffers with or without the substrate-triggered circuit under different temperatures.
Based on the experimental results, the ESD protection circuit can be designed with the special substrate-triggered circuit to generate the substrate current to reduce the trigger voltage and to further increase ESD robustness of the stacked-nMOS device in the mixed-voltage I/O buffers.
B. Leakage Current
The leakage current under normal circuit operating condition is a concern for an ESD protection device connected to an I/O pin. The leakage currents of the fabricated mixed-voltage I/O buffers with or without the proposed substrate-triggered circuit are measured and compared in Fig. 10. The leakage current is measured (using a HP4155) by applying a voltage ramp from 0 to 3.3 V to the I/O pad under the bias condition of 2.5-V and 0-V at a room temperature of 25 C. In Fig. 10, the maximum leakage current of the mixed-voltage I/O buffer with (without) the substrate-triggered circuit under 3.3-V bias at the I/O pad is only 1.1 nA (0.2 nA), which is acceptable for general I/O applications. The mixed-voltage I/O buffer in this measure-ment has a channel width of 240 m in the stacked nMOS and a channel width of 480 m in the pull-up pMOS. The leakage currents of the mixed-voltage I/O buffer with or without the sub-strate-triggered circuit, under the 3.3-V voltage bias at the I/O pad at different temperatures are shown in Fig. 11. The leakage current of the mixed-voltage I/O buffer is increased while the temperature is increased. In Fig. 11, the leakage current of the mixed-voltage I/O buffer with the substrate-triggered circuit at the temperature of 25 C (125 C) is 1.1 nA (0.2 ). The diode
Fig. 12. Positive-to-V (PS-mode) HBM ESD levels of the mixed-voltage I/O buffers with or without the substrate-triggered circuit, realized in a 0.25-m CMOS process with silicide-blocking process.
TABLE I
THEHBM ESD ROBUSTNESS OF THEMIXED-VOLTAGEI/O BUFFERS
WITH ORWITHOUT THEPROPOSEDSUBSTRATE-TRIGGERED
CIRCUITUNDER AFIXEDDEVICEDIMENSION
string of the substrate-triggered circuit in this investigation in-cludes six diodes. More diodes can be added into the diode string to further reduce the leakage current of the mixed-voltage I/O buffer with the substrate-triggered circuit.
C. ESD Level
The PS-mode human-body-model (HBM) ESD levels of the mixed-voltage I/O buffers with or without the substrate-trig-gered circuit are measured and compared in Fig. 12. The failure criterion is defined as the leakage current of the circuits after ESD zapping is greater than 1 under the normal operating voltage of 3.3 V. The original mixed-voltage I/O buffers with different stacked-nMOS channel widths are also tested as a ref-erence. As shown in Fig. 12, the HBM ESD level of the mixed-voltage I/O buffers with the substrate-triggered circuit is almost linearly increased while the stacked-nMOS channel width is in-creased. It implies that the parasitic lateral bipolar transistor in the stacked nMOS can be uniformly turned on to discharge ESD current by the substrate-triggered circuit. The HBM ESD level of the mixed-voltage I/O buffer (with stacked-nMOS channel width of 240 m) can be obviously improved from the original 3.4 kV up to 5.6 kV (an increase of ) by using the sub-strate-triggered technique.
The HBM ESD robustness of the mixed-voltage I/O buffer, with or without the substrate-triggered circuit, under the four pin-combination modes of ESD stress on the I/O pad, is listed in Table I. The stacked nMOS of the mixed-voltage I/O buffer in this ESD test has a of 120/0.5 m, and the pull-up pMOS of the mixed-voltage I/O buffer has a of 240 m/0.5 m.
As shown in Table I, the PS-mode ESD level of the mixed-voltage I/O buffer is worst among four ESD-zapping modes. The PS-mode ESD level for the mixed-voltage I/O buffer with substrate-triggered circuit can be obviously improved from the original 2.1 up to 3 kV. The experimental result has verified the effectiveness of the substrate-triggered design to improve ESD level of mixed-voltage I/O circuits.
IV. CONCLUSION
To improve ESD robustness of the stacked-nMOS device in the mixed-voltage I/O circuit, the stacked-nMOS device with new proposed substrate-triggered circuit, has been de-signed and successfully verified in a 0.25- m salicided CMOS process. The I–V characteristics of stacked-nMOS device with substrate-triggered technique have been measured to verify its effectiveness. By using this substrate-triggered design, the trigger voltage of the stacked-nMOS device can be reduced from the original 8.5 V to become 5.3 V to ensure effective protection for the mixed-voltage I/O circuits. The HBM ESD level of the mixed-voltage I/O buffer with a stacked-nMOS of 240- m channel width can be improved from the original 3.4 up to 5.6 kV by the substrate-triggered circuit. Without using the thick gate oxide, this new proposed ESD protection design is very useful in the sub-quarter-micrometer CMOS processes for effectively protecting the mixed-voltage interface circuits on the input and output pins.
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Ming-Dou Ker (S’92–M’94–SM’97) received the
B.S. degree from the Department of Electronics Engineering, and the M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1986, 1988, and 1993, respectively.
In 1994, he joined the VLSI Design Department of Computer and Communication Research Lab-oratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, as a Circuit Design Engi-neer. In 1998, he was a Department Manager in the VLSI Design Division of CCL/ITRI. In 2000, he was an Associate Professor in the Department of Electronics Engineering, National Chiao-Tung University. In the field of reliability and quality design for CMOS integrated circuits, he has published over 190 technical papers in international journals and conferences. He holds 177 patents on the reliability and quality design for integrated circuits, of which 79 are U.S.-held patents. His inventions regarding ESD protection design and latchup prevention methods have been widely used in modern IC products. He has been invited to teach or aid in ESD protection design and latchup prevention by more than 200 IC design houses and semiconductor companies in the Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. or in the Silicon Valley, San Jose, CA. His research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed or mixed-voltage I/O interface circuits, sensor circuits, and semiconductors.
Dr. Ker has also received many research awards from ITRI, the Dragon Thesis Award (by Acer Foundation), National Science Council, and National Chiao-Tung University. He has been a Member of the Technical Program Committee and as Session Chair of some International Conferences. He was elected as the first President of the Taiwan ESD Association in 2001. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by Junior Chamber International (JCI).
Kun-Hsien Lin (S’03) received the B.S. degree from
the Department of Electronics Engineering and the M.S. degree from the Institute of Electronics, both from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1996 and 1998, respec-tively. He is currently working toward the Ph.D. de-gree at the Institute of Electronics, NCTU.
From 2000 to 2001, he was a Product Engineer in the Taiwan Semiconductor Manufacturing Company. His current research interests include ESD physics, semiconductor devices, and on-chip ESD protection design in CMOS ICs.
Chien-Hui Chuang received the B.S. and M.S.
degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1995 and 2001, respectively.
From 1995 to 1997, he was in military service at the Army of the Republic of China. From 1997 to 1999, he had been a nonvolatile memory design engineer in the HOLTEK semiconductor Corpora-tion, Hsinchu. Currently, he is a design engineer of Intellectual Property Development in the FARADAY Technology Corporation, Science-Based Industrial Park, Hsinchu, Taiwan. His research interests include ESD protection circuit and I/O interface circuit design.
