Role of Positive Trapped Charge in Stress-Induced
Leakage Current for Flash EEPROM Devices
Tahui Wang, Senior Member, IEEE, Nian-Kai Zous, and Chih-Chieh Yeh
Abstract—The transient behavior of hot hole (HH) stress-in-duced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tun-neling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence with the power factor about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time-and field-dependence of SILC time-and the substrate current. Based on our model, the evolution of threshold voltage shift with read-dis-turb time in a Flash EEPROM cell is derived. Finally, the depen-dence of SILC on oxide thickness is explored. As oxide thickness re-duces from 100 Å to 53 Å, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).
Index Terms—Flash EEPROM, positive trapped charge, read-disturb, stress-induced leakage current (SILC), substrate current, transient behavior.
I. INTRODUCTION
H
IGH-FIELD stressing during program/erase (P/E) cycles in Flash EEPROM operation can lead to a significant in-crease in low-level leakage current in tunnel oxide. Such stress-induced leakage current (SILC) has received a lot of attention because of its significance to endurance and data retention of a Flash memory cell. Several mechanisms have been proposed for SILC, including positive charge-assisted tunneling (PCAT) [1], [2], neutral trap-assisted tunneling (TAT) [3], and thermally-as-sisted tunneling at weak spots of the Si/SiO surface due to a barrier height lowering [4]. Despite extensive research on SILC, the role of positive trapped charge in SILC and related read-dis-turb in a Flash cell is still not clear. DiMaria et al. concluded from their experimental result that positive oxide charge plays no part in SILC conduction in oxides by Fowler–Nordheim (FN) stress [5]. Dumin [6] and Ricco [7] showed that neutral TAT is the original cause of SILC for oxide thickness from 40 Å to 130 Å. The concept of inelastic TAT in SILC was proposed by Takagi et al. [8] and is supported by thetemperature-depen-Manuscript received March 4, 2002; revised July 31, 2002. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC90-2215-E009–069. The review of this paper was arranged by Editor J. Vasi.
T. Wang and N.-K. Zous are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 30049, Taiwan, R.O.C. (e-mail: twang@cc.nctu.edu.tw).
C.-C. Yeh was with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 30049, Taiwan, R.O.C. He is now with Macronix International, Hsinchu 30049, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TED.2002.804711
dence of SILC [9], the noise of the tunneling current [10], and the energy-loss measurement [11]. On the other side, Ter-amoto et al. claimed that excess leakage current induced by FN stress is attributed to injected holes produced by high-energy electrons [12]. Shuto et al. found that hot hole (HH) injection during source-side FN erase is the major cause for read-disturb degradation in Flash cells [13]. Matsukawa et al. further showed that SILC caused by positive oxide charge can be reduced by hot electron injection or ultraviolet irradiation [14]. The more recent result of Meinertzhagen et al. [15] has revealed that the role of positive oxide charge in SILC changes with stress and measurement polarities.
In addition, Dumin et al. found that FN SILC contains a dc component, as well as a transient component [16]. In this work, the dc component is attributed to neutral TAT. The transient part is realized due to oxide trap charging and discharging and can be characterized by time-dependence based on the tunneling front model [16]. A threshold voltage shift of 1.0 V resulting from the transient part of SILC in a Flash cell was reported by Kato et al. [17]. Although tremendous efforts have been made to investigate the SILC mechanisms and characteristics, most of previous studies were conducted on a MOS capacitor with uni-form FN stress. In order to correlate with edge FN erase-induced degradation in Flash EEPROM cells, the transient behavior of SILC by band-to-band HH stress will be explored.
In this paper, various stacked gate Flash cells and conven-tional gate nMOSFETs were used. To measure FN SILC and HH SILC directly, nMOSFETs with a long source/drain edge were specially fabricated. The test devices have a gate length of 0.6 m and a total gate area of 9 10 cm . The gate oxide thickness ranges from 53 Å to 100 Å. In theoretical part, we develop a transient model to calculate the electron and hole leakage components in SILC. In our model, a Coulombic po-tential caused by a positive trapped charge is included in the tunneling barrier. Image force and surface quantization effects are taken into account. The Wentzel–Kramer–Brillouin (WKB) method is used to evaluate electron and hole tunneling rates. In measurement, a charge separation technique is employed to characterize individual electron and hole components in SILC. The measured HH SILC will be analyzed with respect to time-, field-, and oxide thickness-dependence.
II. HOT HOLESILC CHARACTERIZATION
The transient behavior of SILC by positive FN stress and band-to-band HH stress is shown in Fig. 1. The oxide thickness is about 100 Å. The +FN stress is performed at V for 2000 s. The band-to-band HH stress is at V and V for 500 s. Under the two stress conditions, oxide
Fig. 1. Measured gate current transients in +FN stressed and HH stressed nMOSFETs. The oxide field in measurement is about 6.5 MV/cm. The shaded areasQ (HH) and Q (FN) represent total charge flowing to the gate carried by the transient component of the SILC in the measurement period.
Fig. 2. Drain current versus gate bias in a nMOSFET before and after band-to-band HH stress. After stress, GIDL current shifts to the left due to positive oxide charge creation andV is unchanged.
trap generation is almost saturated. The oxide trapped charge in the two stressed devices is measured from a threshold voltage method and a GIDL current method [18]. The reason of using a GIDL method for the HH stressed device is that threshold voltage in a nMOSFET is not sensitive to localized positive trapped charge, as shown in Fig. 2. After HH stress, GIDL current shifts to the left due to positive oxide charge cre-ation and threshold voltage is nearly unchanged. In Fig. 1, the HH SILC apparently exhibits a more pronounced transient ef-fect. The transient magnitude is about two orders of magnitude larger than the +FN SILC. The shaded area denoted by
and is an integral of the SILC transient in a measure-ment interval from 0.1 s to 300 s. The integral represents total charge flowing to the gate carried by the transient component of SILC. The measured and in the two devices are com-pared in Table I. and are normalized to stressed gate areas. The HH stress region in the channel is assumed to be 0.2 m [19]. It is interesting to note that is less than in the +FN stressed device while is about ten times larger than in the HH stressed device. If the transient compo-nent is contributed completely by charge trapping/detrapping, should not exceed the total trapped charge in the
oxide ( ). The result can be
understood because the FN SILC transient is caused by
neg-Fig. 3. HH and FN SILC transients plotted on alog(I)-log(t) scale. The symbols are measurement data points and the solid lines represent a least square error fit.The measurement condition is the same as in Fig. 1.
ative oxide charge detrapping [16]. Thus, should not exceed the total trapped charge in the oxide. On the other side, suggests that the HH SILC transient should contain another leakage component in addition to the displacement current resulting from oxide charge trapping/de-trapping.
Moreover, we plot the FN and HH SILCs on a log-log scale in Fig. 3. Both the SILCs follow a straight line, i.e., power law time-dependence. However, a slight difference in the slope of the transients is noticed. The FN SILC has a slope close to 1, which is in agreement with previously published results [16]. The HH SILC in Fig. 3 was measured for three decades of time. The measured slope significantly deviates from the theo-retical value of 1 obtained from the tunneling front model [16]. This significant deviation provides another evidence that the HH SILC transient cannot be explained simply by oxide charge trap-ping/detrapping.
III. HH SILC MECHANISM
To explain the observed differences between FN SILC and HH SILC, a positive trapped charge-assisted tunneling model is proposed for the HH SILC, as illustrated in Fig. 4. Positive trapped charges are created during HH stress. The HH SILC transient in our model actually consists of two parts, namely, and (see Fig. 4). represents positive oxide charge de-trapping current and denotes positive oxide charge-assisted
Fig. 4. Illustration of two major SILC transient components, namely,I and I , at a positive measurement gate bias in an HH stressed n-MOSFET. The open circle represents holes.T 1 and T 2 are electron tunneling probability.
electron tunneling current. Note that is a displacement
cur-rent and is a conduction current. For ,
the HH SILC is dictated by . The transient behavior of arises from that the positive oxide charges helping electrons to tunnel through the oxide are themselves tunneling out to the Si substrate in measurement. An analytical model relating the time-dependence of to positive oxide charge tunnel detrap-ping was derived in our previous publication [20]. The time-de-pendence of is expressed as
(1)
(2)
where , represents an average oxide
charge volumetric concentration; in (1) denotes the Gamma function; and are electron and hole tunneling character-istic times, respectively [21]; and are effective tunneling barrier heights for electrons and holes, respectively; and other variables have their usual definitions. Similarly, the expression for is given as
(3) where is the area of the HH stress region. Detailed numer-ical analysis for the time- and field-dependence of and including positive trapped charge enhanced tunneling will be discussed later.
Since is a hole current and is an electron current, a charge separation technique shown in Fig. 5 can be used to mon-itor at the substrate and at the source and the drain, spectively. Fig. 6 shows the charge separation measurement re-sult for and before and after HH stress. The pre-stress is negligible until is above 8 V, where anode HH injection is appreciable [22]. After HH stress, remarkable and
are both observed in the low-field regime. The stress-induced arises from the discharging of hole traps near the substrate. In Fig. 7, we plot the stress-induced versus HH SILC at different stress times and bias conditions. A linear correlation between them is obtained. This correlation provides strong evidence that positive oxide charge plays an important role in HH SILC.
Fig. 5. Illustration of a charge separation technique.I represents positive oxide detrapping current, flowing to the substrate.I flows to the source and the drain..
Fig. 6. Gate current and substrate current versus measurement gate bias before and after HH stress.
Fig. 7. Stress-induced substrate current versus SILC measured at different stress times and conditions. The oxide field in measurement is 3 MV/cm.
IV. NUMERICALSIMULATION OFHH SILC
In our calculation, a Coulombic potential well caused by a positive trapped charge is included in the electron tunneling bar-rier (see Fig. 4). This Coulombic potential acts as a sequen-tial tunneling center and can increase leakage current at local-ized spots. Although the actual problem is a three-dimensional one, the purpose here is to understand the first-order behavior. Thus, a one-dimensional treatment of the trapped charge effect is adopted as an approximation. The total potential energy as a function of distance is then given by
potential lowering due to tunnel electron image force;
distance of the trapped positive charge from the Si/SiO interface;
modification of the tunnel barrier by a positive trapped charge.
In Fig. 4, the electron tunneling probability from the conduc-tion band of the Si substrate to the site of the positive trapped charge at is denoted by . The subsequent electron transi-tion probability from to the SiO conduction band is . By using the WKB approximation, and can be evaluated as follows:
(7)
and
(8)
Since is larger than in our measurement interval, we ne-glect for simplification. Thus, the current flow through the modified potential barrier can be expressed as [23]
(9)
where 10 Amp V in orientation [23].
Since the trapped positive charge is tunneling out through a trapezoid barrier, the tunneling time of the trapped hole to the valence band of the Si substrate is formulated according to the WKB approximation [21]
(10) where is the hole trap energy. The transient behavior of and positive oxide charge detrapping current are then formu-lated as follows:
(11)
(12)
where
positive oxide charge tunneling time; cross section of the PCAT center;
Fig. 8. Simulated and measured I and I transients in an nMOSFET by band-to-band HH stress.t = 90 A. The oxide field is 6.0 MV/cm, 5.0 MV/cm, and 4.2 MV/cm. The symbols represent measurement data points and the solid lines are from simulation. The1=t dependence of I implies uniform +Q distribution in a tunnel detrapping distance.
volumetric positive oxide charge concentration; area of the HH stress region.
The parameters used in our simulation are given in Table II. The hole trap volume density ( ) is extracted from the exper-imental data.
Comparing (11) and (12), the is expected to have a larger field dependence than . The reason is that the electron effec-tive tunneling barrier is smaller and thus the electron tunneling probability exhibits a stronger field dependence than hole tunneling probability . In addition, the supply function term of (9) that is contributed by the surface quan-tization effect [23] is also a factor.
V. RESULTS ANDDISCUSSION A. Time- and Field-Dependence
The measured and calculated time-dependence of and at different oxide fields is shown in Fig. 8. The symbols repre-sent measurement data and the solid lines are from simulation. A close look reveals that the HH SILC and exhibit a slightly
dif-ferent slope, i.e., and with . As shown
in (2), the factor is related to electron and hole tunneling masses and barriers. The dependence of was also noticed by other groups ( ) [15]. The field-dependence of the HH SILC and is plotted in Fig. 9. The SILC and stress-induced are measured at s. Two distinguished features are noted.
Fig. 9. Field-dependence of electron tunneling current (I ), substrate current (I ), and gate current (I = I + I ). The symbols represent measurement data att = 0:2 s and the lines are from simulation.
Fig. 10. Simulated threshold voltage shift versus read-disturb time from the SILC in Fig. 8.E = 5 MV=cm. The measured threshold voltage shift versus read-disturb time in a stacked gate Flash EEPROM after 10 P/E cycles is shown in the inset. The applied control gate voltage in read-disturb isV = 6 V.
First, the measured hole detrapping current ( ) is nearly inde-pendent of an oxide field, which is consistent with the calculated result. As a contrast, the HH SILC exhibits small field depen-dence in the low-field range ( 3.5 MV cm) and strong field dependence in the medium field range ( MV MV cm). The reason is that the major component of the HH SILC is the hole detrapping current ( ) at low fields and is the electron tunneling current ( ) at higher fields. Our model shows that the larger field dependence of results from a smaller ef-fective tunneling barrier for electrons and the supply function term . The component will become more significant in multi-level cells (MLC) with regard to read-disturb since a larger read gate bias is usually required in MLC.
In Fig. 10, the read-disturb characteristics due to the tran-sient effect of HH SILC are simulated. According to the tun-neling front model, threshold voltage shift caused by oxide charge trapping/detrapping should vary linearly with the loga-rithm of time [24]. Instead, our simulation shows the read-dis-turb caused has power law time-dependence at an oxide field of 5 MV/cm. The obtained power factor is approximately 0.25, which can be derived from the integration of . The measurement result in a stacked gate Flash EEPROM device ( ) after 10 P/E cycles are plotted in the inset of
Fig. 11. SHE injection effect on HH SILC.t = 100 A.
Fig. 10 as a reference. The Flash device is programmed by hot electron injection at V and V at the drain side and erased by edge FN injection at V and V at the source side. A linear relationship of versus in a
log-log scale is obtained with a slope of 0.3. It is not our
in-tention to compare between measurement and calculation. The calculated is based on the measured SILC in a conven-tional gate nMOSFET, which has a quite different stress con-dition from the P/E stress in a Flash cell. Thus, the calculated and measured in Fig. 10 have a large difference in mag-nitude although they have similar time-dependence. The power law-dependence of on read-disturb time was also found by other groups [17] with a power factor of 0.28 for at
V.
B. Reduction of HH SILC
HH SILC can be greatly reduced by annealing the positive oxide charges. Here, substrate hot electron (SHE) injection at V and V is utilized to neutralize posi-tive trapped charges created by HH stress. Since the substrate injection current is relatively large (2 10 A cm ), positive oxide charge neutralization is achieved via either recombination or compensation by the injected electrons. The electron filling efficiency is strongly dependent on an oxide field and is less de-pendent on electron injection energy [25]. The filling (recombi-nation) efficiency is better at a lower oxide field. For this reason, a smaller gate bias was chosen in the SHE filling. The effect of positive charge neutralization on HH SILC is shown in Fig. 11. The HH SILC is greatly reduced by the filling. Its steady-state level is below 1 pA after the filling. After subsequent HH stress, the HH SILC transient reappears. The HH stress and SHE filling cycle is repeated in Fig. 11. No noticeable difference is observed between the two cycles, implying that the SHE filling itself does not introduce additional stress effect. Fig. 12 shows the corre-sponding change in . A reduction of by an order of mag-nitude is observed after the filling. From this study, it can be concluded that can be used as an effective monitor for PCAT in SILC.
C. Oxide Thickness Dependence
In the above discussion, the role of PCAT in SILC has been substantiated for . On the other side, it is also well
Fig. 12. Transient characteristics of positive oxide charge detrapping current (jI j) with and without SHE filling.
Fig. 13. Gate current versus gate bias in nMOSFETs before and after band-to-band HH stress.t = 53 A, 70 Å, and 90 Å.
published that neutral TAT is the dominant SILC mechanism in ultrathin oxides. It is interesting to investigate the transition be-tween these two mechanisms. Stress-induced and in large gate area nMOSFETs with , 70 Å, and 53 Å are measured. Negative channel FN stress was performed at
MV cm. Fig. 13 shows pre-stress and post-stress and Fig. 14 shows the corresponding change in . The pre-stress in Fig. 14 is negligible until anode hot hole (AHH) injection for and 90 Å and valence electron tunneling for occur [22]. After stress, a remarkable appears even at a small gate bias in thicker oxides while this stress-in-duced vanishes at low fields in the 53 Å oxide. The reduction of in the thinner oxides can be explained as follows. Since a constant voltage stress is applied, the stress gate voltage is smaller for thinner oxides. Thus, the injected electrons have less energy and the creation of trapped holes is reduced [26]. Further characterization shows that the SILC in the 53 Å oxide does not contain a transient component. According to the published results in literature [8], [11], [27], the responsible mechanism
Fig. 14. Substrate current versus gate bias in nMOSFETs before and after band-to-band HH stress.t = 53 A, 70 Å, and 90 Å. The stress-induced I vanishes at low fields in the 53 Å oxide device. TAT represents TAT and AHH represents AHH injection.
Fig. 15. Oxide thickness dependence of SILC and stress-inducedI measured atE = 5 MV/cm. The dominant SILC mechanism changes from PCAT in thick oxides to TAT in thinner oxides.
of the SILC in thinner oxides should be TAT. The TAT current strongly depends on the oxide thickness and increases as the oxide thickness is reduced [27]. In Fig. 15, the oxide thickness dependence of SILC and is shown. The measurement field is at 5 MV/cm. As reduces to 53 Å, the correlation between stress-induced and SILC does not exist. In other words, the dominant SILC mechanism changes from PCAT at
to TAT at .
VI. CONCLUSION
Positive trapped charges created during edge FN erase play an important role in SILC and related read-disturb in Flash EEPROM cells. A power law dependence of on read-dis-turb time, resulting from the transient effect of PCAT, is derived from measurement and simulation. Stress-induced low-field can be used as an effective monitor for PCAT effect in
SILC. By using an appropriate hot electron injection technique, the PCAT current can be greatly reduced. In ultrathin oxides (53 Å), the correlation between SILC and no longer exists. We conclude that the dominant SILC mechanism changes from PCAT in thicker oxides (100 Å) to TAT in ultrathin oxides.
ACKNOWLEDGMENT
The authors wish to thank Dr. C. Huang for many useful dis-cussions.
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Tahui Wang (S’85–M’86–SM’94) was born in
Taoyuan, Taiwan, R.O.C., on May 3, 1958. He received the B.S.E.E. degree from National Taiwan University, Taipei, in 1980, and the Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1985.
From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung Uni-versity, Hsinchu, Taiwan, where he is currently a Professor. His research inter-ests include hot-carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices, and nonvolatile semiconductor devices.
Dr. Wang was granted the Best Teacher Award by the Ministry of Education, R.O.C. He has served as Technical Committee Member of many international conferences, among them IEDM and IRPS. His name is listed in Who’s Who in the World (2001).
Nian-Kai Zous received the B.S. degree in
elec-tronics engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1996, where he is currently pursuing the Ph.D. degree. His research interests include thin oxide reli-ability and hot-carrier effects in deep submicrometer MOSFETs.
Chih-Chieh Yeh received the B.S. and M.S. degrees
in electrical engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. 1997 and 1999, respectively.
In 2001, he joined Macronix International, Hsinchu, Taiwan, R.O.C., where he has been working on the device characterization of Flash memories.
