中 華 大 學 碩 士 論 文

中 華 大 學

碩 士 論 文

全金屬矽化閘極與氮氧化鋁鉿絕緣材料P型場 效電晶體元件之研製

系 所 別：電機系電機所電子電路組 學號姓名：M09401044 林哲緯

指導教授：謝焸家 博士

荊鳳德 博士

中 華 民 國 九 十 六 年 七 月

全金屬矽化閘極與氮氧化鋁鉿絕緣材料 P 型場效 電晶體元件之研製

研究生：林哲緯

指導教授：謝焸家博士、荊鳳德博士

中華大學 電機系研究所 電子電路組 摘 要

隨著互補式金氧半電晶體(CMOS)元件尺寸持續微縮，傳統的絕緣層-二氧化矽

(SiO²)將遭遇漏電流過大的物理限制。另外，傳統的多晶矽閘極也將遭遇諸多挑戰-

多晶矽空乏、硼穿透及高電阻係數。因此，新的絕緣層及閘極材料將是往後幾年超大 型積體電路(VLSI)發展極需解決的問題。近年來，高介電係數介電層與金屬閘極的技 術發展，已成為半導體產業最重要的研究之一。在本論文中，吾人將探討數種高介電

係數介電層與金屬閘極的研究與應用。

本 論 文 旨 在 以 矽 化 銥(IrxSi)作 為 全 金 屬 矽 化 閘 極 材 料，搭 配 的 閘 極 介 電 層 為 氮氧化鋁鉿(HfAlON)， 製 作 出 等 效 氧 化 厚 度 (EOT)值 為 1.7 nm 的 P 型 場 效 電 晶 體。在 經 過 950 ^oC 的快速熱退火後，全 金 屬 矽 化 銥 (IrxSi)閘 極 結 合 閘 極 介 電 層 為 氮氧化鋁鉿(HfAlON)的 P 型 場 效 電 晶 體 有 著 高 功 函 數 值 4.9eV， 而 此 元 件 最 高 峰 值 電 洞 遷 移 率 為 80 cm²/V-s， 並且有著完全相容於現今超大型積體 電路(VLSI)製程產線額外的優點。此元件對高溫的穩定度也有著優秀的表現， 由 實 驗 結 果 顯 示 ， 以 矽 化 銥(IrxSi)為 金 屬 閘 極 搭 配 氮氧化鋁鉿(HfAlON)閘 極 介 電

層 的 結 構 ， 適 用 於 P 型 金 氧 半 場 效 電 晶 體 ， 對 於 CMOS 電 路 元 件 的 應 用 更 具 潛 力◦

The Fabrication and Characterization of Ir

_x

Si FUSI Metal Gate with HfAlON Insulator P-MOS

Field-Effect Transistors

Student：Je-Wei Lin

Advisor：Dr. Ing-Jar Hsieh and Dr. Albert Chin

Department of Electrical Engineering

Chung Hua University

Abstract

To continue down-scaling CMOS technology, traditional insulator layer - SiO2 will face the physical limitation - large gate leakage current. In addition, traditional poly-Si gate encounters several inherent limitations, such as poly-Si depletion, boron penetration, and high resistivity. Therefore, new insulator and gate material technologies will become urgent for very large scale integration (VLSI) technology in the future years. Recently, metal-gate/high-κ process technologies become one of the most important researches in the semiconductor industry. In this dissertation, we will investigate the application of several high-κ dielectric and metal gate process technologies.

We have fabricated the fully silicided IrxSi gated p-MOSFETs on HfAlON gate dielectric with 1.7 nm EOT. After 950^oC RTA, the fully IrxSi/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm²/V-s and advantage of process compatible to current VLSI fabrication line.It will useful for CMOS circuit.

Acknowledgement

First of all, I would like to thank my advisor Prof. I.J.Hsieh and Prof. Albert Chin for their fruitful discussions and illuminative suggestions during the period of my working toward master degree. Their inspiration benefits me a lot on the creative ideas, effective schedule control and the integrity to the processing tasks. I am also grateful to ED633 group members – Dr. B. F. Hung, Dr. H. L. Kao, Dr. C. H. Lai, C. H. Wu, S. C. Chen and Terry Wang, for their enthusiastic assistance and cooperation.

Moreover, I am appreciative of the financial and equipment supports form National Science Council, National Nano Device Lab (NDL), and Semiconductor Center of NCTU.

I am also grateful to those who ever assisted this work.

Finally, I greatly appreciate my parents and family. Without them, I can’t finish this dissertation.

目錄

Abstract (in Chinese) i

Abstract (in English) iii

Acknowledgement iv

Contents v

Figure Captions vii

Table Captions i

x

CHAPTER 1 Introduction

1.1 General Background 1

1.2 Motivation 2

1.3 The Choice of High-κGate Dielectrics Materials 3

1.4 The Choice of Metal Gate Electrodes 4

1.5 Organization of This Thesis 6

CHAPTER 2 The Fabrication of P-MOS Field-Effect Transistors

2.1 Introdution 10

2.2 Experimental Procedure 12

2.3 Experimental Process Diagram 14

CHAPTER 3 Results and Discussion

3.1 C-V and J-V Characteristics measured and analysis 15 3.2 I-V Characteristics measured and analysis 16 3.3 Mobility Characteristics measured and analysis 16

CHAPTER 4 Conclusions and Suggestions for Future Work

4.1 Conclusions 26

4.2 Suggestions for Future Work 27

Reference

28

Figure Captions

CHAPTER 1

Fig. 1-1 The evolution of CMOS technology requirements (ITRS 2005).

Fig. 1-2 The band offset of popular high-κ materials.

Fig. 1-3 The values of work function for different metal materials.

CHAPTER 2

Fig. 2-1 Ideal the transistor structure.

Fig. 2-2 J-V characteristics of HfSiON/n-Si with IrxSi, Ir and Al gates capacitors.

Fig. 2-3 Experimental Process Diagram

CHAPTER 3

Fig. 3-1 (a)C-V characteristics of IrxSi/HfAlON, Ir/HfAlON, Al/HfAlON,

TiN/Ti0.5Ir0.5N/HfO2, and IrxSi/HfO2 capacitors measured under accumulation.

The device area is 100μm×100μm.

Fig. 3-2 (b) Jg-Vg characteristics of IrxSi/HfAlON, Ir/HfAlON, Al/HfAlON,

TiN/Ti0.5Ir0.5N/HfO2, and IrxSi/HfO2 capacitors measured under accumulation.

The device area is 100μm×100μm.

Fig. 3-3 The I_d-V_d characteristics of IrxSi/HfAlON p-MOSFET. The gate length is 10μm.

Fig. 3-4 The I_d-V_g characteristics of IrxSi/HfAlON p-MOSFETs. The gate length is 10μm.

Fig. 3-5 The extracted hole mobility from I_d-V_d characteristics of IrxSi/HfAlON p-MOSFET.

Fig. 3-6 XRD profile of IrxSi on HfSiON at different RTA temperature with x=3 determined. Insert figures are the top view pictures for Ir3Si and Ir at 1000oC RTA.

Fig. 3-7 SIMS profile of Ir3Si gates on HfAlON at different RTA temperature. The Ir3Si accumulated toward HfSiON interface is found to un-pin the Fermi-level.

Table Captions

Table 1. Device integrity comparison of various metal-gate/high-κ p-MOSFETs

Chapter 1

Introduction

1.1 General Background

The enormous growth of microelectronics over the past four decades and, as a result, the significant progress of information technology in general are based, to a large extent, on a simple gift of nature, the SiO2/Si system. This is especially true because ultrathin gate dielectrics in MOSFETs remain the key element in conventional silicon-based microelectronic devices. Since the very beginning of the microelectronics era, the SiO2 gate oxide in the first transistors was a few hundred nanometers, the functionality and performance of state-of-the-art devices currently rely on gate oxide that are just a few atomic layers (~1-2 nm) thick. Until very recently, the evolutionary scaling of the gate dielectric and ULSI devices in general has been accomplished by shrinking physical dimensions. As the physical thickness of SiO2-based gate oxides approaches ~2 nm, a number of fundamental problems arise.

In this ultrathin regime, some key dielectric parameters degrade: gate leakage current, oxide breakdown, boron penetration from the polysilicon gate electrode, and channel mobility [1,3]. Each of the parameters is vital for device operation. In other words, the conventional device-scaling scenario involving scaling down SiO2-based dielectrics below 1 nm becomes impractical.

The solution is to replace conventional SiO2 gate oxides with a material having higher permittivity. High-κ insulators can be grown physically thicker for the same equivalent electrical oxide thickness (EOT), thus offering significant gate leakage reduction, as demonstrated by several research groups. After almost a decade of intense research, the family of hafnium-oxide-based materials, such as HfO2, HfSixOy, HfOxNy, and HfSixOyNz, emerges as a leading candidate to replace SiO2 gate dielectrics in advanced CMOS applications . It has also become evident in the last few years that only replacing the gate insulator, with no concurrent change of electrode material, may not be sufficient for device scaling.

1.2 Motivation

The purpose of CMOS scaling is to enhance the performance of circuit and increase the packing density in a chip. Driving current of a MOSFET Ids can be well modeled by the following equation [2],

Ids = 1/2Coxμn(W/L)(VGS-Vt)(VDS) [eq-1]

Where μn is the effective mobility, Cox is the gate capacitance, W is the channel width, L is channel length. Obviously, drive current is inversely proportional to the channel length L. Therefore, the shrinkage of channel length is the most effective way to promote the driving current of a transistor. Another way to improve the Ids is increasing the Cox, i.e. scaling down oxide thickness. [2]

Cox = ^A

ox 0 ox

t k ε

^[eq-2]

However, thinning gate dielectrics inevitably accompany with larger direct tunneling current. The more recent high-k approach is to increase the physical thickness to reduce the direct tunneling current, yet at the same time obtain higher values of gate capacitance by using a dielectric material with a higher dielectric constant (high-κ) relative to SiO2,[2]

k high

k high ox

ox

t k t

k

−

=

− [eq-3]

Therefore, we still have enough capacitance value to obtain excellent gate control ability, lower leakage current and sufficiently large drive current.

1.3 The Choice of High- κ Gate Dielectrics Materials

The gate leakage current through the gate oxide increases significantly because direct tunneling is the primary conduction mechanism in down-scaling CMOS technologies. To reduce the leakage current related higher power consumption in highly integrated circuit and overcome the physical thickness limitation of silicon dioxide, the conventional SiO2 will be replaced with high dielectric constant (high-κ) materials as the gate dielectrics beyond the 65 nm technology mode [1]-[6]. Therefore, the engineering of high-κ gate dielectrics have attracted great attention and played an important role in VLSI technology. Although high-κ materials often exhibit smaller bandgap and higher defect density than conventional silicon dioxide, using the high-κ gate dielectric can increase efficiently the physical thickness in the same effective

oxide thickness (EOT) that shows lower leakage characteristics than silicon dioxide by several orders without the reduction of capacitance density [2]-[5]. According to the ITRS (International Technology Roadmap for Semiconductor) [7], the suitable gate dielectrics must have κ value more than 8 for 50-70 nm technology nodes and that must be more than 15 when the technology dimension less than 50 nm. Fig. 1-1 shows the evolution of CMOS technology requirements.

Research on finding an appropriate substitute to the superior SiO2 has been going on for almost a decade. Oxy-nitrides (SiOxNy) have been introduced to extend the use of SiO2 in production but eventually it has to be replaced by a high-κ material, such as Ta2O5,TiO2, HfO2, ZrO2, Al2O3, La2O3 or mixtures of them or metal-oxide-silicates of the mentioned compounds. However, most metal oxides will have the characteristics of crystallization at elevated temperature which cause devices generate non-uniform leakage distribution and give large statistical variation for nano-meter devices across the chip. Therefore, replacement gate strategies have been proposed to prevent crystallization and deleterious effects of mass and electrical transport along grain boundaries. Fig. 1-2 shows the summaries of the κ value and band offset for popular high-κ dielectric candidates.

1.4 The Choice of Metal Gate Electrodes

The gate electrode in CMOS devices is conventionally made of highly doped polycrystalline silicon (poly-Si). However, as the CMOS technology down-scaling, poly-Si gate will encounter several inherent limitations. One of them is depletion of the poly-Si electrode when the gate stack is biased in inversion [8]-[20]. The depleted

region is added to the dielectric thickness, which results the increase of EOT and degradation of the transconductance. Increased resistance of the gate electrode fingers is another issue due to the scaling geometry. Besides, diffusion of boron penetrates from the poly-Si gate will also degrade the performance of the transistors.

To overcome these problems, using metal gate electrodes will be a practical way to eliminate poly gate depletion and boron penetration [8]-[15]. In addition, metal gates also show the potential of reduced sheet resistance. However, metal-gate/high-κ CMOSFETs show undesired high threshold voltages (Vt), which is opposite to the VLSI scaling trend. This phenomenon is known as “Fermi-level pinning”, although the background physics may be attributed to interface dipole and/or charged defects [8]. Moreover, thermal stability of the effective metal electrode and metal diffusion are also important considerations.

The work functions (Φm) of metal shown in Fig. 1-3 play an important role for metal-gate/high-κ CMOSFETs. The preferred work function of the metals are ~5.2 eV for p-MOSFETs and ~4.1 eV for n-MOSFETs. Recently, lots of metal or metal-nitride materials have been widely researched and successfully intergraded in advanced CMOSFETs, such as TiN, TaN, Pt, Mo and Ir [8]-[20]. However, it has been found that thermal annealing of the metal gates at temperatures above 900^oC results in mid-gap values for almost all metal gate candidates. Therefore, the Fermi-level pinning effect needs to be avoided by selecting suitable metal gate and high-κ materials for advanced CMOS technologies.

1.5 Organization of This Thesis

The investigation includes four chapters. In chapter 1 , we make an introduction to describe the characterization of alternative metal gates and high-κ dielectric materials for the sub-45 nm technology node. In this chapter, the history of high-κ dielectrics and metal gate electrode evolution and the key materials have been reviewed. In chapter 2 , we will introduce the IrxSi gate on HfAlON for p-MOS, respectively. In chapter 3 , we will discuss the result of the IrxSi gate on HfAlON for p-MOS and explain the experimental results. Finally, in chapter 4 , we will make a conclusion and suggestion in the whole thesis.

2.7 7.4

7.4 Extended Planar Bulk (Å)

6.5 11

11 Extended Planar Bulk (Å)

195 185

DG MOSFET (mV)

167 167

UTB FD-SOI (mV)

151 165

168 Extended Planar Bulk (mV)

Saturation Threshold Voltage Requirement

4 4

DG MOSFET(Å)

4 4

UTB FD-SOI(Å)

Gate Poly Depletion and Inversion-Layer Thickness Requirements 5 6

DG MOSFET(Å)

5 7

UTB FD-SOI(Å)

Equivalent Oxide Thickness (EOT) Requirement

22 32

45 68

MPU/ASIC Metal ½ Pitch 78 (nm) (contacted)

2016 2013

2010 2007

2006 Year of Production

2.7 7.4

7.4 Extended Planar Bulk (Å)

6.5 11

11 Extended Planar Bulk (Å)

195 185

DG MOSFET (mV)

167 167

UTB FD-SOI (mV)

151 165

168 Extended Planar Bulk (mV)

Saturation Threshold Voltage Requirement

4 4

DG MOSFET(Å)

4 4

UTB FD-SOI(Å)

Gate Poly Depletion and Inversion-Layer Thickness Requirements 5 6

DG MOSFET(Å)

5 7

UTB FD-SOI(Å)

Equivalent Oxide Thickness (EOT) Requirement

22 32

45 68

MPU/ASIC Metal ½ Pitch 78 (nm) (contacted)

2016 2013

2010 2007

2006 Year of Production

Fig. 1-1 The evolution of CMOS technology requirements (ITRS 2006).

Fig. 1-2 The band offset of popular high-κ materials.

Fig. 1-3 The values of work function for different metal materials.

Chapter 2

The Fabrication of P-MOS Field-Effect Transistors

2.1 Introduction

Metal-gate/high-κ technology is required for future CMOS devices to reduce the gate leakage current and eliminate poly gate depletion. However, one of the difficult challenges for metal-gate/high-κ CMOS is the large threshold voltage (Vt) due to Fermi-level pinning. This is especially difficult for p-MOSFET [8], [10], since only Ni (5.15 eV), Ir (5.27 eV) and Pt (5.65 eV) in the Periodic Table [21] have work function close to the desired 5.2 eV used in conventional p⁺ poly-Si gated p-MOS.

Among them, the Ni-rich silicide (Ni3Si) [29] or germanide [25] has reasonable high work function, but it is still needed to develop the Ir or Pt gated high-κ p-MOS due to the lowered effective work function (φm,eff) by Fermi-level pinning. Unfortunately, large metal diffusion through high-κ dielectric was found to cause the CMOS devices failure [25], [30]-[31]. To overcome this problem, in this paper we have used the robust HfAlON to reduce the metal diffusion through gate dielectric by adding high diffusion barrier Al2O3 and oxynitride [30]-[33] into HfO2. Although the HfAlON has improved metal diffusion property, the Ir gated HfAlON p-MOS still failed at temperature higher than 900^oC. To further improve the thermal stability, we have developed the Ir/Si gated HfAlON p-MOSFET. After 950^oC RTA, the IrxSi/HfAlON p-MOS shows good device integrity of high φm,eff of 4.9 eV, small Vt of -0.1 V, and high hole mobility of 80 cm²/Vs. These results are compatible with or better than the best reported metal-gate/high-κ p-MOSFETs [27]. Fig. 2.1 shows ideal the structure.

Fig. 2.1 Ideal the transistor structure.

Source Drain

Gate

High-k dielectric

2.2 Experimental Procedure

Si wafer RCA Cleaning

Standard Clean steps：

DI water rinse, 5 min.

H2SO4 : H2O2 = 3:1, (10 min, 75~85℃) ---remove native oxide

DI water rinse, 5 min.

HF : H2O = 1:100 ---remove chemical oxide

DI water rinse, 5 min.

NH4OH : H2O2 : H2O = 1:4:20 (SC1), ( 10 min,75~85℃) ---remove particle

DI water rinse, 5 min.

HCl : H2O2: H2O = 1:1:6 (SC2), (10min, 75~85℃) ---remove IA Ion

DI water rinse, 5 min.

HF : H2O = 1:100 --- remove chemical oxide

DI water rinse.

Spinner

HfAlO was deposited by PVD

N-type Si wafer with resistivity 1~10 Ω-cm were used in this study. After standard RCA clean, the HfAlO was deposited by PVD followed by post deposition anneal.

NH

3

plasma surface nitridation on HfAlO

The HfAlON was formed by applying NH3 plasma surface nitridation on HfAlO and 800^oC post-deposition anneal (PDA).

Gate patterning

The gate was defined through lithography.

α-Si and Ir was deposited by PVD

Then ~25 nm amorphous Si and 60 nm Ir was deposited by PVD [14]-[15], patterned and RTA annealed at 600-950 ^oC for 30 sec to form the MOS capacitor.

Boron source-drain ion implantation at 25 KeV

The gate first p-MOSFET was fabricated by forming HfAlON, metal-gate deposition and patterning, Boron source-drain ion implantation at 25 KeV, and activated at 950 ^oC RTA for 30 sec.

Ir

x

Si was formed at the same time as ion implantation RTA

Note that this process is different from conventional salicide process, where the IrxSi was formed at the same time as ion implantation RTA. This can reduce the reaction of amorphous Si with high-κ dielectric to cause Fermi-level pinning, owing to the fast silicidation reaching to the Si/HfAlON interface in thin amorphous Si.

Al, Ir gated devices on HfAlON or HfO

2

were also fabricated

For comparison, Al, Ir gated devices on HfAlON or HfO2 were also fabricated.

The fabricated p-MOS devices were further characterized by C-V and I-V measurements.

2.3 Experimental Process Diagram (figure 2.2)

n-Si RCA Cleaning

n-Si HfAlO

Deposited HfAlO

n-Si HfAlO

PDA

800℃ PDA

n-Si HfAlO NH3 Plasma

NH₃ Plasma

n-Si HfAlON

Formed HfAlON

Gate patterning

P/R

P/R P/R

n-Si HfAlON

α-Si

P/R α-Si P/R α-Si α-Si

α-Si α-Si

n-Si HfAlON

Deposited Ir

Deposited α-Si

Ir

P/R α-Si P/R α-Si α-Si

α-Si α-Si

n-Si HfAlON

Ir Ir

Ir Ir

Ir

Remove P/R

P/R

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

Ion Implant

Ion Implant

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

S D

950℃ RTA

RTA

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

S D

IrXSi gate formed

n-Si HfAlON

S D

Ir_XSi Device formed n-Si

RCA Cleaning

n-Si RCA Cleaning

n-Si HfAlO

n-Si HfAlO

Deposited HfAlO

n-Si HfAlO

PDA

n-Si HfAlO

n-Si HfAlO

PDA

800℃ PDA

n-Si HfAlO NH3 Plasma

n-Si HfAlO

n-Si HfAlO NH3 Plasma

NH₃ Plasma

n-Si HfAlON

Formed HfAlON

Gate patterning

P/R

P/R P/R

n-Si HfAlON

P/R

P/R P/R

n-Si HfAlON

α-Si

P/R α-Si P/R α-Si α-Si

α-Si α-Si

n-Si HfAlON

α-Si

P/R α-Si P/R α-Si α-Si

α-Si α-Si

n-Si HfAlON

Deposited Ir

Deposited α-Si

Ir

P/R α-Si P/R α-Si α-Si

α-Si α-Si

n-Si HfAlON

Ir Ir

Ir Ir

Ir

Ir

P/R α-Si P/R α-Si α-Si

α-Si α-Si

n-Si HfAlON

Ir Ir

Ir Ir

Ir

Remove P/R

P/R

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

P/R

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

Ion Implant

Ion Implant

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

S D

Ion Implant

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

S D

950℃ RTA

RTA

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

S D

RTA

α-Si α-Si

α-Si

n-Si HfAlON

Ir Ir

Ir

S D

IrXSi gate formed

n-Si HfAlON

S D

Ir_XSi Device formed

n-Si HfAlON

S D

Ir_XSi

n-Si HfAlON

S D

Ir_XSi Device formed

Chapter 3

Results and Discussion

3.1 C-V and J-V Characteristics measured and analysis

Figs. 3.1(a) and 3.2(b) shows the C-V and J-V characteristics of different RTA temperature annealed IrxSi/HfAlON, Ir/HfAlON, TiN/Ti0.5Ir0.5N/HfO2, IrxSi/HfO2, and control Al/HfAlON capacitors. We have chosen the Al gated capacitor as a reference since the pure metal at low RTA temperature has little Fermi-level pinning on high-κ dielectric [5]. An equivalent oxide thickness (EOT) of ~1.7 nm is measured, while the shift of C-V curves with different gate electrodes are attributed to different work function. This is because the 800^oC PDA has already annealed out some defects and the Ir of IrxSi reaction toward HfAlON interface was also confirmed by X-Ray Diffraction (XRD) measurement. However, the IrxSi/HfO2 device fails even after 800^oC RTA due to the reaction of amorphous-Si with HfO2. The TiN/Ti0.5Ir0.5N/HfO2

also fails at temperature higher than 800^oC that may be due to Ir diffusion into HfO2. Thus, the using metal-nitride (IrN) is run out of solution to achieve both high work-function and good thermal stability. The thermal stability is largely improved to 900^oC by using HfAlON instead of HfO2 even for Ir-gated capacitor, but still failed at higher temperature. The adding additional ~25 nm amorphous Si to form the IrxSi on HfAlON can further improve the thermal stability to 950^oC with a reasonable leakage current. The increasing flat band voltage (Vfb) with increasing RTA temperature of

IrxSi/HfAlON capacitors may be due to more Ir diffusion toward HfAlON surface to increase the work function. However, the better thermal stability of IrxSi/HfAlON than Ir/HfAlON is traded by the lower work function. From C-V shift to Al control gate, the extracted φm,eff of IrxSi/HfAlON and Ir/HfAlON are 4.9 and 5.3 eV, respectively. Therefore, good thermal stability of 950^oC RTA, reasonable high φm,eff of 4.9 eV, and low gate dielectric leakage current can be simultaneously achieved in IrxSi/HfAlON MOS capacitors. It is important to note that although the Vfb tunneling can also be changed by dopant diffusion in FUSI/SiON, this method becomes less effective in high-κ metal-oxide due to the stronger interface reaction.

3.2 I-V Characteristics measured and analysis

Fig. 3.3 shows the transistor Id-Vd characteristics as a function of Vg-Vt for 950^oC RTA annealed IrxSi/HfAlON p-MOSFETs. The well-behaved Id-Vd curves of IrxSi/HfAlON shows little device performance degradation using IrxSi gate.

Fig. 3.4 shows the Id-Vg characteristics of IrxSi gated p-MOSFETs with HfAlON film as the gate dielectric. A Vth is as low as -0.1 V is obtained from the linear Id-Vg plot, which is consistent with the large φm,eff of 4.9 eV from C-V curves.

3.3 Mobility Characteristics measured and analysis

Figs. 3.5 shows the extracted hole motility versus gate electric field from measured Id-Vg curves of p-MOSFETs. High hole mobility of 80 and 57 cm²/V-s is obtained at peak value and 1 MV/cm effective field for IrxSi/HfAlON p-MOSFETs,

respectively. This result also suggests low Ir diffusion through HfAlON even though excess Ir must be used to avoid un-reacted amorphous Si to cause gate depletion or Fermi lever pinning. Table 1 summarizes the comparison among various metal-gate/high-κ p-MOS. The merits of IrxSi/HfAlON p-MOS are very high φm-eff of 4.9 eV, low Vt of -0.29 V, and high mobility of 80 cm²/Vs. This indicates the successful integration of IrxSi on HfAlONp-MOSFETs with advantage of process compatible to current VLSI line.

Fig. 3.6 XRD profile of IrxSi on HfSiON at different RTA temperature with x=3 determined. Insert figures are the top view pictures for Ir3Si and Ir at 1000oC RTA.

Fig. 3.7 SIMS profile of Ir3Si gates on HfAlON at different RTA temperature.

The Ir3Si accumulated toward HfSiON interface is found to un-pin the Fermi-level.

-2 -1 0 1 2 0.0

0.5 1.0 1.5 2.0

2.5

Al/HfAlON@ RT

Ir/HfAlON @ 900^oC Ir/HfAlON @ 600^oC Ir_xSi/HfAlON @ 850^oC TiN/Ti_0.5Ir_0.5N/HfO₂ @ 800^oC Ir_xSi/HfAlON @ 900^oC

Ir_xSi/HfAlON @ 950^oC

Voltage (V) Capacitance ( μ F/cm

2

)

Fig. 3.1 C-V characteristics of IrxSi/HfAlON, Ir/HfAlON, Al/HfAlON, TiN/Ti0.5Ir0.5N/HfO2, and IrxSi/HfO2 capacitors measured under accumulation.

The device area is 100μm×100μm.

0.0 0.5 1.0 1.5 2.0 10

^-11

10

^-9

10

^-7

10

^-5

10

^-3

10

^-1

10

¹

Al/HfAlON @ RT Ir/HfAlON @ 900^oC Ir/HfAlON @ 950^oC

TiN/Ti

0.5Ir

0.5N/HfO

2 @ 800^oC Ir

xSi/HfAlON @ 850^oC Ir_xSi/HfO₂ @ 800^oC Ir_xSi/HfAlON @ 900^oC Ir

xSi/HfAlON @ 950^oC

Voltage (V) Gate Current ( A/cm

2

)

Fig. 3.2 J_g-V_g characteristics of IrxSi/HfAlON, Ir/HfAlON, Al/HfAlON,

TiN/Ti0.5Ir0.5N/HfO2, and IrxSi/HfO2capacitors measured under accumulation.

The device area is 100μm×100μm.

-3 -2 -1 0 0.0

0.5 1.0 1.5 2.0 2.5

Ir

x

Si/HfAlON p-MOSFET Gate Length = 10

μ

m

|V

_g

- V

_T

| = 0.5 V |V

g

- V

T

| = 1 V |V

_g

- V

_T

| = 1.5 V |V

_g

- V

_T

| = 2 V

I

d

( m A )

V

_d

(V)

Fig. 3.3 The I_d-V_d characteristics of IrxSi/HfAlON p-MOSFET. The gate length is 10μm.

-3 -2 -1 0 1 10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

Ir

x

Si/HfAlON p-MOSFET

Gate Length = 10

μ

m I

d

(A)

V

g

(V) V

ds

= - 0.1 V

Fig. 3.4. The I_d-V_g characteristics of IrxSi/HfAlON p-MOSFETs. The gate length is 10μm.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 40

80 120 160

200 Universal

Ir

x

Si/HfAlON p-MOSFET

μ

eff

( cm

2

/V -sec )

Effective field (MV/cm)

Fig. 3.5 The extracted hole mobility from I_d-V_d characteristics of IrxSi/HfAlON p-MOSFET.

20 30 40 50 60 unreacted Ir

In te n s it y ( cps )

2 θ (Degree)

Ir

_x

Si(20/5nm) @ Room Temp.

Ir

_x

Si(20/5nm) @ 900oC RTA Ir

_x

Si(20/5nm) @ 950oC RTA Ir

_x

Si(20/5nm) @ 1000oC RTA

Ir

3

Si

Fig. 3.6. XRD profile of IrxSi on HfSiON at different RTA temperature with x=3

determined. Insert figures are the top view pictures for Ir3Si and Ir at 1000oC RTA.

0 50 100 150 200 10

³

10

⁴

10

⁵

10

⁶

accumulation toward HfSiON

Si (RTA1000^oC)

Si (RTA950^oC) Si (RTA900^oC) Ir (RTA1000^oC) Ir (RTA950^oC) Ir (RTA900^oC)

Sputter Time (sec)

In ten s it y (c ou nts )

Ir

3

Si

Ir

Ir accumulation

HfSiON

Fig. 3.7 SIMS profile of Ir3Si gates on HfAlON at different RTA temperature. The

Ir3Si accumulated toward HfSiON interface is found to un-pin the Fermi-level.

High-κ Gate φ_{m-eff (eV)}^€ Vt Thermal budget Mobility(cm²/Vs)

HfAlON Ir_XSi 4.9 -0.29 950 ^oC 80

HfOXN PtSiX 4.86 -0.39 Gate last 130

HfO2 MONX 4.87 -0.5 1000 ^oC ~75

HfSiON NiSiGe - -0.5 Gate last ~70

HfSiON Ni3Si 4.85 -0.3 Gate last -

Table 1. Device integrity comparison of various metal-gate/high-κ p-MOSFETs

Chapter 4

Conclusions and Suggestions for Future Work

4.1 Conclusions

To compensate Fermi-level pinning effect, low and high work function metal electrodes are required to reduce the pinning effect for n- and p-MOSFETs, respectively. For p-MOSFETs, high work function metal electrodes larger than the 5.2 eV of p⁺ poly-Si are needed. However, only Ir (5.27 eV) and Pt (5.65 eV) in the Periodic Table [21] can meet this requirement, which make the metal-gate/high-κ p-MOSFETs especially challenging [8]-[10]. Ir is more preferable than Pt due to a simpler etching process by reactive ion etching (RIE) [22]-[23].

Unfortunately, large metal diffusion through high-κ dielectrics was found in pure Ir gates after 1000^oC RTA which caused p-MOS device failures [24]-[25]. Another possibility is using low temperature full silicidation (FUSI) gates [9],[24]-[27].

However, the p-MOS devices incorporating high work function PtxSi or IrxSi still failed to integrate into the CMOS SALICIDE process due to the lack of required selective wet etching of Pt or Ir during SALICIDE. In this thesis, we have fabricated the fully silicided IrxSi gated p-MOSFETs on HfAlON gate dielectric with 1.7 nm EOT. After 950^oC RTA, the fully IrxSi/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm²/V-s and advantage of process compatible to current VLSI fabrication line.

4.2 Suggestions for Future Work

Although we have fabricated the fully silicided IrxSi gated p-MOSFETs on HfAlON gate dielectric with 1.7 nm EOT. After 950^oC RTA, the fully IrxSi/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm²/V-s, several works are worthy to do in the future and are recommended here：

1. We need to find the way how to fabricate the device of n-type MOSFET.

2. Because the fully IrxSi/HfAlON device doesn’t stability in 1000 ^oC, we need to search new electrode of high-κ metal gate and high-κ insulation to improve the thermal stability.

3. In future, we will apply this work in my investigation to the present circuit design in order to check the influences of short channel effects in the advanced semiconductor technology.

4. We should also measure the reliability of the fully IrxSi/HfAlON device.

Reference

[1] M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C.

Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorporated ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” in IEDM Tech. Dig., pp. 20.3.1-20.3.4, 2001.

[2] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A.

Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. -A.

Ragnarsson and Rons, “Ultrathin high-κ gate stacks for advanced CMOS devices,” in IEDM Tech. Dig., pp. 20.1.1-20.1.4, 2001.

[3] W. Zhu, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson and T.

Furukawa, “HfO2 and HfAlO for CMOS: thermal stability and current transport,” in IEDM Tech. Dig., pp. 20.4.1-20.4.4, 2001.

[4] L. Kang, K. Onishi, Y. Jeon, Byoung Hun Lee, C. Kang, Wen-Jie Qi, R. Nieh, S.

Gopalan, R Choi and J. C. Lee, “ MOSFET devices with polysilicon on single-layer HfO2 high-κ dielectrics,” in IEDM Tech. Dig., pp. 35-38, 2000.

[5] Rino Choi, Chang Seok Kang, Byoung Hun Lee, K. Onishi, R. Nieh, S.

Gopalan, E. Dharmarajan and J. C. Lee, “High-quality ultra-thin HfO2 gate dielectric MOSFETs with TaN electrode and nitridation surface preparation,” in IEDM Tech. Dig., pp. 15-16, 2001.

[6] Z. J. Luo, T. P. Ma, E. Cartier, M. Copel, T. Tamagawa and B. Halpern,

“Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate applications,” in Symp. on VLSI Technology, pp. 135-136, 2001.

[7] International Technology Roadmap for Semiconductor, 2004.

[8] J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer,

Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White Jr, and P. J. Tobin, “Challenges for the integration of metal gate electrodes,” in IEDM Tech. Dig., pp. 287-290, 2004.

[9] W. P. Maszara, Z. Krivokapic, P. King, J. S. GooIlgweon, and M. R. Lin,

“Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., pp.367–370, 2002.

[10] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., pp. 821-824, 2004.

[11] H. -J. Cho, C. S. Kang, K. Onishi, S. Gopalan, R. Nieh, R. Choi, E.

Dharmarajan and J.C. Lee, “ Novel nitrogen profile engineering for improved TaN/HfO2 Si MOSFET performance,” in IEDM Tech. Dig., pp. 30.2.1-30.2.4, 2001.

[12] Y. T. Hou, M. F. Li, T. Low, and D. L. Kwong, “ Impact of metal gate work function on gate leakage of MOSFETs,” in DRC Symp., pp. 154-155, 2003.

[13] Dae-Gyu Park, Kwan-Yong Lim, Heung-Jae Cho, Tae-Ho Cha, Joong-Jung Kim, Jung-Kyu Ko, Ins-Seok Yeo and Jin Won Park, “ Novel damage-free direct metal gate process using atomic layer deposition,” in Symp. on VLSI Technology, pp. 65-66, 2001.

[14] C. Cabral Jr. , J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A.

Steegen, P. Kozlowski, R. Carruthers, and R. Jammy,” Dual workfunction fully silicided metal gates,” in Symp. on VLSI Technology, pp. 184-185, 2004.

[15] S. B. Samavedam, L. B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J.

Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. H. Tseng, P. J.

Tobin, D. C. Gilmer, C. Hobbs, W. J. Taylor, J. M. Grant, R. I. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M.

Sadd, B.-Y. Nguyen, and B. White,” Dual-metal gate CMOS with HfO2 gate dielectric,” in IEDM Tech. Dig., pp. 433-436, 2002.

[16] D. S. Yu, A. Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C. Zhu, M.-F.

Li, S. P. McAlister, and D. L. Kwong, “3D GOI CMOSFETs with novel IrO2

(Hf) dual gates and high-κ dielectric on 1P6M-0.18 μm-CMOS,” in IEDM Tech.

Dig., pp. 181-184, 2004.

[17] D. S. Yu, A. Chin, C. C. Liao, C. F. Lee, C. F. Cheng, M. F. Li, Won Jong Yoo, and S. P. McAlister, “3D Metal-Gate/High-κ/GOI CMOSFETs on 1-Poly-6-Metal 0.18-μm Si Devices,” IEEE Electron Device Lett. 26, pp.

118-120, Feb. 2005.

[18] X. P. Wang, C. Shen, Ming-Fu Li, H.Y. Yu, Yiyang Sun, Y. P. Feng, Andy Lim, Hwang Wan Sik, Albert Chin, Y. C. Yeo, Patrick Lo, and D.L. Kwong,” Dual Metal Gates with Band-Edge Work Functions on Novel HfLaO High-κ Gate Dielectric,” in Symp. on VLSI Technology, pp. 12-13, 2006.

[19] J. H. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra,”

Tunable work function dual metal gate technology for bulk and nonbulk CMOS,” in IEDM Tech. Dig., pp. 359-362, 2002.

[20] H. Y. Yu, M. F. Li, and D.L. Kwong,” Thermally Robust HfN Metal as a Promising Gate Electrode for Advanced MOS Device Application,” IEEE Transactions on Electron Devices, vol. 51, Apr., 2004.

[21] H. B. Michaelson, “The work function of the elements and its periodicity,” J.

Appl. Phys., vol. 48, pp. 4729-4733, Nov. 1977.

[22] C. H. Lai, A. Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng, S. P. McAlister, C. C.

Chi and P. Wu, “Novel SiO2/AlN/HfAlO/IrO2 memory with fast erase, large ΔVth and good retention,” in Symp. VLSI Tech. Dig., 2005, pp. 210-211.

[23] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung, C.

C. Liao, “Very high k and high density TiTaO MIM capacitors for analog and RF applications,” in Symp. VLSI Tech. Dig., 2005, pp. 62-63.

[24] D. S. Yu, A. Chin, C. H. Wu, M.-F. Li, C. Zhu, S. J. Wang, W. J. Yoo, B. F.

Hung and S. P. McAlister, “Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference,” in IEDM Tech. Dig., 2005, pp.

649-652.

[25] C. H. Huang, D. S. Yu, A. Chin, W. J. Chen, C. X. Zhu, M.-F. Li, B. J. Cho, and D. L. Kwong, “Fully silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-On-Insulator MOSFETs,” in IEDM Tech. Dig., 2003, pp.

319-322.

[26] B. Tavel, T. Skotnicki, G. Pares, N. Carrière, M. Rivoire, F. Leverd, C. Julien, J.

Torres, and R. Pantel, “Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (~2Ω/ ) without metal CMP nor etching,” in IEDM Tech.

Dig., 2001, pp. 815-828.

[27] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high-k gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.

[28] See http://public.itrs.net/ for most recent updates to the International Technology Roadmap for Semiconductors.

[29] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H.

Watanabe, T. Tatsumi, and Y. Mochizuki, “Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices,” in IEDM Tech. Dig., 2004, pp. 91–94.

[30] C. C. Liao, C. F. Cheng, D. S. Yu and A. Chin, “The copper contamination effect on Al2O3 gate dielectric on Si,” J. Electrochem. Soc., vol. 151, pp. G693-G696,

Oct. 2004.

[31] Y. H. Lin, F. M. Pan, Y. C. Liao, Y. C. Chen, I. J. Hsieh, and A. Chin, “The Cu contamination effect in oxynitride gate dielectrics,” J. Electrochem. Soc., vol.

148, G627-G629, Nov. 2001.

[32] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high-k Al2O3 gate dielectric with good mobility and low Dit,” in Symp. VLSI Tech. Dig., 1999, pp. 133-134.

[33] C. H. Huang, M. Y. Yang, A. Chin, W. J. Chen, C. X. Zhu, B. J. Cho, M.-F. Li, and D. L. Kwong, “Very low defects and high performance Ge-On-Insulator p-MOSFETs with Al2O3 gate dielectrics,” in Symp. VLSI Tech. Dig., 2003, pp.

119-120.

[34] E. P. Gusey, V. Narayana, M. M. Frank, “Advanced high-j dielectric stacks with polySi and metal gates: Recent progress and current challenges”, In IBM J. RES.

& DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006

[35] B. F. Hung, “The Investigation and Application of High-κ Dielectrics and Metal Gate Process Technologies”, 2006, Department of Electronics Engineering &

Institute of Electronics National Chiao Tung University

[36] S.C. Chen, “The Interface Investigation of High-K Material HfO2 on Si Substrate”, 2003, Department of Electronics Engineering & Institute of Electronics National Chiao Tung University

[37] Byoung Hun Lee, Laegu Kang, Renee Nieh, Wen-Jie Qi, and Jack C. Lee,

“Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing”, Applied Physics Letters -- April 3, 2000 -- Volume 76, Issue 14, pp. 1926-1928.

[38] L. Kang, B. H. Lee, W.-J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C.

Lee,” Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric”, IEEE Electron Device Lett. 21, 181 2000.

[39] H.Uchida, S.Inomata, and T.Ajioka, “Effects of interface traps and bulk traps in SiO2 on hot-carrier-induced degradation” , Conference on Microelectronic Test Structures, Vol 2 , NO. 1 , March 1989.

[40] Y.H.Kim. Onishi, C.S.Choi, Jack C.Lee etc.”Hard and Soft-Breakdown Characteristics of Ultra-Thin HfO2 under Dynamic and Constant Voltage Stress.”, IEDM 2002.