Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique

FED

Evolution of

Low-Voltage

CMOS

Digital VLSI Circuits Using

Bootstrap

Technique

James B. Kuo

Dept of Electrical Engineering, Rm 338 National Taiwan University

Taipei, Taiwan 106-17 Email: j.kuo@ieee.org Abstract-This paper reports the

evolution of the low-voltage CMOS digital VLSI circuits using bootstrap technique.

Combining bootstrap and DTMOS

techniques, low-voltage CMOS digital circuits using a power supply as low as 0.5V are feasible for low-power VLSI system applications.

I. INTRODUCTION

For next-generation CMOS VLSI circuits, low supply voltage is the trend [1] [2]. Since the threshold voltage of the CMOS devices cannot be scaled down accordingly with the supply voltage, designing a CMOS digital circuit using a low supply voltage for the next-generation CMOS VLSI is a challenge. In this paper, the evolution of the low-voltage CMOS digital VLSI circuits using bootstrap technique is described. In the following sections, the bootstrap technique is presented first, followed by bootstrapped dynamic and static circuits.

II. Bootstrap Technique

Fig. 1 shows the bootstrap technique used in a CMOS large-load driver circuit [1]. Capacitor Cbp and NMOS devices MN1b/MN2b are used for the bootstrapped pull-up operation and capacitor

Cbn

and PMOS devices Mplb/Mp2b are used for the bootstrapped pull-down operation. Fig. 2 shows the equivalent circuit of this bootstrapped CMOS large-load driver circuit during the pull-up transient [3]. Prior to the ramp-up period, Cbp has been charged to VDD. Due to the charge stored in Cbp, after the ramp,

Mp,

has been driven by a minus gate voltage, hence a faster pull-up-bootstrap technique. As described in the following sections, the bootstrap technique has been used in the dynamic and static circuits to enhance the speed performance.

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Fig. 1. Bootstrap technique used in a CMOS large-load driver circuit [3].

V1. ?7 _ _ -IfN 5 V M,. .1 *-~~~~~~~~4

Fig. 2. Equivalent circuit of the bootstrapped CMOS large-load driver circuit during the pull-up transient [3].

Ill. BOOTSTRAPPEDDYNAMIC LOGIC CIRCUITS Fig. 3 shows the bootstrapped dynamic logic (BDL) circuit, which is composed of the dynamic logic circuit and the bootstrapper circuit. During the precharge period (CK low), the bootstrap capacitor Cb is charged to VDD. During the logic evaluation period (CK high), if both inputs are high, owing to the charge in the bootstrap capacitor, Vb is bootsrapped to over VDD, hence the driving capability of the output is enhanced. V.t... ';"I . V_1 -0 .P_

1- type BDL

Fig. 3 CMOS bootstrapped dynamic logic (BDL) 2-input AND circuit [4].

V,,, 1= .5V

P- tvpe BDL + BiC'OS

Fig. 4. 1.5V BiCMOS dynamic logic (BDL) circuit with the bootstrap technique [4]. Using the bootstrapper circuit, the speed performance of a 1.5V BiCMOS boostrapped dynamic logic (BiCMOS BDL) as shown in Fig. 4 can be improved [4]. As shown in the figure, in this BiCMOS BDL circuit, it has a BiPMOS pull-down dynamic logic circuit and a p-type BDL circuit with a p-type bootstrapper circuit, which is complementary to the one as shown

in Fig. 3.

Fig. 5 shows a three-input NAND circuit using the 1.5V CMOS all-N-logic TSP BDL circuit [5]. As shown in the figure, it is composed of an nl block, which is identical to the n-type BDL as shown in Fig. 3, and an n2 block, which is derived from a p-type BDL circuit as shown in Fig. 4 to avoid using slower PMOS devices.

V2-=1 5V V5= SV

V,

A.XCl P -Ji C t1iK t

Bi C' .,*

Fig. 5. Three-input NAND circuit using the 1.5V CMOS all-N-logic TSP BDL circuit [5].

Fig.

6.1.5V CMOS

bootstrapped.

PTbae

carry circu'>'iha it 6

t]

<

Fi

t5>5.g5

i.

6 shw

',E

th '1I5.CMS

bottrpe

pastransis;|tor.

(P)bae

car look<5St-ahead

CA

circuit

6. As shown in the

figre

the

Fg6.15CMSbootstrapper

cici,wihfnTionsasedn

inverter with its

output

high

level boosted to

over

VDD,

iS used to boost the

input

signal

to the

gate

of the pass transistors used in

producing

the

propagate

signal.

With the

gate

overdrive

voltage,

the pass transistor can turn

on earlier and have a

larger

current

driving

capability.

Owing

to the critical

path

formed

by

the serial-connected pass

transistors,

which

are controlled

by

the

propagate

signals,

the

voltage

overshoot at the

output

of the

bootstrapper

circuit enhances the

speed

performance

of this PT-based Manchester carry chain circuit.

Therefore,

the bootstrapper circuit is

especially advantages

for low

supply

voltage

applications.

IV. BOOTSTRAPPED STATIC CIRCUITS

LVo4 1N1

Fig. 7. Sub-1V CMOS load driver circuit using the direct bootstrap technique [7]. In addition to dynamic circuits, bootstrap technique has been used in the static circuits to enhance the speed performance. In this section, the direct bootstrapped circuit, the 0.5V bootstrapped SOI CMOS load driver

I i.-{e 8M FED K

and the bootstrapped adiabatic

power systems are described. circuit for low- differential switchCMOS adiabaticlogic (DSL) are effective inlogic circuits using achieving goals in low power consumption [1].

PCI PC2 PC3 PC4

IN PC3 O UT4C7P4

PC3 PC4 PCI PC2

Fig. 8 0.5V SOI CMOS inverting driver circuit using DTMOS/bootstrap technique [9]. The bootstrap technique described in Fig. 1 is called indirect bootstrap technique since it is applied at the gate of the output devices in a driver circuit, which may not be effective in shortening the switching speed of the output. Fig. 7 shows a sub-1V CMOS load driver circuit using the direct bootstrap technique [7]. As shown in the figure, in this direct bootstrap technique, the bootstrap capacitor CB1/CB2 is connected to the output node via P2/N2, instead of via the gate of the output device as in other indirect bootstrap technique. Owing to the charge stored in the bootstrap capacitor

CB1/CB2 prior

to the

pull-up/pull-down

transient,

the output can be pulled up/down quickly.

Combining with DTMOS technique [8], the bootstrap technique has been used in the SOI CMOS load driver using a very low power supply voltage. Fig. 8 shows a 0.5V CMOS inverting driver using DTMOS/bootstrap technique [9]. As shown in the figure, this driver is composed of two bootstrap capacitors with the DTMOS technique for magnifying the input signals to overcome the shortage of the gate voltage over-drive problems for ultra low-voltage operation such as 0.5V, which is comparable to or smaller than the magnitude of the threshold voltage of the devices used. The bootstrap capacitor CB1/CB2 with the precharge device P3/N3 and the driver device N2/P2 with its body controlled by the DTMOS technique has been used to resolve the problem associated with the shortage of gate voltage over-drive.

Fig. 9 0.8V CMOS adiabatic differential switch logic (ADSL) circuit using the bootstrap technique

[10].

Fig. 9 shows a 0.8V CMOS adiabatic differential switch logic (ADSL) circuit using the bootstrap technique [10]. As shown in the figure, this ADSL circuit is derived from a DSL circuit with the cross-coupled bootstrap devices MN3/MN4 to enhance its switching performance. Owing to the capacitance coupling of the gate-drain capacitance of MN3/MN4, the voltage of the internal node BP1/BP2 could be bootstrapped. Thus the flow of charge stored at the output node is enhanced and hence the speed performance is raised.

REFERENCES

[1] J.Kuo, "LV CMOS VLSI Ckts," Wiley, NY 99. [2] J.Kuo,"LV SOI CMOS VLSI Dev/Ckts,"

Wiley, NY, 01.

[3] J.Lou & J.Kuo, "A 1.5V FS Bt CMOS Lg Cap-Ld Dr," IEEE JSSC,119-21, 97.

[4] J.H. Lou & J.B. Kuo, "1.5V CMOS and BiCMOS BDL," S.VLSI TSA, 279-82, 97. [5] J.Lou & J.Kuo,

"1.5V

CMOS All-N-Log TSP

Bt BDL for LV Op," IEEE TCAS, 628-31, 99. [6] J.Lou & J.Kuo, "A 1.5-V Bt PT-B Man Carry

Cfor CLA Add," IEEE TCAS, 1191-4, 98. [7] P.Chen & J.Kuo,"Sub-lV CMOS Dr Using

DB Tech," Elec.Lett. 265-6, 02.

[8] F.Assaderaghi et al, "DTMOS for Ultra-Low-Volt VLSI," IEEE TED, 414-422,1997. [9] J.Chen & J.Kuo, "ULV SOI CMOS Dr

Based on Bt Tech," Elec. Lett. 183-5, 03. [10] Y.Zhang,H.Chen & J.Kuo, "0.8V CMOS

Adiabatic Diff Sw Logic Using Bt Tech for LV LP VLSI," Elec. Lett., 1497-9, 02.

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