A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS

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740 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, MARCH 2009

A 1.2 V 114 mW Dual-Band Direct-Conversion

DVB-H Tuner in 0.13

m CMOS

Ming-Ching Kuo, Student Member, IEEE, Shiau-Wen Kao, Chih-Hung Chen, Tsung-Shuen Hung, Yi-Shing Shih,

Tzu-Yi Yang, and Chien-Nan Kuo, Member, IEEE

Abstract—A fully integrated direct-conversion tuner is imple-mented in 0.13 m CMOS technology. A broadband noise-can-celing balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degra-dation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L-bands, and occupies only 7.2 mm2die area.

Index Terms—Balun, CMOS RF, current-mode switching, di-rect-conversion, DVB-H, DVB-T, mobile TV, noise-canceling LNA, OFDM, passive mixer, receiver, tuner.

I. INTRODUCTION

M

OBILE TV systems are in great demand for multi-func-tion mobile entertainment platforms. Among the newly introduced mobile TV standards, DVB-H is currently consid-ered as the globally dominant one. To be successfully integrated into a crowded handheld device, a DVB-H solution must meet the requirements of a small form factor and low power consump-tion. Several direct-conversion tuners have been reported in an attempt to address these needs in recent years. Implemented in SiGe BiCMOS [1]–[3] or in 0.18 m CMOS [4], [5] technolo-gies, these tuners consume 200–300 mW in the continuous re-ceiving mode from the supply voltage around 2.7 V. In order to further reduce the power consumption and to provide a high level of integration, a mobile TV system-on-a-chip (SoC) is the optimal solution by integrating a radio tuner, a baseband demod-ulator, and even a decoder into a single die. Towards this evolu-tion, the first step is to develop a tuner in a finer deep-submicron or even nanometer CMOS technology [6].

Manuscript received May 15, 2008; revised November 14, 2008. Current ver-sion published February 25, 2009.

M.-C. Kuo is with the National Chiao-Tung University, Department of Electronic Engineering, Hsinchu, Taiwan. He is also with the Industrial Tech-nology Research Institute, SoC TechTech-nology Center, Hsinchu, Taiwan (e-mail: mckuo@itri.org.tw; mckuo.tw@gmail.com).

S.-W. Kao, C.-H. Chen, T.-S. Hung, Y.-S. Shih and T.-Y. Yang are with the Industrial Technology Research Institute, SoC Technology Center, Hsinchu, Taiwan.

C.-N. Kuo is with the National Chiao-Tung University, Department of Elec-tronic Engineering, Hsinchu, Taiwan (e-mail: cnkuo@mail.nctu.edu.tw).

Digital Object Identifier 10.1109/JSSC.2008.2012366

The trend of technology scaling in advanced CMOS technolo-gies benefits digital demodulators in both speed and power dis-sipation. The associated supply voltage reduction, which could be as low as 1.2 V, however, causes issues to RF tuner design. In practice, a low supply voltage constrains stacking of several devices, and limits applications of many conventional circuit topologies. The reduced voltage headroom further degrades cir-cuit linearity and an achievable signal-to-noise-and-interference ratio (SNIR). Therefore, the tuner architecture and each circuit block must be carefully designed to overcome the limitations of a low supply voltage and to comply with system requirements.

Implemented in 0.13 m CMOS technology from a single 1.2 V supply, this work focuses on the tuner design to tackle the challenges of a single low supply voltage and trade-offs among noise, linearity, power consumption, silicon area, and external bill-of-materials (BOM). Section II briefly states the system re-quirements. Section III characterizes the architecture and fre-quency plan of the RF tuner. Section IV describes the detailed circuit implementation, focusing on: 1) a low power consump-tion noise-canceling balun LNA; 2) an SNIR enhanced gain switching scheme with a current-mode instead of voltage-mode signal processing; 3) a wide-dynamic-range, highly integrated tunable channel-selection filter with auto-tuned bandwidth; 4) a fractional-N phase-locked loop (PLL) with agile automatic fre-quency calibration (AFC). Section V reports the experimental results, and Section VI concludes this paper.

II. SYSTEMSPECIFICATION

The MBRAI document details DVB-T/H RF specifications such as noise figure, sensitivity, selectivity, and linearity tests [7], [8]. Fig. 1 depicts the block partition of a DVB-T/H system. The defined requirements are referred to the RF reference point. In the updated MBRAI (MBRAI 2.0), it specifies a stringent noise figure (NF) requirement below 4 dB without the GSM-re-ject filter, which is 1 dB lower than that in MBRAI 1.0. Hence, the sensitivity for 8 MHz channel bandwidth shall be lower than 96.6 dBm for the QPSK 1/2 modulation scheme, having an SNR requirement of 4.6 dB. The use of the 64-QAM modulation scheme further poses difficult challenges on lowering impair-ments such as LO phase noise and I/Q mismatch. The associated SNR becomes as high as 27.5 dB in mobile reception conditions. The additive noise level from those impairments shall be at least 33 dB below the desired signal according to the MBRAI spec-ification. This leads to the requirement of LO integrated phase noise below 37 dBc and I/Q mismatch below 35 dBc [1], translating into an equivalent SNR of 33 dB if neglecting the

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Fig. 1. Block diagram of a DVB-H system.

AWGN contribution. However, the distortion due to I/Q mis-match can be estimated and compensated in the baseband pro-cessor [9]. Therefore, the requirement of I/Q mismatch in the RF receiver can be largely mitigated if the digital demodulator supports I/Q correction.

The wide frequency spectrum of DVB-T/H causes the issue that the desired signal usually comes with multiple band in-terferers. Several types of interference tests are specified in the MBRAI document to characterize the interference from strong undesired signals. The interference tests include two categories: 1) receiver selectivity testing with a single analog or digital in-terferer, and 2) receiver linearity testing with two analog and/or digital TV interferers. From these test specifications, linearity together with NF requirements can thus be derived by analytical calculations and system simulations [1], [3], [6]. For example, the L3 test leads to a minimum requirement of 7 dBm IIP3 and 12 dB NF [3]. In addition, the S2 test with a large TV inter-ferer at the channel requires a baseband IIP2 in excess of 30 dBm [6]. Conforming to these stringent tests requires a large dynamic range. Thus, a gain tuning scheme at the very front-end is necessary to protect the following stages from being saturated by far-off blockers, and to optimize the SNIR perfor-mance. This is especially important for a tuner having a low supply voltage.

III. FREQUENCYPLAN ANDTUNERARCHITECTURE

Frequency downconversion is essential in an RF tuner. A small LO frequency tuning range permits a small chip area and high performance. In previous work, frequency downconversion required an LO source with dividers of divide-by-2 and/or di-vide-by-4 to cover the UHF and the L bands [1]–[4]. Such a scheme calls for very wide frequency tuning of the LO source up to 62%, from 1.88 to 3.56 GHz or from 0.94 to 1.78 GHz. To re-duce the required VCO tuning range, the LO chain was designed using divide-by-2 and divide-by-3 dividers for UHF quadrature LO generation, and using a first-order polyphase filter for the L-band in [5], [6]. The required VCO range is thus reduced to 40%, from 1.2 GHz to 1.8 GHz. This work utilizes a similar fre-quency plan while multiplying the frefre-quency by two, requiring the VCO range from 2.56 to 3.84 GHz. The quadrature LO sig-nals are generated using divide-by-4 and divide-by-6 dividers in the UHF band, and using a divide-by-2 circuit in the L-band. Such a plan avoids using a polyphase filter and a divide-by-3 circuit, which potentially produces high I/Q mismatch. Further-more, operating at higher frequencies enables the use of on-chip inductors with smaller area and higher Q-factors.

The tuner adopts the direct-conversion architecture to fulfill small physical size and low power consumption. The block dia-gram of the tuner is as shown in Fig. 2. Except for the front-end, all circuit blocks are shared for dual-band operation to save chip area. The signal received from the UHF- or L-band antenna is amplified and down-converted to the baseband in two sepa-rate signal paths. This facilitates the connection to different ex-ternal RF filters for each band. Moreover, two sets of I/Q mixers avoid complicated combinations required in both RF signal and LO paths. After down-conversion, both UHF and L-band signal chains are combined in the current mode at the input of the tran-simpedance amplifier (TIA). Subsequently, the analog baseband circuitry removes the out-of-channel interferers and amplifies the signal to the desired amplitude. Finally, the tuner produces I/Q balanced outputs for further signal processing at the base-band demodulator.

The single-ended-input differential-output low-noise am-plifier (LNA), or balun LNA, facilitates the connection to the front antenna and to the following mixer of double balanced topology. It eliminates the need of an off-chip balun in front of the LNA for low noise figure and low external BOM. Also, it needs no on-chip balun after LNA, effective for low distortion as well as low power consumption. In this design, digitally controlled variable-gain function is included in both the front-end and the analog baseband to achieve the optimal SNIR. A wideband detector senses the total received RF power and then delivers an RSSI signal to the baseband demodulator to assist rapid front-end gain adjustment. Gain control can be done via a serial control bus or via an on-chip 7-bit SAR ADC by interfacing an analog signal from the baseband demodulator. To facilitate time slicing operation in the DVB-H system, one independent pin is ready for the baseband demodulator to switch the receiver on and off.

IV. CIRCUITIMPLEMENTATION A. RF Front-End

The front-end consists of two sets of LNAs and I/Q mixers for the UHF and L-band, respectively. Fig. 3 shows the simpli-fied schematic for the UHF band. Identical topology is used for L-band implementation except replacing the LNA resistor load with the on-chip inductor load.

Recently the Balun LNA has been demonstrated successfully by using the hybrid common-gate (CG) and common-source (CS) amplifier topology, which exhibits not only broadband single-to-differential conversion but also noise cancella-tion [10]–[12]. The convencancella-tional topology is as shown in Fig. 4(a). The input impedance is dominated by the CG

am-plifier M1. If , broadband impedance

matching is achieved. A balanced voltage output is obtained if . As a result, the differential output voltage gain is as . Note that it requires only

to have a voltage gain of 20 dB, indicating the topology is applicable to low supply voltage applications. This load re-sistance causes no significant dc drop across the load, and also allows a loading capacitance as large as 600 fF to ensure 1 GHz bandwidth. As to noise performance, the noise from M1 appears as the common-mode response and contributes

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Fig. 2. Block diagram of the designed RF tuner.

almost no output in the balanced condition. As such, only M2 noise contributes significantly to the noise factor in the form of , where represents the voltage gain of the LNA and stands for the excess noise factor. Unfortu-nately, the LNA noise performance is still poor. For example, the total noise figure of LNA will be larger than 3.8 dB assuming

, , and .

One method to resolve this issue is by increasing the input transconductance and decreasing the load resistance accordingly, keeping a balanced output. By designing larger than four times of , an NF less than 3 dB is achieved at the expense of 14 mW power consumption in [11], [12].

The proposed LNA design in this work utilizes the technique of dual cross coupling (DCC) as shown in Fig. 4(b) to improve noise performance. DCC allows symmetric device dimensions in the two branches without increasing current dissipation. It includes two types of cross coupling. One type is the bulk cross-coupling (BCC) applied to the input transconductance stage by connecting the body terminals to the source nodes of the devices. The body source cross-coupled configuration successfully incorporates an extra bulk-driven transconductor [13] with the conventional gate-driven one. The input transcon-ductance is thus enhanced by 20% in such dual-gate transistor implementation without consuming extra dc current. The boosted input transconductance increases the voltage gain and reduces the noise contribution from the current buffer and the load resistors. It is worth mentioning that increasing voltage gain without relying on more current dissipation or larger load resistors might mitigate the problem of insufficient voltage headroom in low-voltage design.

The other type of cross coupling is the capacitive cross-cou-pling (CCC) applied to the cascode stage using a pair of cross-coupled feed-forward capacitors . As compared to the conventional topology, the proposed CCC technique helps reduce the contribution from M2 channel noise, , without increasing . The coupling results in a negative feed-forward path to improve NF performance. The output noise due to is analyzed by the simplified schematic as shown in Fig. 4(c), where the cross-coupling capacitor is ignored . The total output noise current is the difference of the two output noise current , and generated

from as . The equivalent

circuit for noise analysis is shown in Fig. 4(d), with M1, M2, and M4 each replaced by an effective impedance. The output noise current is determined by using the impedance ratio based upon the current division principle at node X, while is generated through M3 acting as a CS amplifier with a degenerative resistance . Therefore, the two output noise current and , can be expressed, respectively, as

(1) (2) Thus, the total output noise current is approximately as

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Fig. 3. Simplified schematic of RF front-end for operation at UHF band.

Fig. 4. Balun LNA in (a) the conventional hybrid CG and CS amplifier, and (b) the proposed hybrid CG and CS amplifier with the DCC technique. (c) Simplified schematic of LNA for noise analysis. (d) The equivalent circuit for M2 channel noise analysis.

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Fig. 5. Simulated noise contribution of dominant devices to the total output noise between the proposed and conventional LNAs.

Performing KCL/KVL at node X and Y, we obtain the three terminal impedances as

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(6) where is a shorthand notation standing for

(7) The effect of the proposed CCC technique can be observed from these impedances. From (4), is boosted about 0.4 times of intrinsic gain, or , due to the negative feed-forward through the path from to the gate of , if compared to in the case of a simple CG transistor as a current buffer. From (5), is reduced about one half due to the shunt feedback through the path from , then , to the gate of . From (6), is enlarged by a factor larger than two due to the series feedback by the source resistance . Consequently, in this design, is close to and is about 4 times of , leading to the noise current gain about 0.64 from (3). As a result, the transistor M2 contributes to the noise factor, reduced by a factor of 0.41 as compared to the conventional balun topology without the CCC technique.

Fig. 5 illustrates the simulated noise contribution of , , , and source resistance of 50 to the total output noise. The conventional balun LNA without the DCC technique is also explored for comparison with this proposed balun LNA with DCC technique. As can be seen, the percentage of noise contribution from M2 is much reduced in the proposed balun LNA. Further analysis shows that noise figure improvement of

0.7 dB is achieved as compared to the conventional balun LNA. The proposed balun LNA exhibits a noise figure of 2.1 dB, a nominal gain of 21 dB, and IIP3 of 0 dBm while drawing only 3 mA, 75% of power reduction as compared to the previous work [10], [11].

A cascode amplifier is cascaded to the proposed balun LNA to obtain maximum front-end gain. Variable gain control is implemented by three methods in combination of these two cascode amplifiers. Fine gain tuning is realized by a bank of digitally controlled resistor load , providing 12 dB gain range in 2 dB steps. Coarse gain stepping is carried out by the current steering technique of switching [14] with a gain step of 5 dB, and by a novel current-mode scheme of switching the signal path. Furthermore, an additional gain switch path not shown is also implemented using the pre-attenuation method [15]. It provides a 5 dB gain attenuation and 15 dBm IIP3 to further extend the input dynamic range.

As shown in Fig. 3, a pair of switch transistors is in-serted between the low impedance terminals of the two cascode amplifiers, providing the signal path of gain attenuation. Fig. 6 illustrates how to achieve high-gain and low-gain by switching the signal path. When the switch transistors are turned off, the front-end is configured as cascaded two-stage amplifiers, pro-viding a transconductance of to the input voltage . When the switch transistors are turned on and transistors are all off, the front-end is configured as one single-stage cascode amplifier, giving a transconductance of . As a result, one-step gain attenuation of is achieved. This current-mode scheme effectively reduces the distortions caused by voltage modulation. It avoids large voltage swings across the switch transistors as compared to the conventional voltage switching method. Besides, it also substantially helps achieve high linearity by avoiding inter-stage intermodulation since the two cascaded amplifiers are reduced to a single-stage amplifier. In addition to linearity, this scheme causes negligible loading effect on the low-impedance terminals due to switch transistor parasitics. It avoids degrading the operating frequency range.

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Fig. 6. (a) Front-end configuration at high-gain mode. (b) Front-end configuration at low-gain mode.

Another important advantage is that this scheme affects no input and output interface after gain switching so that the input matching condition can be maintained. Furthermore, this scheme also features much better noise performance if com-pared with the conventional variable load or current steering methods when the gain attenuation becomes much larger. The measured results show that this switched path offers a stepped attenuation of 15 dB with a high IIP3 level of 5 dBm, im-proved by 18 dB from that at the maximum gain configuration while noise figure degrades only by 6 dB in overall receive chain, 9 dB better than the conventional pre-attenuation method [16]. However, a gain step of 19 dB is measured in the L-band due to the inductor load having higher resonant resistance, and an IIP3 up to 8 dBm is achieved.

Instead of using a Gilbert mixer, a current-mode passive mixer is utilized to achieve high linearity with a flexible output DC level. The mixer output must have a DC level compatible to the analog baseband input, since it is directly coupled to the analog baseband in a direct-conversion receiver. With a common-mode level of half supply voltage, the analog baseband built using an active RC structure achieves output swing that is almost rail to rail, alleviating the constraints of a low supply voltage. For 1.2 V operation, such a low common-mode level would pose a difficult challenge for a Gilbert mixer because it requires stacking of multiple devices. Instead, a current-mode passive mixer avoids a large voltage swing across the transistor and has no dc current dissipation. Thus, the control of DC level is much more flexible. As shown in Fig. 3, the quadrature mixer is composed of a transconductance amplifier followed by a mixing quad. It helps minimize quadrature inaccuracy by sharing one common input transconductor between I and Q paths. After down-conversion through the mixing quad, the baseband current is driven into the TIA in an OP-amp RC structure and then converted to voltage. The TIA achieves a maximum allowable output swing of over 2 V peak-to-peak differential at the expense of 7 mA current dissipation. One tracked pole placed in the TIA can pre-filter the adjacent interference which may saturate the first stage of the following filter because its full swing is limited by the low 1.2 V supply voltage.

B. Analog Baseband

The analog baseband functions as channel selection and programmable amplification for both In-phase and Quadrature signal processing. Programmable gain function provides the flexibility to optimize noise, linearity and power consumption. To optimize noise, power consumption and silicon area, it is necessary to make trade-offs in the Op-amp together with the input/feedback resistor pair. In this design, the analog baseband provides total gain control from 0 to 63.5 dB in 0.5 dB steps. It includes several circuit blocks as shown in Fig. 7: a vari-able-gain low-pass channel filter (VGCF) with cutoff frequency calibration, a first-order all-pass filter, a programmable-gain amplifier, four independent dc-offset cancellation (DCOC) loops with on-chip capacitors, and a unit-gain buffer.

The channel filter is a seventh-order Chebyshev type-I imple-mented using the leap-frog topology. Embedded into the filter blocks, gain control provides a range from 0 to 48 dB with a tunable cutoff frequency from 2 to 5 MHz depending on the channel bandwidth in use. In the VGCF, the first two Op-amps consume high current for low noise and large signal-handling capability. Also small input/feedback resistor pairs are applied to reach better noise performance at the expense of large ca-pacitor area. The remaining five Op-amps consume less current since the noise contributions are less critical. In addition, the input/feedback resistor pairs have high resistances to reduce the capacitor area. Following the VGCF, the first-order all-pass filter is added to improve the group delay. Then two PGA stages pro-vide an extra gain of 15.5 dB.

On-chip RC auto-calibration activated at power up accurately sets up the channel bandwidth from 2.5 to 4 MHz against PVT variations. The architecture and the timing diagram are depicted in Fig. 8. A duplicate RC integrator compares the RC time con-stant with a reference clock generated from the crystal output through a programmable divider. The detailed procedure is de-scribed as follows.

Two successive states are utilized to complete the auto-cal-ibration process in an iterative process. In the first phase, the clock is set to high. The integrator is configured as a resistive feedback amplifier with gain attenuation. As a result, both integrator outputs, and , are reset to the Op-amp’s

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Fig. 7. Architecture of analog baseband.

common-mode voltage. In the second phase, is low. The integrator is configured as a lossless integrator, which forces its positive output to charge toward and its negative output to discharge to ground. Once voltage becomes smaller than the reference voltage, the comparator will deliver a control signal to stop counting. The 6-bit counter’s code is sub-sequently subtracted from the Bandwidth Code, a default value of RC time constant corresponding to the channel bandwidth. After that, the subtracted output code is sent to update the Ca-pacitor Code used to control the caCa-pacitor banks. The calibration will continue until the capacitor code remains constant for sev-eral consecutive iterations. As soon as the calibration is finished, another control signal will be sent to power off the calibration circuits and stop the input clock. Finally, a 5-bit control word is provided to adjust the capacitors in the TIA and filter stages within 3% bandwidth accuracy.

DC-offset cancellation is indispensable in a direct conversion receiver because DC offset may saturate the baseband output and degrade the dynamic range. Featuring a high-pass response in the signal chain, the DCOC has a cutoff frequency less than 1 kHz to ensure sub-carriers around DC are not affected too much. However, if a single loop cancellation is utilized, such a low cutoff frequency will demand for large loop capacitors, inevitably implemented in off-chip components at the expense of four extra package pins [2], [3]. Since the high-pass corner frequency is proportional to the signal processing gain, but in-verse to the loop capacitance, multi-loop cancellation can effec-tively reduce the required loop capacitances. For example, as the signal chain is uniformly divided into M segments in cascade and each segment has an independent servo-loop for DCOC, the processing gain and the used capacitance in each loop can be expressed by and , respectively, where is the total gain of the signal chain and is the total capacitance required in M loops. To maintain the same high-pass corner fre-quency in the single-loop and multi-loop implementations, the ratio of the total required loop capacitance in single-loop cali-bration to that in multi-loop can be approximated as

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where is the total capacitance required in single-loop cancel-lation. In this design, four independent servo-loops are utilized to reject DC offset, in total using 16 pF capacitance which is much easier to integrate on chip since 60 times less total capac-itance is required compared with a single loop implementation. The final high-pass cutoff frequency is set constant at 1 kHz for all gain settings by keeping the gain of feedback loop in-versely proportional to that of the signal path. Furthermore, the remaining DC offset resulting from the last stage of the servo loop chain is carefully minimized by enhancing transistor sym-metry and by using larger dimensions. The measured DC offset is less than 6 mV with an average of 4 mV characterized over 50 samples at the maximum gain setting. The analog baseband totally dissipates 22 mA current, where 8.3 mA is dissipated by the first two stages. The simulated input-referred noise level is about 6 nV Hz.

C. Frequency Synthesizer

A fractional-N PLL synthesizer using a third-order delta-sigma modulator with 24-bit accumulators is employed to achieve a high resolution and fast switching time as well as good phase noise. The frequency step of this synthesizer is less than 10 Hz to meet the requirement of multi-standard opera-tion where different channel spacing is specified. In addiopera-tion, fractional synthesis provides the flexibility to share the same crystal with the existing cellular platform to reduce the BOM cost and PCB area.

The synthesizer generates a wide frequency output from 2.56 to 3.84 GHz by using two VCOs with overlapped tuning charac-teristics. As shown in Fig. 9, each VCO consists of two PMOS cross-coupled transistors with an internal regulator and one LC tank. The on-chip voltage regulator reduces the impact of power supply noise [17]. Moreover, the tank which is terminated into DC ground enables a wide range of analog control almost from rail to rail, which is crucial for low-voltage VCO design.

As far as phase noise is concerned, the entire tuning range is divided into 64 sub-bands by a 6-bit capacitor bank to de-crease the voltage-to-frequency gain. Consequently, adaptive frequency calibration (AFC) is needed to select a specific

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sub-Fig. 8. (a) Architecture of the RC calibration loop. (b) Timing diagram of the RC calibration loop.

Fig. 9. Schematic of VCOs.

band prior to starting the process of phase locking. The AFC procedure is described as follows. In the beginning, the PLL loop is open and the analog control terminal of the VCO is biased at half supply voltage. Subsequently, AFC is activated, trying to select an appropriate sub-band using the binary search method by comparing the divided VCO frequency with the ref-erence one. Instead of using counters [18], the frequency

de-Fig. 10. Measured locking process of frequency synthesizer.

tector is implemented using a quadri-correlator to shorten the comparison time [19]. After one suitable sub-band has been chosen, the PLL loop is closed achieving phase locked, and AFC is turned off. The measured transient frequency response during the locking process is as shown in Fig. 10, showing a locking

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Fig. 11. Die photograph.

TABLE I

PERFORMANCESUMMARY OFRF TUNER

Measured at (Max RF019 dB).

time of 78 s including coarse and fine tuning. The locking time is still less than 100 s in the worst case of the power-up sequence.

V. MEASUREMENTRESULTS

The tuner chip was fabricated in 0.13 m 1P8M CMOS process. It occupies a total silicon area of 7.2 mm including all ESD pads. The chip is housed in a mm 40-pin QFN package. The micrograph of the die is as shown in Fig. 11, where the analog baseband occupies a significant portion of the chip area due to using lower-density MIM capacitors of 1 fF . The measured performance referred to the SMA connector input from a single 1.2 V supply is summarized in Table I.

The measured NF ranges from 3.7 dB to 4.3 dB in the UHF band. The stated IIP3 values are measured, applying two-tone frequencies at 13.25 MHz and 29.25 MHz away from the desired

Fig. 12. Phase noise profile measured at synthesizer output.

Fig. 13. MeasuredC=(N + I) vs. input power for the test chip comprising digital front-end.

TABLE II

SELECTIVITY/LINEARITY ANDSENSITIVITYMEASUREMENTRESULTS

frequency, whereas, for the IIP2, a two-tone test with blockers at 13.25 MHz and 16 MHz offset was performed. At 11 dB back-off from maximum RF gain, which is convergent by the RSSI-AGC loop for L3 blocking test, IIP3 is 4.3 dBm while

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TABLE III

BENCHMARK OFRF TUNERS FORDVB-H APPLICATIONS

5 dB Noise Figure is measured at the channel above 800 MHz Measured at (Max RF010 dB).

NF is 8.7 dB. The current switch path provides a 15 dB RF gain backoff, achieving a baseband IIP2 of 50 dBm in the UHF band. The measured phase noise spectrum at the synthesizer output is as shown in Fig. 12. The noise profile will be lowered by 15 dB after 6 divisions for 626 MHz channel, resulting in an integrated noise from 400 Hz to 4 MHz better than 0.3 degrees. The C/N plot at the baseband output, evaluated in terms of EVM, is ex-hibited in Fig. 13 by applying an input signal of the 16-QAM 1/2 modulation scheme. The SNR shown is better than 30 dB from 70 dBm to 7 dBm, allowing for robust operation in a mo-bile environment. Because the BER test (system performance) depends on not only the radio chip but also the baseband de-modulator, the estimates in sensitivity, selectivity, and linearity tests are given according to the measured MER not exceeding one specific value based on the modulation scheme defined in the MBRAI specification. In Table II, these measurement results are summarized.

Compared with the previously reported work related to DVB-H tuner, shown in Table III, this chip achieves the lowest power consumption from a single 1.2 V supply while maintaining comparable performance. The maximum power consumption is 114 mW in the UHF band as all circuits are activated in the continuous mode. However, the power con-sumption reduces to 103 mW in the L-band. The reduced power mainly results from the operation with divide-by-2 instead of divide-by-6 as well as no usage of RF power detector.

VI. CONCLUSION

A 1.2 V highly integrated RF tuner for DVB-T/H applica-tions in 0.13 m CMOS technology is demonstrated. Utilizing a direct-conversion structure and a smart frequency plan, the tuner consumes only 114 mW in the continuous mode and oc-cupies a silicon area of 7.2 mm . Together with system and circuit design techniques, this tuner complies with the MBRAI 1.0 requirement, while slightly insufficient to meet the stringent MBRAI 2.0 specifications. However, low BOM as well as small PCB size are achieved, requiring a minimum number of external components: an inductor and a coupling capacitor for each LNA input, a crystal, and RC components for the loop filter. Since the

supply voltage is as low as 1.2 V, it is straightforward to convert to advanced technologies of 65 nm and beyond towards a more competitive SoC solution.

ACKNOWLEDGMENT

The authors wish to thank Sou-Chieh Chang, Susie-Jean Liao, and Jia-Hung Peng for their support in the measurements.

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Ming-Ching Kuo (S’07) received the B.S. degree from the Department of Electrical Engineering and the M.S. degree from the Institute of Elec-tronics Engineering, National Tsing-Hua University, Hsinchu, Taiwan, in 1998 and 2000, respectively. He is currently working toward the Ph.D. degree in electronics engineering at National Chiao-Tung University, Hsinchu, Taiwan.

In 2001, he joined the High-Frequency IC Design Department of the SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Taiwan, as a Design Engineer. His research interests are in the area of wireless communication integrated circuits.

Shiau-Wen Kao received the B.S. degree in electrical engineering from National Sun Yat-Sen University, Kaohsiung, Taiwan, in 1999 and the M.S. degree from the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan, in 2002.

In 2002, he joined SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, as a Design Engineer. His current research interests are in low power and high performance analog/mixed-signal integrated circuits.

Chih-Hung Chen was born in Kaohsiung, Taiwan, 1978. He received the B.S. degree in electrical engineering from Feng Chia University, Taichung, Taiwan in 2001 and the M.S. degree from the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan, in 2003.

In 2003, he joined the SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, where he was engaged in the re-search and development of integrated CMOS VCO, and RF frequency synthesizers for wireless communi-cation applicommuni-cations. Since 2008, he has been with Novatek as a design engineer, developing high-speed circuits for serial interfaces such as DVI/HDMI.

Tsung-Shuen Hung received the B.S. degree in elec-tronics engineering from United University, Miaoli, Taiwan, in 2002 and the M.S. degree in electronics engineering from National Yunlin University of Sci-ence and Technology, Taiwan, in 2004.

He joined Opto-Electronics and Systems Labora-tories, and SoC Technology Center, Industrial Tech-nology Research Institute (ITRI), Hsinchu, Taiwan, in 2004 and 2006, respectively. His research interests in mixed-signal, high-speed and high-resolution inte-grated circuits design in data communications.

Yi-Shing Shih was born in Changhua, Taiwan, 1981. He received the B.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2003 and the M.S. degree in communication engineering from National Chiao Tung University, Hsinchu, in 2006.

In 2007, he joined SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. His research interests are in the area of RF and analog integrated circuit design. He is currently working on 65 nm RF IC design for Mobile TV applications.

Tzu-Yi Yang was born in Taichung, Taiwan, 1973. He received the B.S. degree in electronics engineering from National Chiao-Tung University, Taiwan, in 1995, and the M.S. degree in electrical engineering from National Taiwan University, Taipei, in 1997.

After graduation, he worked for Electronic Re-search & Service Organization (ERSO), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan on RF integrated circuit design. Since 2001, he joined SoC Technology Center (STC), ITRI, Taiwan. His research interests are integrated circuits and systems for wireless communications.

Chien-Nan Kuo (S’93–M’97) received the B.S. degree from National Chiao Tung University, Hsin Chu, Taiwan, in 1988, the M.S. degree from National Taiwan University, Taipei, Taiwan, in 1990, and the Ph.D. degree in electrical engineering from the University of California, Los Angeles (UCLA), in 1997.

In 1997, he joined ADC Telecommunications, San Diego, CA, as a Member of Technical Staff with the Mobile System Division, during which time he was involved in wireless base-station design. In 1999, he joined Broadband Innovations Inc. In 2001, he joined the Microelectronics Di-vision, IBM. He is currently Assistant Professor in Department of Electronics Engineering, National Chiao Tung University. His research interests include re-configurable RF circuit and system integration design, low-power design for the application of wireless sensor networks, and development of circuit-package co-design in the system-in-package (SiP) technique.

Dr. Kuo was a recipient of IEEE MTT Graduate Fellowship Award in 1996. He was a co-recipient of the 2006 Best Paper Award presented at the 13th IEEE International Conference on Electronics, Circuits and Systems. He has served as a Program Committee member in IEEE Asian Solid-State Circuits Conference since 2005.

A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS