A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

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in the BZ-FAD architecture. For SPST (synthesized in gate level) the critical path is about 25 ns.

V. SUMMARY ANDCONCLUSION

In this paper, a low-power architecture for shift-and-add multipliers was proposed. The modifications to the conventional architecture in-cluded the removal of the shift of theB register (in A 2 B), direct feeding ofA to the adder, bypassing the adder whenever possible, use of a ring counter instead of the binary counter, and removal of the par-tial product shift. The results showed an average power reduction of 30% by the proposed architecture. We also compared our multiplier with SPST [6], a low-power tree-based array multiplier. The compar-ison showed that the power saving of BZ-FAD was only 6% lower than that of SPST whereas the SPST area was five times higher than that of the BZ-FAD. Thus, for applications where small area and high speed are important concerns, BZ-FAD is an excellent choice.

Additionally, we proposed a low-power architecture for ring coun-ters based on partitioning the counter into blocks of flip-flops clack gated with a special clock gating structure the complexity of which was independent of the block sizes. The simulation results showed that in comparison with the conventional architecture, the proposed archi-tecture reduced the power consumption more than 75% for the 64-bit counter.

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A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, and Jwu E Chen

Abstract—For very deep sub-micrometer VLSI, crosstalk becomes

an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.

Index Terms—Crosstalk, delay, glitch, interconnect.

I. INTRODUCTION

The crosstalk-induced noises have been attracting increasing atten-tion as spacing between lines decreases and coupling capacitances increases in the interconnection structure of deep sub-micrometer VLSI. These noises affect the circuit performance in two ways: glitches, which may be captured by end latches to produce erroneous logic values, or signal propagation delay [1], [2]. These crosstalk issues should be considered during the design stage for performance, and they should be tested during the manufacture step.

The crosstalk noises on interconnect lines had been modeled and analyzed in many previous works. For example, they were studied by treating the interconnect lines as coupled lossy transmission lines [3], [4], and analyzed numerically [5], [6]. Simulation models for intercon-nect lines were also reported [7]. Simplified lumped resistance–capac-itance (RC) model for studying crosstalk noises was proposed and an-alyzed by many authors [1], [2], [8], [9]. Other issues for crosstalk, in-cluding fault avoidance, test generation, test set evaluation, and built-in

Manuscript received March 02, 2007; revised July 09, 2007. First published January 06, 2009; current version published January 14, 2009.

K. S.-M. Li is with the Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail: smli@ cse. nsysu.edu.tw; gis88554@cis.nctu.edu.tw).

C.-L. Lee and C. Su are with the Department of Electronics Engineering, Na-tional Chiao Tung University, Hsichu, Taiwan (e-mail: cllee@mail.nctu.edu.tw; ccsu@cn.nctu.edu.tw).

J.-E Chen is with the Department of Electrical Engineering, National Central University, Chungli, Taiwan (e-mail: jechen@ee.ncu.edu.tw).

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Fig. 1. Circuit model for the crosstalk analysis.

self-test (BIST) had been reported in [10]–[14]. In addition, various on-chip circuits for the measurement of crosstalk effects have been pro-posed [15], [16], including measuring glitch amplitude [15], or charac-terizing the crosstalk effects [16]. A comprehensive review of signal in-tegrity problem, including crosstalk modeling, analysis, and measure-ment was given in [17].

In general, the two crosstalk effects, i.e., the induced glitches and the induced delay, require different fault detection techniques. A glitch can be easily detected by a pulse detector. On the other hand, delay fault detection requires more complicated at-speed test schemes or spe-cial measurement circuit if timing measurement is involved [17], which complicates the testing process and increases the testing cost. In par-ticular, the on-chip measurement of delay effect is rather difficult and needs special circuit [17]. In this paper, we investigate the relationship between crosstalk glitch and induced delay, and identify their respec-tive importance in affecting the circuit performance; and then show that crosstalk induced delay can be tested by detecting glitches whose am-plitudes are larger than a predetermined detection threshold. The pro-posed method is implemented with a very simple circuit, and crosstalk induced delay faults can be detected in the same way as glitches are detected. This result greatly facilitates on-chip detection of crosstalk delay.

II. CIRCUITMODEL FORCROSSTALK

Coupling crosstalk effects are mainly caused by parasitic capacitors between neighboring interconnection lines. Fig. 1 shows the bus cir-cuit model, where adjacent wires run in parallel. The middle wire is the victim net, while the other two wires are the aggressor nets. The wires are driven by inverters served as buffers with characteristic “ON” re-sistancesRon-a1,Ron-a2, andRon-v, respectively. Each wire contains unit-length wire resistance (R_a1,R_a2, andR_v) and capacitance (C_a1, Ca2, andCv). A coupling capacitance (Cc1,Cc2) exists between two adjacent wires, which causes crosstalk effects. The output of each wire is connected to an end inverter, which also serves as a buffer. These end inverters provide the load,C_L1,C_L2, andC_Lv, for the wires, re-spectively. Assume that wires are homogenous (i.e.,Ra1 = Ra2 =

Rv = Rw,Ca1 = Ca2 = Cv = Cw,CL1 = CL2 = CLv = CL,

andCc1= Cc2). All aggressor signals are assumed to be synchronized in order to maximize the crosstalk effects and the skew effects among aggressor lines. In the following analysis, we conduct simulation for the circuit model shown in Fig. 1 with the TSMC 0.18m 1.8/3.3 V 1P6M technology. Metal 5 layer is used in the simulation, where the wire length is set to be 1 mm, and the wire width and spacing are both set to 0.28m, which are the minimum values allowed in the tech-nology. A distributed RC model is used to characterize the circuit be-havior. The power supply(VDD) is set to 1.8 V, and all transistors are

minimum sized.

Fig. 2. Superposition of crosstalk-induced delay.

III. RELATIONSHIPBETWEENGLITCHES ANDDELAYS Fig. 2 shows the SPICE simulation results for the circuit in Fig. 1 with the applied inputs. The curves are taken from pointB (i.e., the end of victim line). Two sets of simulations have been carried out: one with nominal coupling capacitance (upper figure), and the other with four times larger (lower figure) coupling capacitance. A curve marked with “+” is the response of the victim line when only a rising transition is applied to the input of the line, and a curve marked with “2” is the response of the same victim line but with only the crosstalk glitch ef-fect considered, i.e., a static “0” is applied to the victim line. The curve marked with “3” is the signal on the victim line with both excitations considered, i.e., the victim line is affected by the coupling effect and its own applied rising transition input. The curve(3) is exactly superpo-sition of the first(+) and second (2) curves in each case. This means that the crosstalk-induced delay is in fact the crosstalk-induced glitch plus the original response on the victim line.

The previous result is obvious since the interconnect part of the cir-cuit is a linear circir-cuit for which the superposition rule holds. The larger the glitch, the larger the induced delay. There is a monotonic relation-ship between the induced glitches and the induced delay, which is il-lustrated in Fig. 3. As the amplitude of induced glitch increases, the induced delay also increases. The induced delay is calculated as fol-lows. The propagation delay of a signal is defined as the time between input signal reaching 50% of its final value and output signal reaching 50% of its final value. The induced delay is thus the difference between propagation delays with and without excessive coupling effects.

The monotonic relationship suggests a unified crosstalk detection ap-proach. If the induced glitch is detected, the induced delay can also be detected. For example, in Fig. 3, if the specified delay of the intercon-nection line is 200 ps, we can detect if there are induced glitch faults with amplitude higher than 0.91 V. We can devise a detector to detect

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Fig. 4. PD with an adjustable threshold by W/L ratio of INV1.

the induced glitches; and once these induced glitches are detected, the corresponding induced delays are detected. Thus, a delay fault can be detected without actual delay measurement.

IV. PULSEDETECTORWITHDETECTIONTHRESHOLD A glitch is a pulse, and it can be detected by a pulse detector. In order to detect the crosstalk-induced glitch with a given peak value (ampli-tude), we should be able to adjust the detection threshold of a detector. A pulse detector (PD) is shown in Fig. 4. The detector consists of two major components: an inverter(INV₁) that is used to determine the detection threshold voltage(Vdet), and a pseudo static latch (the

re-maining part) that is locked to “1” once a pulse is detected. The latch is enabled byVDD, which is controlled by a pMOS pass transistor. The two pass transistors are controlled byINV₁and they serve as a multi-plexer. The detection thresholdVdetof the pulse detector is determined by the W/L values of pull-down nMOS and/or pull-up pMOS inINV1. The latch can be reset by a reset input. Whenever a glitch whose ampli-tude is higher than the detection thresholdVdet, the pMOS pass tran-sistor will be turned on and the latch outputq is set to “1”, indicating a glitch is detected.

The transient behavior of the PD is illustrated in Fig. 5 by SPICE simulation. The upper figure show the input waveform (in), which is a glitch generated by 1 mm Metal 5 wires with quadruple coupling as shown in Fig. 2, and the output ofINV1(in_). Signal in_ is the inverse of in, and since the swing of in_ is large enough to temporarily turn off the nMOS pass transistor while at the same time turn on the pMOS pass transistor, the latch output(q) changes state successfully, as shown in the lower part of the figure.

Fig. 6 shows the simulated results on the threshold of the detected pulse amplitude (V_det) versus (W=L)_{p mos}=(W=L)_{n mos} in INV₁ of the pulse detector. Both pass transistors are minimum sized, with W=L = 0.22 m=0.18 m. In the gates, except for INV1, all nMOS transistors are minimum-sized with L_n = 0.18 m and

Fig. 5. Simulated transient waveform of the PD.

Fig. 6. Simulated relationship between the thresholds of detection threshold voltage(V ) versus the W/L ratio of the PD.

Wn = 0.22 m, while in the logic gates the channel widths of

pMOS transistors are increased to equalize the rising and falling transition time: Lp = 0.18 m and Wp = 0.50 m. In INV1, Ln= Lp= 0.18 m, while WnandWpare varied to create different

detection thresholds (Vdet). The figure shows that the detection

threshold of the pulse detector is adjustable by changing the W/L ratio of the pull-up transistors (pMOS) and pull-down (nMOS) inINV1.

In general, many simulations are needed to determine the proper W/L ratios of the MOS transistors for a given detection threshold Vdet. To facilitate the design, a procedure similar to the binary search algorithm can be used to determine the ratio r = (W=L)p mos=(W=L)n mos for the target Vdet, except that the geometric mean is used instead of the arithmetic mean in each iteration.

The PD itself becomes a load to the victim line, and hence may im-pact the pulse detection result. A PD with very large or very small

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Fig. 7. Delay (picoseconds) versus skews: (a) 3-D waveforms and (b) 3-D mesh.

detection threshold requires a very wide nMOS or pMOS transistor, which is essentially a large load capacitance. One should always avoid using such detectors.

V. SOMECONSIDERATIONS FORUNIFIEDDETECTIONSCHEME A. Effect of Skew Between Aggressor and Victim Signals

In Sections II and III, it is assumed that excitations from aggressor lines are synchronous, and the falling excitation signals are in coinci-dence with the rising edge of the victim line signal, i.e., there was no skew between signals on the lines. In practice, the signals on aggressor lines and in the victim line may not be in coincidence. One might think that the induced delay on a victim line is maximized when the falling edges of the aggressors’ excitation signals and the rising edge of the victim line signal occur at the same time. However, according to [18], the maximum delay actually occurs when there is a little skew between these two signals. To investigate how the relationship between the peak amplitude of the induced glitch and the induced delay is affected by the skew between aggressor lines and the victim line, we conducted simu-lation for the three-wire system in Fig. 1, considering different skews between aggressor lines and the victim line. Metal 5 layer is used in the simulation, where the wire length is set to be 1 mm, and the wire

Fig. 8. Glitch (Volts) versus skews: (a) 3-D waveforms and (b) 3-D mesh.

width and spacing are both set to 0.28m. For the output buffers, all nMOS transistors are minimum-sized(W=L = 0:22=0:18), while the size of nMOS transistors is 0.5/0.18. To maximize the induced glitch, the widths of transistors in the input buffers are set to 102 of the min-imum values. The results are given in Figs. 7 and 8.

Let the skew between aggressor 1 (aggressor 2) and the victim be denoted as SK₁(SK₂). In the simulation, we set 080 ps SK₁, SK2 + 80 ps. For skews outside this range, the coupling effects on

signal delay are negligible. Fig. 6 plots the crosstalk-induced delay on the victim net, which is shown in thez-axis with the unit in picosecond, versus the aggressor signals’ skews (SK₁andSK₂), and two figures are given. Fig. 6(a) shows 17 curves forSK1 = 080;070; . . . ; +80. In

each curve,SK₁is fixed whileSK₂is varied from080 ps to +80 ps. It can be seen that, in each curve, the induced delay increases asSK2

moves from080 ps toward +80 ps, and the maximum value occurs whenSK₂is slightly larger than 0, as reported in [17]. Fig. 6(b) is a 3-D mesh plot over the same set of data. Fig. 7 plots the relationship be-tween the glitch amplitude (measured inV ) versus skews. It can be seen that, in either case, the plot is symmetric with respect toSK1= SK2. In Fig. 7, we can see that the maximum glitch amplitude always hap-pens when the aggressor signals are synchronized (i.e.,SK1 = SK2). The reason is that, the glitch is the results of coupling effect only, and the coupling effect is maximized when both aggressor signals arrive at

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SK = SK = 0; 2) SK = SK = 080 ps; and 3) SK = 0; SK =45 ps.

the same time. On the other hand, the maximum delay is affected by the coupling effect as well as the skews. For a fixedSK1, the maximum delay occurs whenSK2is positive. In our experiments, for a fixedSK1, the delay is maximized whenSK₂is about+30 to +50 ps.

The results are summarized in Fig. 9 for three different cases: 1) SK1 = SK2 = 0; 2) SK1 = SK2 = 080 ps; (i.e., both aggressor

signals 1 and 2 arrived 80 ps before the victim line signal); and 3) SK1= 0, SK2=45 ps, (i.e., aggressor 1 has zero skew and aggressor

2 has 45 ps skew with respect to the victim line respectively). Case 1) is the case that the aggressor signals are in coincidence with the victim signal. Case 2) creates the maximum glitch but a small delay, while Case 3) represents the maximum delay but a small glitch. Thus, the re-lationship between the amplitude of the induced glitch and the induced delay spread as a band instead of a single line.

The spreading of curves in Fig. 9 depends on skews between ag-gressor lines. However, for a interconnect bus system, it could be safely assumed that these skews will not be large since signals on a bus system usually change simultaneously as a set of bits switch their states at the same time. Also, in the test mode, it could be relatively easy to have every bit in a bus switching at roughly the same time.

In the previous simulation, it is assumed that the aggressors’ drivers have the same driving strength. When the drivers’ sizes are different, a compact model [19] can be used for delay analysis.

B. Process Variation Effect on Pulse Detector

In Section IV, the detection threshold of the proposed pulse detector is adjusted by the W/L ratio of the input inverter. This W/L values, along with other circuit parameters, can be affected by the manufacture process variation. Hence, the relationship be-tween the threshold of detected pulse amplitude(Vdet) and the ratio

(W=L)p MOS=(W=L)n MOS of the pulse detector is also Monte

Carlo simulated. In the simulation, all circuit parameters of the pulse detector are allowed to be varied by 10% with respect to the nominal values. The results are shown in Fig. 10. The relationship becomes a band. A designer should consider the worst-case scenario in order to achieve enough fault coverage, and this will be covered in Section VI.

VI. MONTECARLOSIMULATION ON THEUNIFIEDDETECTION SCHEMECONSIDERINGPROCESSVARIATION

In Fig. 11, we demonstrate the overkill and escape probability with respect to (W/L) ratio of the pulse detector. The “overkill” occurs when a good circuit is identified as faulty by the PD, while “escape” occurs when a faulty circuit is identified to be fault-free. Monte Carlo sim-ulations are carried out to show the process variation effect on both overkill and escape probability. Either process variation or signal skews may cause overkill or escape condition. For example, if the threshold

Fig. 10. Monte Carlo simulation of the threshold of detected pulse amplitude (V ) with respect to the W/L ratio of the pulse detector.

Fig. 11. Monte Carlo simulation of the escape probability and overkill proba-bility with respect to (W/L) ratio.

is chosen according to the maximum induced delay but with the lowest peak of the induced glitch, i.e., Case 3) in Section V-A there may exist “Overkills”. As an example, assume that we want to detect an induced delay of 100 ps. According to Fig. 9, the PD threshold is set to about 0.55 V (the curve marked with2). However, if both SK1andSK2are 0 (the curve marked with ), a 0.55 V pulse corresponds to an induced delay smaller than 100 ps. As a result, the overkill condition occurs. On the other hand, if the threshold is chosen to Case 2) in Section V-A there may exist “Escapes”. Fig. 11 shows simulated probability for overkills and escapes with respect to the(W=L)p mos=(W=L)n mosratio of the pulse detector. With the ratio set to 1, the detection thresholdV_det is 0.91 V, which corresponds to a delay of about 200 ps. When the W/L ratio decreases, so does the detection thresholdV_det, and the proba-bility of overkills increases while the probaproba-bility of escapes decreases. On the other hand, a larger(W=L)p mos=(W=L)n mosratio produces a detector with a higher thresholdV_det, which increases the probability of escapes but decreases the probability of overkill.

VII. CONCLUSION

We analyzed the crosstalk effects on the interconnect bus in very deep submicrometer SOC VLSI circuits and proposed a unified detec-tion scheme to test glitches and the crosstalk induced delay at the same time. We found that the crosstalk induced fault in fact is superposition of the crosstalk induced glitch fault and the original applied signal on the victim line. For the unified detection scheme, we proposed a pulse detector whose detection threshold is determined by designers through transistor sizing, and thus it can also detect induced delay whose corre-sponding glitch amplitude exceeds the given detection threshold. Sev-eral issues regarding the detection scheme, such as the amplitude of the induced glitch, the skews between the applied excitation signals on the aggressor line and the victim line, and variations in PD were discussed.

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interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13- m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.

Index Terms—Bus drivers, bus receivers, digital CMOS, interconnect

sig-naling, level converters, low energy, low-voltage, performance tradeoffs.

I. INTRODUCTION

An ever increasing energy budget in the integrated circuits comes from the interconnect wires (busses, global clocks, and timing signals) and associated driver and receiver circuitries. In some gate array de-sign styles power dissipation from the interconnect wires amounts to up to 40% [1] of the total on-chip power dissipation. On the field-pro-grammable gate array (FPGA) fabric the reported power dissipation from interconnect wires is up to 90% [2]. Interconnect is also a domi-nating factor in the chip performance and robustness [3], [4].

To achieve power reduction and energy2 delay efficiency on the global interconnects reducing the voltage swing of the signal on the wire is the most effective way. However, reducing the voltage swing generally comes at the expense of reduced reliability and performance and increase in the driver and receiver complexity. Signal reliability and integrity effects include interconnect delay, cross talk, transmission line effects, substrate coupling, power supply integrity, and noise-on-delay effects [4].

Most low-swing voltage techniques to-date [1], [5] rely on extra power supply, or reference voltage, multiple threshold process tech-nology, large area penalty, and multiple wire interconnects when differ-ential signaling is employed [6]. They also suffer from large short-cir-cuit current problem, long propagation delay, and high power dissipa-tion [1], [5]. Due to reducdissipa-tion in the voltage swing, drivers for the low-swing voltage signaling schemes generally do not provide sufficient driving capability for the larger loads. In order to improve the driving capability, some driver circuits rely on bootstrapping techniques [7], [8]. However, these circuits require extra bootstrapping capacitors, and generally need access to the well terminals that may not be readily available in many digital CMOS processes.

Manuscript received May 08, 2007; revised October 15, 2007. First published January 06, 2009; current version published January 14, 2009.

J. C. García Montesdeoca and J. A. Montiel-Nelson are with the Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, E-35017 Las Palmas de Gran Canaria, Spain (e-mail: jcgarcia@iuma.ulpgc.es; montiel@iuma.ulpgc.es).

S. Nooshabadi is with the Department of Information and Communications, Gwangju Institute of Science and Technology, GIST, Gwangju, Republic of Korea (e-mail: saeid@gist.ac.kr).