Contributed Paper
Original manuscript received July 11, 2003
Revised manuscript received January 29, 2003 0098 3063/04/$20.00 © 2004 IEEE Frame Memory Video Input DCT Q EncoderVLC Q-1 IDCT Frame Memory Motion Compensation Vario-Power Architecture of ME MV Pre-Processing Buffer Stream Output Host Procesor Power Mode Battery Monitor Unit Battery Pack CMB RMB
Fig. 1. A typical application of the vario-power ME architecture in a video compression system.
A Vario-Power ME Architecture
Using Content-Based Subsample Algorithm
Hsien-Wen Cheng and Lan-Rong Dung, Member, IEEE
Abstract —The Motion estimator is a key element in many
video compression systems and it tends to dominate the power consumption in them. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is essential. To meet this requirement, this paper presents a novel power-aware architecture, called the Vario-Power Architecture, for the motion estimation. Based on a semi-systolic array with the content-based subsample algorithm, the architecture real-time disables some processing elements to reduce power consumption. By performing the edge extraction first, a threshold is then set as the criterion of whether to enable or disable processing elements and thus the switch activities of the system can be reduced. As the simulation shows, the architecture may operate at different power consumption modes according to the remaining capacity of the battery pack giving little quality degradation and the power overhead under 0.36%.1
Index Terms —motion estimation, VLSI architecture, video compression, power-aware architecture, subsample.
I. INTRODUCTION
The technique of motion estimation has been widely used in the video compression system for years. As the demand of portable, power-aware multimedia devices increases, an architecture that can be flexible in both power consumption and compression quality is essential. This paper presents a power-aware architecture, called the Vario-Power Architecture, which provides real-time switching of power consumption mode for conserving battery life2 while it maintains the compression quality in high level. The proposed architecture is driven by the content-based subsample algorithm which maintain acceptable quality degradation when the system works at different power consumption modes; that is, the proposed architecture can perform trade-offs between power consumption and compression quality as the battery status changes. Because the control mechanism and data sequences at different power consumption modes are the same, the vario-power architecture can perform the switching of power consumption mode very smoothly. The block diagram shown in Fig.1 illustrates a typical
1 This work was supported in part by Taiwan MOE Program for Promoting
Academic Excellent of Universities under the grant number 91-E-FA06-4-4 and the National Science Council, R.O.C., under the grant number NSC 92-2220-E-009-003.
The authors are with the Department of Electrical and Control Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan, R.O.C. (email: [email protected]; [email protected]).
2 The idea is motivated from the SpeedStepTM technology of Intel [1].
application of the vario-power architecture for motion estimation in a video compression system. The host processor monitors the remaining capacity of the battery pack and switches the operation mode of the vario-power element to maintain the performance of the compression system better.
Lots of published papers presented efficient algorithms for the VLSI implementation of motion estimator either on high performance or low power design. Yet, most proposed algorithms cannot adapt their system to different power consumption modes. Among these proposed algorithms, the Full-Search Block-matching (FSBM) algorithm with Sum of Absolute Difference (SAD) criteria is the most popular approach for motion estimation because of its considerably good quality. There are many types of architecture which have been proposed for the implementation of FSBM algorithms [2] [3] [4] [5]. However, a huge number of comparison/difference operations result in high computational load and significant power consumption. To reduce the computational complexity of FSBM, researchers have proposed various fast algorithms by reducing the searching steps [6] [7] [8] [9] [10]. Unfortunately, these fast algorithms suffer from irregular block-matching scheme and much worse quality than FSBM, and they are not suitable for the implementation of vario-power architecture. Papers in [11] and [12] may reduce the computational load without degrading the compression quality; nevertheless, they both require additional operations for each search step and cannot adapt themselves to different power consumption modes. The Novel Early-Jump-Out (NEJO) technique in [13] addressed the low-power architecture with some quality degradation. However, the EJO also requires extra operations for each search step and is not feasible enough for vario-power architecture.
Articles in [14] and [15] present subsample algorithms to significantly reduce the computation cost with low quality de-gradation. The reduction of computational cost implies saving of the power consumption, and the power consumption can be reduced by simply increasing the subsample rate; thus, the subsample algorithms are very suitable for implementing the vario-power architecture. However, applying the subsample algorithms for the vario-power architecture may suffer from aliasing problem for high frequency band. The aliasing problem makes compression quality degrading rapidly as the subsample rate increases. To alleviate the problem, we extend the traditional subsample algorithm to a novel algorithm, which is called the content-based subsample algorithm. In our approach, we first use edge extraction techniques to separate the high-frequency band from a macro-block and then perform subsampling within the low-frequency band only. Based on the architecture proposed by Hsieh and Lin [4], we present a semi-systolic architecture which is driven by the content-based subsample algorithm. The proposed architecture can real-time alter the subsample rate as the power consumption mode changes. As the result shows, our methodology successfully switches the power mode while the quality degradation is a little.
II. GENERAL SUBSAMPLE ALGORITHM
The FSBM algorithm with SAD criteria is the most popular approach for motion estimation because of its considerably good quality and many published papers presented efficient architectures for the VLSI implementation of it [2] [3] [4] [5]. To determine the motion vector, the algorithm uses (1) and (2) to compare each current macro-block (CMB) of the frame with all the reference macro-blocks (RMB) in searching area.
1 1 0 0 ( , ) ( , ) ( , ) , where , 1. N N i j SAD u v S i u j v R i j p u v p − − = = = + + − − ≤ ≤ −
∑∑
(1) , 1 , 1 min ( , ) min ( , ) ( , ) p u v p p u v p MV SAD u v SAD SAD u v and MV u v − ≤ ≤ − − ≤ ≤ − = = uuuur uuuur (2)where the macro-block size is N-by-N, R(i,j) is the luminance value at (i,j) in the current macro-block (CMB). The S(i+u,j+v) is the luminance value at (i,j) of the reference macro-block (RMB) which is offset (u,v) from the CMB in the searching area which size is 2p-by-2p.
Many researches addressed subsample techniques for motion estimation to reduce the computation load of FSBM [14] [15]. Liu and Zaccarin, as pioneers of the subsample algorithms, significantly reduced the computational load by applying the 4-to-1 alternative subsampling to FSBM. As the simulation results show, the subsample algorithm reduces the computational load by a factor of 8 or 16 while the quality is similar to that of exhaustive search [14]. Here, we present the general subsample algorithm in which the subsample rate ranges from 4-to-1 to 1-to-1 for the vario-power architecture.
The general subsample algorithm shown in (3) uses the matching criterion which is called subsample sum of absolute difference (SSAD). In (3), the SM8:m which is generated from
(4) is the subsample mask for the subsample rate 8-to-m.
( )
( ) (
(
) ( )
)
( )
(
)
1 1 8: 8: 0 0 8: 8: 8: , , , , for 1,where ( , ) is the mask for 8- - subsample and , mod 4, mod 4 N N m m i j m m m SSAD u v SM i j S i u j v R i j p u,v p -SM i j to m SM i j BM i j − − = = = ⋅ + + − ≤ ≤ =
∑∑
(3)(
) (
) (
) (
)
(
) (
) (
) (
)
(
) (
) (
) (
)
(
) (
) (
) (
)
( )
( )
. 0 0 0 1 is, that function; step a is where 8 4 7 3 6 2 5 2 8 4 7 3 6 2 5 2 : 8 < ≥ = − − − − − − − − − − − − − − − − = for n , for n , n u n u m u m u m u m u m u m u m u m u m u m u m u m u m u m u m u m u BM m (4)Using the general subsample algorithm, the power consumption can be reduced by simply increasing the subsample rate in which way the reduction of computation cost implies the saving of power consumption. Obviously, the general subsample algorithm is very suitable to implement the vario-power architecture. However, the algorithm is rather content independent and suffers from aliasing problem in high frequency band. To enhance the performance, we introduce a content-dependent technique to the general subsample algorithm as addressed in the following section.
III. CONTENT-BASED SUBSAMPLE ALGORITHM As mentioned above, the general subsample algorithm has aliasing problem when it is in high subsample rate. The aliasing problem leads to considerable quality degradation because the high frequency band is messed up. To alleviate the problem, we use edge extraction techniques to separate the edge pixels from a macro-block and then perform subsampling to the remaining pixels.
Fig. 2 describes the procedure of the content-based subsample algorithm. The algorithm first determines edge pixels of the current macro-block and then generates the content-based subsample mask (CSM). Upon the CSM generated, we are able to calculate SSAD values and find the best motion vector. The determination of edge pixels starts from applying gradient filter in the current macro-block. In this paper, we use three popular gradient filters which are the high-pass filter, the Sobel filter and the morphological gradient filter to exercise the performance of the content-based algorithm [16]. Equations (5)-(8) illustrate their gradient calculations.
0 0 ; ; W H for(y ; y W N ; y ){ for(x ; x H N ; x ){ × = < + + = < + +
Input current and reference frames;
Perform gradient filtering
Calculate the edge threshold accroding to power mode Determine edge pixels and edge
( )
( ) (
(
) ( )
)
min 1 1 0 0 min ; ; , ; , ; , , N N i j SSAD (x y)for(u p;u p;u ){ for(v p;v p;v ){ SSAD u v CSM i, j S i u, j v R i, j if SSAD (x y) SSAD(u − − = = = ∞ = − < + + = − < + + = ⋅ + + − >
∑∑
maskGenerate content - based subsample mask (CSM)
min ,
for loop index for loop index for loop index for loop index
v)
{SSAD (x y) SSAD(u,v);MV(x, y) (u,v); }
}// v
}// u
}// x
}// y
= =
Fig. 2. The procedure of the content-based subsample algorithm.
High-Pass Filter:
( )
,(
,( )
,)
, 1 1 1 where 1 8 1 . 1 1 1 hpf mask mask G i j MF HPF R i j HPF = − − − = − − − − − (5) Sobel Filter:(
)( )
(
)( )
− − − = − − − = + = 1 0 1 2 0 2 1 0 1 , 1 2 1 0 0 0 1 2 1 where , , , , , ) , ( mask mask mask mask sobel SY SX j i R SY MF j i R SX MF j i G (6)In (5) and (6), the MF(·) function is the mask filter operation which is shown in (7).
( )
(
)
1 1(
) (
)
1 1 , , 1, 1 , , where is a 3 3 maskand ( , ) is the luminance value at ( , )
p q MF M R i j M p q R i p j q M by R i j i j =− =− = + + ⋅ + + − −
∑ ∑
(7)Morphological Gradient filter:
(
) (
)
log,
0 0 0
where 0 0 0
.
0 0 0
morpho icalG
R
B
R B
B
=
⊕
− Θ
=
(8)The operation ‘⊕ ’ and ‘Θ ’ denote the morphological operation of dilation and erosion respectively.
After obtaining the gradient value G, we first determine the edge threshold of this CMB as defined in (9).
( )
{
}
{
( )
}
1 2
1 2
max , min , ,
where and are set according to power mode.
threshold m G i j m G i j
m m
= ⋅ + ⋅
(9) Then, the algorithm uses the threshold value as a condition to pick the edge pixels and produces the edge mask by (10).
( )
01 , for G i, j( )
threshold EdgeMask i, j , otherwise ≥ = (10)Finally, the contend-based subsample mask (CSM) is generated from (11) and, therefore, the content-based subsample rate (CSR) is N2-to-(the number of 1's in CSM).
( )
( )
( )
. 1 , 0 for , , , 8: − ≤ ≤ = N j i j i EdgeMask OR j i SM j i CSM m (11) Since the higher the threshold value is, the less the edge pixels will be, the CSM is highly dependent on the threshold. Thus, the switching of power mode can be done by adjusting the threshold parameters m1 and m2.IV. THE VARIO-POWER ARCHITECTURE
According to the content-based subsample algorithm, we present a semi-systolic architecture which is based on the architecture proposed by Hsieh and Lin [4]. The vario-power architecture shown in Fig. 3 contains an edge-extraction unit (EXU), an array of processing elements (PEs), a parallel adder tree (PAT), a shift register array (SRA), and a motion-vector selector (MVS). Given the power consumption mode, the EXU extracts high frequency pixels (or edge pixels) from the current macro-block (CMB) and generates 0-1 content-based subsample masks (CSM) for the PE array to disable or enable processing elements (PEs). As shown in Fig. 4, the structure of PE array, which is used to accumulate the absolute differences of pixels column by column while the parallel adder tree sum up all the results to generate the subsample sum of absolute difference (SSAD). Finally, The MVS performs compare-and-select operation to compare-and-select the best motion vector which has a minimum SSAD.
1 − N uv PS 1 uv PS 0 uv PS
Parallel Adder Tree (PAT) Motion-Vector Selector (MVS) MV PEs array Shift Register Array (SRA) CMB RMB Edge-Extraction Unit (EXU) CSM Power mode Fig. 3. The system block diagram of the content-based subsample algorithm. SR SR 1 − N uv PS 2 uv PS 1 uv PS 0 2p−2 uv PS PE (N-1,N-1) SR SR To Paralle Adder Tree
CMB data N N N−1 PE (N-1,2) PE (N-1,1) PE (N-1,0) PE (1,0) PE (1,1) PE (1,2) PE (1,N-1) PE (0,N-1) PE (0,2) PE (0,1) PE (0,0) CSM RMB data SRA
Fig. 4. The architecture of PE array and shift register array.
to PE(i+1,j)
from PE(i-1,j) from PE(i,j-1) from PE(i,j+1) ∑− = 1 i 1 k j) AD(k, ∑ = i 1 k j) AD(k, reg breg reg reg CMB CSM b a− Adder breg RMB reg mux enable control 8 8 1 1 8 8
Fig. 5. The PE structure for the vario-power architecture.
delay line CMB delay line D D D D absGradient x8 _ + bottom boundary top boundary right boundary left boundary N pixels
Fig. 6. The architecture to implement the high-pass gradient filter.
Gradient max D min D cmp edge pattern m2 m1 Controller OR regular subsample pattern CSM power mode N2 delay line
Fig. 7. The architecture of the CSM generator. Since the adder operations which PE achieves dominant
significant power consumption in the system, the proposed architecture driven by the content-based subsample algorithm can disable some processing elements to save the switch activity of PE; that is, it can save the power consumption of the system. By performing the edge extraction first, a threshold was then set as the criterion of how many processing elements will be turn-off. Figure 5 shows the structure of the Processing Element and explains how the CSM disables or enables the PE. The absolute difference (AD) unit, which is denoted as |a-b|, calculates the absolute difference of CMB and RMB pixels. Then the adder unit accumulates the absolute difference value with the partial sum from the previous PE and conveys the results to the next PE in the same column. In order to reduce the switch activity, the PE receives the CSM signals from the EXU to disable or enable the blocking registers, which is abbreviated as ‘breg’ in Fig. 5, to decide the PE is active or inactive. When the blocking registers are enabled, the data paths of AD unit and the adder unit remains still, that is, the switch activity of this inactive PE is reduced. Thus, the power consumption can be saved.
The edge-extraction unit contains two main blocks which are gradient filter and CSM generator. The implementation of
gradient filter is based on one of the (5), (6) and (8). Figure 6, for instance, is the structure of the implementation for the high-pass gradient filter. The multiplexers are used to prevent the boundary error for border pixels of the CMB. The black-dot in each multiplexer indicates the switching path when the filter is processing a border pixel. The CSM generator, whose structure is illustrated in Fig. 7, figures out the maximum and minimum of the gradient value in the macro-block and then determines the threshold value according to the power mode as shown in (9). Finally, it generates the CSM by OR-merging the regular subsample pattern and the edge pattern.
The execution of the vario-power architecture has five phases: initial CMB phase, filtering phase, edge-determination phase, initial RMB phase, and SSAD calculation phase. The initial CMB phase is for loading the CMB data into PE array and the initial RMB phase is for filling up PE array in full with RMB data to start the SSAD calculation. Figure 8 illustrates the timing of data flow. Since the execution of edge-extraction
Filter phase Edge-determination phase Edge-extraction
Gradient filter operation
Determine the threshold according to the power mode.
1. Generate the CSM 2. Shift the CSM to PEs Vario-power motion estimation of a macro-block
Calculate SAD Phase Initial RMB phase
CMB
RMB CMB InitialCMB
phase
1. Shift the RMB data to PEs array. 2. Accumulate the SAD of each searching step.
Shift the CMB to PEs array
Fig. 8. The data flow of the vario-power architecture.
3 4 5 6 7 8 9 10 11 12 13 x 106 47.98 48 48.02 48.04 48.06 48.08 48.1 48.12 48.14 news
power consumption (εadder)
PS N R (d B ) + : General subsample * : Morphological context-based ♦ : HPF context-based o : Sobel context-based
Fig. 9. The PSNR vs. power consumption of the News clip.
3 4 5 6 7 8 9 10 11 12 13 x 106 40.2 40.25 40.3 40.35 40.4 40.45 weather
power consumption (εadder)
PS N R (d B ) + : General subsample * : Morphological context-based ♦ : HPF context-based o : Sobel context-based
Fig. 10. The PSNR vs. power consumption of the Weather clip. unit, which includes filtering phase and edge-determination
phase, is parallel to the initial RMB phase, the behavior of the proposed architecture is the same as the architecture without vario-power function proposed by Hsieh and Lin [4].
V. ESTIMATION OF POWER CONSUMPTION
From (12), the power consumption of digital VLSI is in proportion to the switch activity, f ⋅γ(0↔ . 1)
2 (0 1),
where (0 1) is the switching rate of the gate.
gate gate DD
P f C V γ
γ
= ⋅ ⋅ ⋅ ↔
↔ (12)
Because the addition is the majority of the motion estimation architecture, by referring to [11], this paper uses the number of equivalent additions, denoted as
ε
adder, as the power measure unit to estimate the power consumption. As per Fig. 5, the calculation of an absolute difference nearly requires2
ε
adderand each PE consumes 3ε
adder in each iteration. Whenthe PE array operates at the content-based subsample rate of
s
R
, it requires 1 2( )
2 2 3s adder
R− ⋅N ⋅ p ⋅ ε . Since the calculation of
PAT requires
(
) ( )
2 1 2 adderN− ⋅ p ⋅ε , the power consumption of calculating SSADs for all RMBs in searching area is
(
)
1 2 2 2
12R N ps− εadder+4 N−1 pεadder.
As regard to the EXU, three gradient filters which are mentioned in this paper consume 6 2
adder
N ε ,9 2
adder
N ε and
2
8N εadder ,respectively, and the edge-determination consumes
2
3N εadder. So the power consumption of the content-based subsample algorithm (PCSA) can be expressed as (13).
(
)
{
}
1 2 2 2 2 12 4 1 , where 9,12,11 .CSA s adder adder adder P R N p N p N ε ε α ε α − ≅ + − + ∈ (13)
From (13), we can learn that the power overhead of EXU is a little. For the worst case, when the subsample rate is 4-to-1 and the gradient filter is Sobel-type, the power overhead is only 0.36% for the motion estimation with N=16 and p=32.
VI. SIMULATION RESULTS
Figure 9 and 10 demonstrate the simulation results of two 352-by-288 MPEG clips for N=16 and p=32. The dashed lines are the results of the general subsample algorithm and the subsample rates at the bullets are (4:1), (8:3), (2:1), (8:5), (4:3), (8:7), and (1:1), respectively from left to right. The solid lines are the results of the content-based subsample algorithm with three gradient filters and the subsample rate is from (4:1) to (1:1). The threshold parameters, (m1, m2) pairs, at the bullets
on solid lines are (1,0), (0.75,0.25), (0.5,0.5), (0.4,0.6), (0.3,0.7), (0.2,0.8), (0.1,0.9), and (0,1), from left to right respectively. As the results, the power consumption can be significantly reduced while the quality degradation is little and the power mode can be dynamically switched by simply changing the threshold parameters.
VII. CONCLUSION
We proposed the vario-power architecture based on a novel content-based subsample algorithm. The vario-power architecture provides the real-time capability for the switching of power consumption mode while the quality degrades a little. In the proposed architecture, the edge extraction unit plays a key role to dynamically adjust the power consumption mode and its power overhead can be neglected. As shown in the simulation results, the proposed algorithm successfully improves the compression quality of the general subsample algorithm and switches the power consumption mode by the content dependent technique.
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Hsien-Wen Cheng received the B.S. degree in Control
Engineering from National Chiao Tung University, Hsinchu, Taiwan, R.O.C. in 1992. He joined the AVerMedia Technologies Inc. from 1994 to 2001.
He is currently working toward the Ph.D degree in the Electrical and Control Engineer, National Chiao Tung University. His research interests are video/image compression, motion estimation, VLSI architecture and digital signal processing.
Lan-Rong Dung received a BSEE and the Best Student
Award from Feng Chia University, Taiwan, in 1988, an MS in electronics engineering from National Chiao Tung University, Taiwan, in 1990, and Ph.D. in electrical and computer engineering from Georgia Institute of Technology, in 1997.
From 1997 to 1999 he was with Rockwell Science Center, Thousand Oaks, CA, as a Member of the Technical Staff. He joined the faculty of National Chiao Tung University, Taiwan in 1999 where he is currently an assistant professor in the Department of Electrical and Control Engineering. He received the VHDL International Outstanding Dissertation Award celebrating in Washington DC in October, 1997. His current research interests include VLSI design, digital signal processing, hardware-software codesign, and System-on-Chip architecture. He is a member of Computer and Signal Processing societies of the IEEE.
