A Low-Power and High-Precision Spread
Spectrum Clock Generator for Serial Advanced
Technology Attachment Applications Using
Two-Point Modulation
Yao-Huang Kao, Member, IEEE, and Yi-Bin Hsieh, Member, IEEE
Abstract—A new technique utilizing two-point (TP) modulation
for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital Σ∆ modulator, and the voltage-controlled os-cillator is modulated analogically. With this technique, the modu-lation bandwidth is enhanced in order that the modumodu-lation profile accuracy and jitter performance caused by the Σ∆ modulator can be improved at the same time. The order of the Σ∆ modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies spec-ifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18-µm CMOS process. The size of the chip area is 0.44× 0.48 mm2. The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.
Index Terms—Frequency modulation, phase-locked loops
(PLLs), sigma–delta modulation, spread spectrum clock genera-tor (SSCG).
I. INTRODUCTION
S
ERIAL interfaces are widely used for high data rate trans-mission. For example, serial advanced technology attach-ment (SATA), which is the standard for high-speed storage devices such as hard disk drives and compact disk (CD)/digital versatile disk (DVD), can transmit data at rates up to 1.5 or 3 Gb/s for generation I and II, respectively [1]. High-speed clocks often cause electromagnetic interference (EMI). There-fore, the spread spectrum clock generators (SSCGs) are em-ployed in SATA to reduce EMI levels. Typical specifications in SATA are the 5000 ppm down-modulation ratio, modulating fre-quency within 30–33 kHz, and EMI suppression of at least 7 dB. In order to realize such a fine modulation ratio, fractional-N phase-locked loops (PLLs) with a Σ∆ modulator are usually used [2]–[7]. This technique has the advantages of fully digital control and fine resolution. The modulator is normally drivenManuscript received April 27, 2008; revised November 2, 2008. First published March 16, 2009; current version published May 15, 2009. This work was supported by the National Chip Implementation Center and National Science Council, Taiwan, R.O.C.
Y.-H. Kao is with the Department of Communication Engineering, Chung-Hua University, Hsin-Chu 300, Taiwan (e-mail: yhkao@chu.edu.tw).
Y.-B. Hsieh is with the Institute of Communication Engineering, Na-tional Chiao-Tung University, Hsin-Chu 30050, Taiwan (e-mail: yibin.cm93g@ nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TEMC.2008.2012115
by a triangular waveform. A nonlinear profile, known as the “Hershey-Kiss” profile, has been suggested for better EMI per-formance [8]. The nonlinear function of the “Hershey-Kiss” profile makes it more expensive due to large area and power consumption. Therefore, triangular waveforms are still used due to their simple implementation [4], [5]. Another important issue is the choice of loop bandwidth of PLL. The loop bandwidth has tradeoffs between the modulation profile and the jitter caused by the Σ∆ modulator. The profile is distorted and the effect of EMI suppression is degraded if the loop bandwidth is not wide enough. Therefore, the wide bandwidth leads to a request for a third-order Σ∆ modulator in order to suppress the in-band fractional spurious. A design of a third-order Σ∆ modulator with a third-order loop filter and a 300-kHz loop bandwidth to improve the jitter and the modulation profile was presented in [4]. However, the third-order Σ∆ modulator has high power consumption and occupies a large area. Recently, the method of two-point (TP) modulation, which has the divider and the voltage-controlled oscillator (VCO) modulated at the same time, was presented to enhance the bandwidth and improve EMI per-formance [9]. Here, a new version of SSCG with TP modulation is presented for the SATA application [10]. The jitter caused by the Σ∆ modulator can be reduced by a small loop bandwidth, while the modulation profile can still be maintained. Only a second-order Σ∆ modulator, as well as a second-order loop filter, is adopted. The chip area and power consumption are im-proved. In addition, aided with a dual-path loop filter (DL), the proposed TPDL-SSCG can be fully integrated.
The organization of the paper is as follows. Section II de-scribes the proposed TPDL-SSCG including the linear model analysis, analysis of the noise power spectral density (PSD) from the Σ∆ modulator and VCO, the proposed digital modulation path, the proposed analog modulation path, and simulation re-sults. Main circuits are briefly described in Section III. The measurement results are demonstrated in Section IV. Conclu-sions are given in Section V.
II. PROPOSEDTPDL-SSCG
It is well known that the transfer function of the phase re-sponse from the feedback divider to VCO output is a low-pass function. On the contrary, the function from VCO input to VCO output is a high-pass function. A wideband response can be achieved if the loop is excited through these two points. The block diagram of the proposed SSCG is shown in Fig. 1 with a phase frequency detector (PFD), a DL containing
Fig. 1. Block diagram of the proposed TPDL-SSCG.
Fig. 2. Linear model of the proposed TPDL-SSCG.
CP1, CP2, R1, C1, and C2, a VCO, a prescaler, a 5-bit
pro-grammable counter (PGC), a digital Σ∆ modulator, a modula-tion profile generator, and a digital-to-analog converter (DAC). Compared to the conventional one, this circuit incorporates two extra circuits of charge pump CP2and DAC. The staircase
trian-gular waveform is digitally generated by the profile generator. The frequency modulation is obtained from two inputs Vx and
Vy, where Vxis the input of the multimodulus divider and Vy is
the input of the VCO. The all-pass behavior is obtained as long as the modulation coefficients along the two paths are matched. The modulation path from Vx to the output is referred as the
digital modulation path while the modulation path from Vy to
the output is referred as the analog modulation path.
A. Linear Model Analysis
Rather than finding out the phase relationship, here, the quency relationship in s-domain is adopted to study the fre-quency modulation in SSCG. The linear model is shown in Fig. 2, where ∆ωcis the output frequency deviation, ∆ωmis the
input modulating frequency deviation, and Gm is the gain
mis-match factor stand for compensation between two paths. Two noise sources are taken into consideration: modulator quanti-zation noise Φ∆ Σ and VCO phase noise Φv n. Here, only the
gain mismatch is taken into consideration because the delay mismatch is assumed to be negligible due to the proposed DAC. To see the advantage of TP modulation, we first examine the results with only one-point modulation Vx. For simplicity, the
noise sources are ignored. The transfer function from ∆ωm to
low-pass behavior when F (s) is taken into account. A triangular wave is given as a waveform sweeping frequency from low to high in one-half of period and from high to low in the other half of period. The variable ∆ωccan be given as
∆ωc=
KVC OKdF (s)
N s + KVC OKdF (s)
Mram p
s2 (2)
as a frequency ramp with a slope of Mram p is applied, i.e.,
s2∆ωm = Mram p. Equation (2) can be rewritten as
∆ωc= Ks + Kω2 s2+ Ks + Kω 2 Mram p s2 (3)
with K = Kd × KVC O × R1/N , and is approximately equal to
the loop bandwidth of PLL and ω2 = 1/R1C1K2is the zero of
the loop filter. Here, the C2 effect is neglected. The frequency
error defined by ∆ωerr= ∆ωm− ∆ωccan be found by
∆ωerr =
Mram p
s2+ Ks + Kω 2
. (4)
Using inverse Laplace transform and under ω2 K, the
tran-sient response is obtained ∆ωerr(t) = Mram p K− ω2 e−ω2t− e−K t ≈Mram p K e−ω2t− e−K t. (5)
The maximum frequency error ∆ωerrcan be found by (5) as
max (∆ωerr)∝
Mram p
K . (6)
Equations (5) and (6) indicate how the low-pass behavior causes frequency errors and distorts the output. It is clear that ∆ωerr = 0 only if K =∞, i.e., the loop bandwidth is infinitely
large.
With TP modulation activated, by the superposition principle, the closed-loop transfer function of Fig. 2 can be derived as
∆ωc ∆ωm = T (s) + (1− T (s)) × Gm (7) with T (s) = KVC OKdF (s) N s + KVC OKdF (s) . (8)
The first term in the right-hand side is the same as (1). The second term appears as a high pass and can be treated as a complementary part if Gm = 1. Therefore, from (7), ∆ωc is
equal to ∆ωm if Gm = 1. This means that the output is all pass
Fig. 3. Simulation results of frequency deviation output with a triangular modulation profile.
A triangular waveform ∆ωm(t) with a mean of zero can be
written as ∆ωm(t) = 2∆fam p(2fmt− 0.5) , for n 2fm ≤ t < 2n + 1 2fm = 2∆fam p(1.5− 2fmt) , for 2n + 1 2fm ≤ t < n + 1 fm (9) where ∆fam p is the amplitude of the waveform and n is an
arbitrary integer number. The frequency deviation outputs for both one-point modulation and the proposed scheme, with the triangular modulation profile input from (9), are shown in Fig. 3. Here, Gm = 1, the modulating frequency is 31.25 kHz, and the
target frequency deviation is 7.5 MHz, which is the same as SATA specification. The dashed-dotted solid line is the ideal all pass, the solid line is from (1), the FN-SSCG case, and the line with a circle mark is the output from (7), the TPDL-SSCG case. The solid line cannot track the input frequency change well due to insufficient loop bandwidth. On the contrary, the line with circle mark can always track the input so that the output error is eliminated. Thus, the proposed scheme can track the modulation waveform very well and is independent of the PLL bandwidth and other loop parameters as long as the paths are matched.
B. Analysis of Noise PSD From theΣ∆ Modulator
and the VCO
The PSD is closely related to the order of the Σ∆ modulator and loop bandwidth. It is already known that a high-order Σ∆ modulator is used to reduce the fractional spur within the loop bandwidth. In this design, only a second-order Σ∆ modulator is chosen to save area and power, while maintaining jitter and EMI performance. To see the interrelation between the order of the Σ∆ modulator and PLL bandwidth, the output phase noise originating from the Σ∆ modulator and the VCO is investigated. The noise PSDs of the phase SΦ(f ) can be expressed as
SΦ(f ) = SΦ VC O(f ) + SΦ ∆ Σ(f ) (10)
Fig. 4. Phase noise simulation for FN-SSCG and TPDL-SSCG.
where SΦ VC O(f ) and SΦ Σ ∆(f ) are the noise of the VCO and
the Σ∆ modulator, respectively. SΦ ∆ Σ(f ) [16] can be found as
SΦ ∆ Σ(f ) = (2π)2 12fbk 2 sin πf fbk 2(m−1) |T (s)s= j 2π f|2 (11) where m is the order of the modulator and fbkis the operational
frequency of the modulator. SΦ VC O(f ) can be easily derived as
SΦ VC O(f ) = SΦ v n|1 − T (s)s= j 2π f|2 (12)
where SΦ v n is the stand-alone VCO phase noise.
In general, the loop bandwidth is much less than the phase comparison frequency fbkat the phase detector to avoid the spur.
From (11), it is realized that the shape of output PSD, caused by the Σ∆ modulator, is increasing inside the PLL bandwidth with f2(m−1) and decreasing outside the PLL bandwidth. In other words, the smaller the PLL bandwidth, the lower the jitter caused by the Σ∆ modulator. However, a large PLL bandwidth is needed to pass faithfully the modulation profile. Otherwise, the spectrum appeared at the output of PLL will be distorted, the modulation ratio will be incorrect, and EMI performance will be degraded. Thus, the PLL bandwidth is a tradeoff be-tween the modulation profile and the jitter performance. In the conventional situation [4], the bandwidth is approximately ten times the modulating frequency to obtain good performance. The in-band fractional spur is suppressed by a third-order Σ∆ modulator to minimize the phase noise and jitter. In addition, a third-order loop filter is needed to reduce the out-of-band phase noise and jitter caused by the comparison clock. In other words, it requires higher power consumption and more area. However, due to the all-pass nature in the proposed method, the PLL bandwidth can be shrunk for jitter without the modulation profile distortion.
The PSDs for the conventional fractional-N SSCG (FN-SSCG) and the TP SSCG (TPDL-SSCG) in nonspread spectrum mode are illustrated in Fig. 4. Only the VCO and the modulator quantization noise are taken into account. The VCO phase noise is measured as−89 dBc/Hz at the offset frequency of 1 MHz with the shape of f−2. Other simulation parameters
are listed in Table I. Two different cases with loop bandwidths of 100 and 300 kHz are studied. A third pole of 4.5 MHz is needed for the FN-SSCG to further filter the quantization noise of the third-order modulator. The center frequency is set at 1500 MHz, the modulation ratio is−0.5%, and the modulating frequency is set at 31.25 kHz. The solid and dashed lines represent the total phase noise for the FN-SSCG with a 300-kHz loop band-width and TPDL-SSCG with a 100-kHz loop bandband-width, respec-tively. The contributions from the VCO are denoted by circle and plus marks in different cases. The phase noise from the Σ∆ modulator is denoted by diamond and square marks. Although the in-band phase noise in the TPDL-SSCG with a second-order Σ∆ modulator is larger than the case in the FN-SSCG with a third-order Σ∆ modulator, the TPDL-SSCG still has enough performance in terms of EMI suppression, modulation profile linearity, and jitter through the following analysis and measurements.
The chip areas for the second- and third-order multi-stage noise shaping (MASH) Σ∆ modulators are evaluated as 3920 and 4887, in units of gate counts, respectively. The power consumption using the Taiwan Semiconductor Man-ufacturing Company (TSMC) 0.18 µm process is 1.40 and 2.00 mW, respectively. The area is approximately 20% off in dig-ital area and approximately 5% off in whole area and the power is approximately 4% off in whole power consumptions when using the second-order Σ∆ modulator. The 4%–5% difference is still important because the power and area of the proposed SSCG are only 15.3 mW and 0.21 mm2, respectively. Hence, in this paper, a second-order Σ∆ modulator and a 100-kHz loop bandwidth, with a second-order loop filter, are designed for saving power and area.
C. Proposed Digital Modulation Path
The digital modulation path consists of a fractional-N-based PLL and the modulation profile generator. The block diagram of the proposed profile generator and Σ∆ modulator is shown in Fig. 5. The input range of the Σ∆ modulator must fulfill the requirement of 0 to−5000 ppm modulation ratio. In order to lower the speed requirement of the PGC from 1.5 GHz to 375 MHz, a divided-by-4 prescaler, implemented by the true single-phase clock (TSPC) logic, is ahead of the PGC. Ac-cordingly, the fractional number is varied between 0.925 and 1. A MASH-type Σ∆ modulator has an input range of less than 1 and cannot be used in this application. To eradicate this issue, a new version of the MASH-1-1 Σ∆ modulator, with extended input range, is used to overcome the overflow prob-lem in the modulator [13]. Stage 1 has two carry bits while stage 2 has only one carry bit. The two-bit carry outputs cause
Fig. 5. Block diagram of the proposed profile generator and Σ∆ modulator.
inputs larger than, or equal to, 1 to quickly pass the integer part of the input to the output, and will not saturate the fol-lowing stages. The advantages of this design are unconditional stability and small area similar to the conventional MASH-1-1 Σ∆ modulator. In addition, this circuit has approximately three times the input range of the conventional MASH-1-1 Σ∆ modulator.
The profile generator consists of an up/down counter and a first-order Σ∆ modulator [14]. In order to utilize the simple architecture of the MASH-type Σ∆ modulator, which is com-posed of adders and some simple logic circuits and whose output of each stag is the carry output of the adders, the bit number B of the adder should be power of 2. In addition, the modulating frequency must be within 30–33 kHz. With the aforementioned two constraints on the modulation profile generator, the operat-ing frequency of the modulation profile generator may not the same as Fbk, the input clock of the modulator. The following
analysis will show the reason. Assuming the actual operating frequency of the up/down counter to be Fcnt, which is
deter-mined from the modulation ratio δ, the modulating frequency
fm, and the bit number of the MASH-1-1 Σ∆ modulator (B),
it can be described by fcnt= fc 4fbk × 2 × δ × 2B× f sig. (13)
Therefore, an extra first-order Σ∆ modulator is added to gen-erate the additional enable signal fen to lower the operation
frequency of the up/down counter, as shown in Fig. 5. The re-lationship between fcnt and fen is fcnt= fen and fbk. In this
study, fc is 1.5 GHz, fm is 31.25 kHz, and δ is 0.5% to meet
SATA specifications. In addition, B = 12 and fbk= 25 MHz.
One can calculate that fcnt= 19.2 MHz.
Unlike [4], the proposed model does not need some level shifters and comparators to increase the area and power con-sumption, nor does it require complicated Σ∆ modulator. More-over, the loop bandwidth can be lowered to minimize the jitter contribution from the modulator through the following analysis.
D. Proposed Analog Modulation Path
The analog modulation path is composed of the DAC and the PLL, which is the same as the digital modulation path. The function of the DAC is redrawn in Fig. 6(a). It consists of a digital slicer, charge pump CP3, and capacitance C1. An
analog triangular waveform across C1is obtained from a digital
Fig. 6. (a) Proposed DAC. (b) Timing diagram for the proposed DAC.
first sliced into a square waveform Fm 1, and then it charges the
capacitor C1to achieve digital-to-analog conversion. The digital
transition is smoothed out to reduce VCO interference. The analog modulation path, whose response is high-passed, serves as the compensation for the digital modulation path, whose response is low-passed. Unlike the VCO directly modulated SSCGs such as [21] and [24], the loop bandwidth does not need much smaller than the modulation frequency and the required capacitor in the loop filter can be much smaller. As compared to a traditional one [11], no high-resolution DAC or reconstruction filter is needed. Therefore, the power consumption and the chip area can be reduced.
The gain and delay mismatch is known to degrade the perfor-mance [11]. The following approach is utilized to eliminate this nonideality from the delay mismatch. Referring to the timing diagram in Fig. 6(b), Fm 1and Vy are two clocks delayed with
respect to Fm in order to synchronize the delay from Fm to the
output of the Σ∆ modulator Vx. Because the digital slicer, the
profile generator, and the Σ∆ modulator use the same clock Fbk,
which is the output frequency of the PGC, the delay mismatch can be avoided.
The relation between controlled voltage Vc and the current
Ip3 of CP3 can be written as Vc Ip3 ≈ 1 s (C1+ C2) (14) under the condition fm 1/(2πR1C2). The loading effects
of CP1 and CP2 are neglected due to high output impedances.
Accordingly, the smooth triangular waveform is obtained as Ip3
is a square waveform. Here, both C1 and C2 with one terminal
grounded are implemented by the accumulation MOS capacitor to save area. Both have good distortion performance when the gate-source bias voltage is equal to, or large than, 1 V [12]. The modulation ratio δ≡ ∆fc/fc as a function of Ip3 is predicted
as
δ = Ip3KVC O
2 (C1+ C2) fmfc
(15)
Fig. 7. Simplified block diagram of the DL.
where fcis the carrier frequency, ∆fc is the peak deviation of
the carrier frequency, fm is the modulating frequency of the
triangle wave, and KVC O is the conversion gain of VCO.
From (15), since C1(2)is varied within 5% and Ip3 is varied
within 15% in the typical CMOS process, the gain mismatch is mainly contributed by KVC O. Therefore, the VCO with low
sensitivity to VCO gain is needed. In this paper, KVC Ois varied
about±30% over process, voltage, and temperature variations. It means Gmis changed from about 0.7 to 1.3. From the
follow-ing simulation results (Section II-E), the gain mismatch impact on modulation ratio will be varied about 0.008% and the gain mismatch impact on EMI performance is about 0.23 dB. More-over, the VCO calibration technique in [22] can be used to further improve the performance.
To save the capacitor area in the loop filter, a modified DL is utilized [7]. The paths of pumping currents are shown in Fig. 7, in which Ip1is the current of CP1 and Ip2is the current of CP2.
Thus, Ip2 = K1Ip1. The loading effect of CP3is neglected. The
loop filter transfer function can be derived as
F (s) = Vc Ip1
= [R1C1/(C1+ C2)] (s + (1/R1K2C1))
s (1 + sR1(C1//C2))
(16) where K2 = 1/(1− K1). The zero is at 1/(K2C1) R1. From
(16), the effect of capacitance multiplication is high when K1is
close to 1. It means that the Ip1 and Ip2are close to each other.
However, the mismatch between Ip1 and Ip2 depends on the
area. Therefore, a tradeoff should be made. Here, K1 = 0.75
and K2 = 4 such that the size of capacitance C1can be reduced
by four times. Compared to the path filter in [24], the dual-path filter adopted here does not need a unity-gain amplifier; therefore, the phase noise is smaller.
E. Simulation Results
To compare the performance between the FN-SSCG and the TPDL-SSCG, the following simulations are made. The same pa-rameters listed in Table I are used. The output frequency swings are shown in Fig. 8. Four different modulation ratios of 0.545%, 0.523%, 0.506%, and 0.510% for the FN-SSCG with a 100-kHz BW denoted by curve (a), the FN-SSCG with a 300-kHz BW denoted by curve (b), the TPDL-SSCG with a 100-kHz BW denoted by curve (c), and the TPDL-SSCG with a 300-kHz BW denoted by curve (d) are obtained, respectively. The correspond-ing spectra results with the Σ∆ modulator noise are shown in Fig. 9. The simulated EMI reductions with Σ∆ modulator noise are 20.35, 19.69, 20.47, and 19.21 dB for curves (a), (b), (c), and (d) shown in Fig. 8, respectively. The simulation results are sum-marized in Table II. It is known that the larger the modulation
Fig. 8. Simulation results for the FN-SSCG and the TPDL-SSCG under dif-ferent loop bandwidths.
Fig. 9. Spectrum simulation results with the Σ∆ modulator noise for the FN-SSCG and the TPDL-SSCG under different loop bandwidths.
TABLE II SSCG SIMULATIONSUMMARY
ratio, the better the EMI performance if the frequency to the modulation profile keeps constant [23]. To see the efficiency of EMI attenuation performance, the EMI reduction and its mod-ulation ratio need to be considered simultaneously. One more parameter, the normalized EMI attenuation (AdB,norm), is
de-fined as
AdB,norm = 10 log10
10Ad B/10
δ% (17)
case of the FN-SSCG with a 100-kHz BW, meaning that it is not a good triangular waveform. The case of the FN-SSCG with a 300-kHz BW has better performance in terms of the modulation ratio (0.523%) and normalized EMI attenuation (37.65 dB/%) compared to one with a 100-kHz BW. However, it is clearly indicated that the case of the TPDL-SSCG with a 100-kHz BW has not only a more accurate modulation ratio (0.506%), but also better normalized EMI attenuation (40.45 dB/%) with re-spect to the two cases of the FN-SSCG because the case of the TPDL-SSCG with a 100-kHz BW has smaller Σ∆ modulator noise than the case of the FN-SSCG with a 300-kHz BW and utilizes the technique of the TP modulation to faithfully pass the modulation profile. This is also indicated from the spectrum shape that no obvious peaks appeared at the two ends of the spectrum. In addition, there is a 0.023% difference in modula-tion ratios for PLL bandwidths changing from 100 to 300 kHz for the FN-SSCG, while there is only 0.003% difference in modulation ratios for the TPDL-SSCG. The slight difference between curves (c) and (d) in Fig. 9 is due to the quantization noise influence. It implies that the effect of bandwidth is of little importance in the proposed modulation.
More effects are illustrated in Figs. 8 and 9, which show that the bigger loop bandwidth and worse jitter both appeared at the output. The cases with a 300-kHz BW show the bigger instantaneous frequency fluctuations from Fig. 8, and the higher noise level from Fig. 9, with respect to the cases with a 100-kHz BW in both architectures. This confirms the results in (11). The proposed TPDL-SSCG has the advantage of low distortion, so that the modulation profile is more like a triangular wave, and can improve the linearity of the modulation profile and the EMI performance at the same time.
In order to deeply investigate the jitter effect on the EMI suppression level, the spectra simulation results without the Σ∆ modulator noise for FN-SSCG and TPDL-SSCG under the same case as in Figs. 8 and 9 are drawn in Fig. 10. The simulation results are also summarized in Table II. The simulated spectra without the Σ∆ modulator noise are 20.32, 20.95, 20.76, and 20.70 dB for the FN-SSCG with a 100-kHz BW, the FN-SSCG with a 300-kHz BW, the TPDL-SSCG with a 100-kHz BW, and the TPDL-SSCG with a 300-kHz BW, respectively. It shows a 1.26 dB (=20.95−19.69) EMI degradation for the case of FN-SSCG with a 300-kHz BW when the Σ∆ modulator noise is taken into consideration, while it is 1.49 dB (=20.70−20.70) for the case of TPDL-SSCG with a 300-kHz BW. It is clearly to seen that there is only 0.29 dB (=20.76−20.76) impact on the EMI performance for the case of TPDL-SSCG with a 100-kHz BW. Therefore, the jitter introduced by the modulator has a deteriorating effect on the EMI suppression levels.
The impacts of the gain mismatch on modulation ratios and the EMI performance are verified. The cases for Gm = 0.6,
Fig. 10. Spectrum simulation results without the Σ∆ modulator noise for the FN-SSCG and the TPDL-SSCG under different loop bandwidths.
Fig. 11. Simulation results for gain mismatch impact on modulation ratio for the TPDL-SSCG.
bandwidths. The impacts on modulation ratios are shown in Fig. 11(a). When the PLL bandwidth is smaller than 100 kHz, the modulation ratio is very sensitive to the gain mismatch between the two points. When the PLL bandwidth is larger than 100 kHz, the modulation ratio variation is small. The impacts on the EMI performance are shown in Fig. 11(b). When Gm = 1.0
or Gm = 1.4, the higher the PLL bandwidth, the worse the EMI
performance is. When Gm = 0.6, the EMI reduction
perfor-mance is less related to the PLL bandwidth. In addition, the EMI variation is sensitive to the gain mismatch when the PLL bandwidth is smaller than 100 kHz. The reason for gain mis-match effects on the proposed SSCG is described later. One can rewrite (8) as
∆ωout= T (s)∆ωsig+ (1− T (s)) × Gm∆ωsig. (18)
The first term in (18) is contributed by the modulation of di-vider and the second term is contributed by the modulation of the VCO. When the loop bandwidth is quite low, the output is dominated by the second term in (18), meaning that the modu-lation ratio is sensitive to gain mismatch. In other words, when the loop bandwidth is quite high, the output is dominated by the
Fig. 12. VCO circuits.
Fig. 13. Die photograph of the proposed TPDL-SSCG.
first term in (18), meaning that the modulation ratio is less sensi-tive to gain mismatch. But, it is noted from the aforementioned analysis that the EMI performance will be degraded once the loop width is large due to the quantization noise of the modula-tor. Therefore, if the gain mismatch is small, one can lower the bandwidth to achieve the desired performance according to the aforementioned analysis. If the gain mismatch is high, or more than 0.4, one needs to tradeoff the loop bandwidth with the per-formance. Thus, in order to reduce the effect of gain mismatch, one can choose an appropriate loop bandwidth to let the first and the third Fourier frequencies of the triangular waveform to be passed through the divider path and to let the fifth and higher Fourier frequencies to be passed through the VCO path. This approach makes the output waveform dominated by the divider modulation path and aided by the VCO modulation path. A rule of thumb of three times the modulating frequency can be the target loop bandwidth. Thus, the 100-kHz loop bandwidth is adopted in this paper.
In short, the advantages of the proposed TPDL-SSCG are remarkable. First, a lower order Σ∆ modulator can be used for lower power consumption. Second, the lower order loop filter
Fig. 14. Measured spectra. (a) Nonspread spectrum mode. (b) Conventional FN-SSCG. (c) Proposed TPDL-SSCG. Measurement condition: RBW = 100 kHz, video BW (VBW) = 100 kHz, and peak-hold mode.
Fig. 15. Measured spectra for the TPDL-SSCG (a) with SSC-OFF(b) with SSC-ON. Measurement condition: RBW = 10 kHz, VBW = 10 kHz, and peak-hold mode.
Fig. 16. Measured modulation profile in time domain.
can be used for a smaller chip area. Third, the linear modula-tion profile and small Σ∆ modulator noise can be optimized simultaneously.
III. CIRCUITDESCRIPTIONS
Fig. 12 shows the schematic of VCO used in this paper [17], [18]. It is composed of four current starved inverters (denoted by X) as delay cells, two pairs of cross-coupled current starved
inverters (denoted by Y), and a voltage to current converter (V2I). The detailed circuit of the V2I is shown in Fig. 12(b), and the inverters of X and Y are shown in Fig. 12(c). This simple architecture is selected for its large signal swing, which allows better phase noise performance and large tuning range. The cross-coupled inverters have two functions: one is to pro-vide negative impedance to mandate the phase delay in each inverter at 90◦ and the other is to allow the VCO to operate pseudodifferentially to obtain better power supply rejection ra-tio (PSRR). In other words, the VCO is a two-stage differential type. The size of inverter Y is suggested to be more than 0.5 times the size of inverter X to maintain oscillation [17]. Here, the factor is 0.7 times to allow a higher oscillation frequency than that of the three-stage single-ended ring oscillator [17] be-cause it has an additional coupling path from the cross-coupled inverters with reduced delay time. Therefore, the power con-sumption can be relaxed for a given frequency. Moreover, un-like a singled-ended ring oscillator, which produces a distorted triangular waveform output, this topology produces a sinusoidal output, and a more symmetrical waveform, to get better phase noise performance [19]. To further minimize the phase noise, a low VCO gain of 480 MHz/V is chosen to lower the phase noise due to the noise coupling to the VCO input node. The noise of the V2I is also a main contributor to the phase noise. Therefore, the size of the V2I is the same as that in inverter X to lower the up-conversion noise from the bias circuit. The measured phase noise at 1 MHz offset frequency is−89 dBc with a power consumption of 3 mA.
Fig. 17. Measured jitters for the TPDL-SSCG (a) with SSC-OFFand (b) with SSC-ON. TABLE III PERFORMANCESUMMARIES
IV. MEASUREMENTRESULTS
The proposed SSCG is designed and fabricated by the TSMC 0.18-µm CMOS process. The die photograph is shown in Fig. 13. The active area is 0.42× 0.48 mm2. The output spectra without spreading, with spreading, using the conventional FN-SSCG, and with spreading using the TPDL-SSCG are shown in Fig. 14(a)–(c), respectively. The resolution bandwidth (RBW) is set to 100 kHz to meet SATA specifications [1]. A second-order loop filter and a PLL bandwidth close to 100 kHz are chosen for both Fig. 14(b) and (c). The second-order extended range MASH Σ∆ modulator is adopted for both Fig. 14(b) and (c). In other words, the conventional FN-SSCG is obtained just by switching off the path of the VCO modulation. The EMI reduction is approximately 7.52 dB for the conventional FN-SSCG and is approximately 10.14 dB for the TPDL-SSCG. The proposed SSCG has 2.62-dB improvements in EMI reduc-tion. The concave shape of the modulation spectra in Fig. 14(b) for the FN-SSCG can be understood due to insufficient loop bandwidth to make the modulation profile more like a sinu-soidal waveform. The slightly concave shape of the modulation spectra in Fig. 14(c) for the TPDL-SSCG is due to the addition of the whole sideband harmonics (resulting from the modulation process) falling inside this RBW = 100 kHz even with the tri-angular modulation profile. Therefore, in order to compare with the simulation results, the RBW needs to be smaller than the modulating frequency [15]. Therefore, the spectra for the TPDL-SSCG, with SSCOFFandONusing 10-kHz RBW, are measured and shown in Fig. 15(a) and (b), respectively. The measured EMI reduction is 19.63 dB and is close to the simulation results of 20.47 dB. No peak appeared in Fig. 15(b), which indicates that the modulation profile is nearly a triangular waveform.
It is difficult to determine the real peak–peak modulation ratio and the shape of the triangular modulation in the frequency domain. Therefore, the time-domain modulation profile is verified in Fig. 16. The solid line and dashed line represent the profile of the proposed TPDL-SSCG and the profile of conven-tional FN-SSCG, respectively. The measured modulation ratios are 0.55% and 0.507% for the conventional FN-SSCG and the TPDL-SSCG, respectively. The measured modulation ratio of the TPDL-SSCG is very close to the simulation results, 0.506%, listed in Table II. The measured modulation profile for the conventional FN-SSCG looks like a distorted triangular wave-form due to the insufficient PLL bandwidth; therefore, the EMI performance is bad. The measured jitter, using a self-triggered method under different conditions, is shown in Fig. 17. The mea-sured rms jitter is 4.748 and 5.485 ps at SSC-OFFand SSC-ON, respectively. The measured peak-to-peak jitter is 30 and 35 ps at SSC-OFFand SSC-ON, respectively. Only a 0.737-ps rms jitter is increased when the TPDL-SSCG is active, which is very close to the theoretical estimation of 0.556 ps (=0.5%/1500 MHz/6). Therefore, the rms jitter caused by the nonideality of the circuits (mostly from the Σ∆ modulator) is only 0.181 ps. The power consumptions with and without an output buffer are 15.3 and 27 mW, respectively. The lower power consumption is achieved due to the low-power VCO and the low-order Σ∆ modulator. Table III summarizes the performance of the proposed TPDL-SSCG and compares with previous work. In Table III, the EMI reduction amounts are compared for the 100-kHz RBW. Note that the proposed TPDL-SSCG results in smaller area, lower power consumption, and better peak-to-peak jitter performance. The EMI performance is comparable to other works.
tegration is realized without using an external loop filter or a high-resolution DAC. The clock rate of 1.5 GHz with a down-modulation ratio of 0.5% is achieved. The jitter at SSC-ONis 5.485-ps rms and 35-ps peak-to-peak with only a 0.737-ps rms jitter attributed from spread spectrum clocking. The improve-ment in EMI reduction is better than 2.62 dB with respect to a conventional one-point implementation.
ACKNOWLEDGMENT
The authors would like to thank National Chip Implemen-tation Center and National Science Council, Taiwan, for chip implementation.
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Yao-Huang Kao (M’76) was born in Tainan, Taiwan,
in 1953. He received the B.S., M.S., and Ph.D. de-grees in electronic engineering from the National Chiao-Tung University, Hsin-Chu, Taiwan, in 1975, 1977, and 1986, respectively.
From 1986 to 2006, he was a member of the De-partment of Communication Engineering, National Chiao-Tung University, where he was also appointed as a Full Professor. In 1988, he was a Visiting Scholar at the University of California, Berkeley, where he was engaged in research on nonlinear circuit. He was at Bell Communication Research (Bellcore). He is currently a Professor in the Department of Communication Engineering, Chung-Hua University, Hsin-Chu. He is also a Technical Consultant for RF circuits in many industrial companies and government institutes. His current research interests include nonlinear dy-namics and chaos, high-speed optical communications, and microwave and RF circuit designs.
Prof. Kao is a member of the Institute of Electronics, Information and Com-munication Engineers (IEICE).
Yi-Bin Hsieh (S’07–M’09) was born in Taiwan in
1973. He received the B.S. degree from the National Taipei Institute of Technology, Taipei, Taiwan, in 1993, and the M.Sc. and Ph.D. degrees from the Institute of Communication Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan, in 1998 and 2008, respectively.
He is currently with the Institute of Communi-cation Engineering, National Chiao-Tung University. His current research interests include mixed-mode signal processing IC design, and clock and data re-covery circuit design.
