11-1
A 0.5-14-GHz 10.6-dB CMOS Cascode Distributed Amplifier
Ren-Chieh Liu’, Chin-Shen Lin’;, Kuo-Liang Deng’ and Huei
Wag’+
+Dept. of Electrical Engineering and ‘Graduate Institute of Communication, National Taiwan University, Taipei, Taiwan, R.O.C.
Phone: +886-2-2363525 1 ext.547 Fax: +886-2-23638247 e-mail: rcliu@ntu.edu.tw
Abstract
A 0.5-14-GHz distributed amplifier (DA) using 0.18-pm
CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6 2 0.9
dB
gain, NFbetween 3.4 and 5.4 dB with good retum losses better than from 0.5 to 14 GHz. The measured output IP3 and Plds are +20 dBm and +IO dBm, respectively, from 2 to 10 GHz.
Introduction
Distributed amplifiers are broadband circuits whose gain-bandwidth product substantially exceeds the transistor unit-gain frequency fr, by absorbing the input and output capacitances of the active devices in the distributed structures. Table 1 summarizes the recently reported performance of CMOS distributed amplifiers compared with this work [I-61. Using cascode gain cells
and m-derived matching sections, the gain bandwidth product of our chip is believed to be the highest among the recent published results reported for a CMOS distruibted amplifier.
Circuit Design and Fabrication
The cascode configuration, known for its high maximum available gain, wide bandwidth, improved input-output isolation, and variable gain control capability, have been utilized in may applications such as mixers, frequency multipliers and distributed amplifiers. Fig. 1 compares the maximum available gain and maximum stable gain of
cascode and common-source stages for the NMOSs with total gain-width of 160
m,
based on the S-parameters of a common-source NMOS from 1 - 30 GHz.The schematic of the CMOS DA is shown in Fig. 2. It consists of an input and output transmission line formed by using lumped inductors and coupled by the transconducatnces of the MOSFETs. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. Conventional cascode FETs suffer from a large feedback capacitance, the drain- source capacitance of the common-gate transistor. This makes it tend to be unstable and thus more difficult to use in an amplifier circuit than a common-source E T . The
cascode devices of t h i s design employ a 20-R damping resistor in the gate of common-gate transistor to improve the stability. The inductors were simulated by a full wave EM simulator, Sonnet 6.0, to ensure the model accuracy up to very high frequency [7]. The die micrograph is
shown in Fig. 3. The proposed cascode CMOS DA was fabricated using a 0.18-pm 1P6M standard CMOS process. The chip size is approximately 1.0 x 1.6 mm* including testing pads.
Measurement Results
The CMOS DA chip was tested via on-wafer probing. Figs. 4 and 5 show the measured gain return losses
(SI] and Sz2) and noise figure from 0.5 to 20 GHz. The power gain is 10.6 0.9 dB and the noise figure is between 3.4 dB and 5.4 dB with good return losses better than lldB from 0.5 to 14 GHz. The measured S-
parameters results agree with the simulated results very well. The power gain of the DA can be controlled with the gate bias of the common gate stage. The measured gain- control range is greater than 25 dB with gain variation less than 3 dB from 0.5 to 14 GHz. The two-tone test result
was showed as in Fig. 6. The output IP3 is +20 dBm and the measured output PI& is +IO dBm from 2 to
IO
GHz.The overall performance rivals the recently published results reported for a CMOS dichuibted amplifier.
Acknowledgement
This work is supported in part by the National Science Council (NSC 91-2213-E-002-042 and ME 89E-FA-06-2-
4) and the Research Excellence Program fund by the Ministry of Education, ROC (89E-FA-06-24), The chip is fabricated by TSMC through the Chip Implementation Center (CIC), Taiwan, ROC. The authors would like to thank Kun-You Lin, Chi-Hsueh Wang and National Nano- Device Laboratory (NDL), Taiwan, ROC, for the chip testing.
References
[I] P. I. Sullivan, B. A. Xavia, and W. H. Ku, “An integrated CMOS distributed amplifier using packaging inductance,”
IEEE Tmn. on M7ir, vol. 45, pp. 1969-1975, Oct. 1997
[Z] B. M. Ballweber, R. Gupta, and D. J. Allstot, “A fully
integrated 0.5-5.5-GHz CMOS distributed amplifier”, IEEE
J. Solid-Stafe Cirnriu-, vol. 35, pp. 231-239, Feb. 2000
[3] H. Ahn. D. J. Allstot, "A 0.5-8.5-GHz fully differential CMOS distributed amplifier", fEEE J. Solid-Sfate Circuifs, vol. 37, pp. 985-993, Aug. 2002
[4] P. F Chen, R. A. Johnson, M. Wetzel, P. R. de la Houssaye, G. A. Garcia, P. M. Asbeck, and 1. Lagnado. "Silicon-on- sapphire MOSFET distributed amplifier with coplanar waveguide matching," IEEE RFIC Symp. Dig., pp. 161-164,
1998
[SI B. Kleveland, C. H. Diaz, D. Vook, L. Madden, T. H. Lee, and S. Wong, "Monolithic CMOS distributed amplifier and
oscillator,"IEEEISSCCDig. Tech. Papers, pp. 70-71, 1999
[6] B. M. Frank, A. P. Freundorfer, and Y. M. M. Antar, "Pdoramnce of I-IO-GHz traveling wave amplifiers in
0 . 1 8 - p C M O S , IEEE MWCL, vol. 12, pp. 327-329, Sep. 2002 [7] http://www.sonnetusacom ".*!, ," 0.6W cMDI 3 5 9 5.1 c4 <-9 i z o +7 3 54 [ I ] 4 6.5 18
-
e-7 ~ ~ 1- 018.8 3 83.4 [Z] 0.6W CMOE 7.5 5.5 26 8.7- 13 <-6 C 9 . S - - 3 216 [3] OIlYoEOI._"
I
I D 5 32 - c.5 <-7 - . .I
-I
I41Table 1. Recently reported performance of CMOS distributed amplifiers. B W Bandwidth. G B P Gain-bandwidth product. NF: Noise Figure. SOS: Silicon-on-sapphire.
0 10 20 x1
Frequeny (GHz)
Fig. 1. Maximum stable gain of a single transistor and cascode- connected transistors.
Fig. 2. Schematic circuit diagram of the cascode CMOS DA.
Fig. 3. Microphotograph of the fabricated cascode CMOS DA.
Fig. 4, Measured power gain and input retum loss.
Fig. 5. Measured noise figure and output retum loss.
~
_
_
50 10 10P o
E
-12
.a Jo 4 -yJ -10 -10 "P"tm"-I'IBm, .~ -Fig. 6. I-dB compression point and third order intercepts point measurement at 2 , h and I O GHz.
11-2
An optimally transformer coupled, 5GHz Quadrature
VCO in a 0.18pm digital
CMOS
process
A. Ravi, K. Soumyanath, Ralph E. Bishop, Bradley A. Bloechel, L. R. Carley'
Communication and Interconnect
Technology,
Intel Labs, Intel Corporation, Hillsboro,OR
97124, USAECE
Dept., Camegie Mellon University, Pittsburgh,PA
15217,USA
2
Abstract
We present a SGHz, voltage controlled quadrature oscillator, based on transformer coupling between the quadrature components. The oscillator is fabricated in a 0 . 1 8 p , low voltage digital CMOS process with a lossy substrate (p
-1Omohm-cm) and thin, high resistivity metallization. Fully integrated low Q (-4) spirals form the transformer windings in the resonators. The coupling has been optimized to obtain quadrature accuracy with minimum phase noise degradation.
The VCO achieves a tuning range of -1GHz, and a phase noise of up to -123dBclHz at a lMHz offset, while drawing
7SmA at 1.6V. An image reject receiver built using the on-
wafer quadrature signals, provides 43dB of image rejection, c o n f d n g better than 1' of quadrature matching.
Introduction
Accurate In-phase (I) and Quadrature (Q) signals are required in many wireless transceiver architectures. Traditionally, the required signals have been generated using poly-phase filters [I], [2], actively coupled oscillators [3], [4] or by a digital frequency divider from an
oscillator at twice the desired frequency. All of the above degrade the intrinsic phase noise of the component resonators. In contrast, we produce quadrature linkage through the magnetic fields of mutually coupled resonators. We are thus able to simultaneously optimize area, energy and phase noise in a native 0 . 1 8 p digital CMOS process. The process we have used presents significant challenges to VCO design, including a lossy substrate (p -1Omohm-cm) and thin (1.6pmm, 0.6gm 'esp.), high resistivity M6, M5, resulting in low Q (-4) inductors. No process enhancements are used in this work.
Quadrature Tank and Transformer Coupling
The conventional LC quadrature oscillator couples two negative impedance based oscillators, operating at the desired carrier frequency (Fig la). Without the negative
impedance cells (NIC), this circuit can also be redrawn as
an explicit 4 stage ring (Fig Ih). Barkhauseu's criterion for sustained oscillations stipulates that each stage provide a phase shift of 90'. Ignoring the inversion at each stage, we require:
e~
+
e
=90° ( I )Where
e,,
is the phase shift provided by the active devices in the bansconductor stages and Omr is the phaseshift across the tank at resonance. Typically, is small and
Eltank
is forced to he significantly greater than O', its value at natural resonance. Since the effective quality factor of the tank (Qea a dO,,.k/df) peaks at Old = 0 [I],the effective quality factor of the stages of the loop is forced to be significantly lower. This reduces loop gain of the quadrature oscillator and in turn worsens the phase noise performance.
The resonant phase shift of the bandpass LC network (Fig.lc) [5], [6] varies in the range
[O',
90'1 and can be controlled by the coupling coefficient k. In principle, this network can be used as the stage resonator to satisfy (1) while operating at a frequency close to tank resonance. Atlow values of k, the phase shift \from port 1 to port 2) of this 2"d order tank approaches 90 (Fig. 2a). However, due to the poor quality factor of on-chip inductors, the gain at resonance across the stage also reduces correspondingly.
At high values of k, the gain at resonance is higher but the phase shift is very close to
O',
which reduces to the conventional LC tank (Fig. 2b). Careful optimization of k(Fig. Zc) however shows that over a reasonably wide range of capacitive coupling, large values (close to 904 of
ea
can he obtained with good gain.Since the tanks provide close to 90' of phase shift, coupling two of them to form a quadrature pair suggests itself. The phase noise degradation can be minimized if the inter-stage coupling can be affected with the fewest number of active devices. The structure we have implemented (Fig. 3) further lowers the phase noise by using magnetic coupling in a dual transformer arrangement.
The shaded box in Fig. 3a, consisting of the primary winding of transformer T2, secondary of T1 and the nodes
190, I90b,, form a differential version of the enhanced tank
in Fig IC. The primary of T I couples this signal to Q and Qbar , the signal nodes of the quadrature oscillator. The phase shift of the enhanced tank and the coupling arrangement ensures that the current directions in the secondary increase the effcctive inductance of the primary (the resonating element). For a I to 1 turns ratio we have; Leq = Lp(l+m) where m is the magnetic' coupling coefticient between the primary and secondary. The resultant Q boosting further reduces phase noise. A reciprocal arrangement using T2 couples I and
Ibar
on the primary to Q90 and Q90b, on the secondary. .The primaryis realized on M6 and the secondary on M5 strapped with M4 (also 0.6pm thick). It is important to note that absolute symmetry between the primary and symmetry is not required for quadrature acccuracy. It is sufficient for the bilateral coupling between the component oscillators to be identical. Capacitor Cc is a linear capacitor realized using vertical walls (M2 through M6). and sets the coupling coefficient (k) of the enhanced tank.
The tuning scheme we present does not use diodes or accumulation mode capacitors. The former is not compatible with low voltage techniques and the latter was
not available naturally in this low cost digital process. We have achieved a large tuning range (-1GHz) by using a
depeletiodinversion varactor (C in Fig. 4). sized with L,, > L- (the minimum gate length). These varactors have a monotonic tuning characteristic with large signal swings, required for PLL stability. In the small signal case, at the maximum control voltage the channel will have disappeared and the capacitance is dominated by the overlap capacitance, resulting in C,,.=W.C,,, where W is the varactor width and CO, is the drain to gate overlap capacitance. At minimum control voltage, the presence of the inversion layer results in C,=W*L*C,,. Hence by using an L,,, >L,,, we achieve the required large Cm/C,, ratio. The large signal effective capacitance
