High-Performance InGaZnO Thin-Film Transistors Using HfLaO Gate Dielectric

IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 12, DECEMBER 2009 1317

High-Performance InGaZnO Thin-Film Transistors

Using HfLaO Gate Dielectric

N. C. Su, S. J. Wang, and Albert Chin, Senior Member, IEEE

Abstract—In this letter, we report a low-voltage-driven

amor-phous indium–gallium–zinc oxide thin-film transistor with a

high-κ-value HfLaO gate dielectric. Good characteristics were

achieved including a low V

of 0.22 V, small subthreshold swing

of 76 mV/dec, high mobility of 25 cm

_/V

_{· s, and large I}

on

/I

ratio of 5

× 10

. These good performances are obtained at an

operation voltage as low as 2 V. These characteristics are attractive

for high-switching-speed and low-power applications.

Index

Terms—Amorphous

indium–gallium–zinc

oxide

(a-IGZO), equivalent oxide thickness, HfLaO, high-κ, thin-film

transistors.

I. I

A

FTER Nomura et al. [1], [2] demonstrated the

trans-parent and flexible TFTs using novel amorphous

indium–gallium–zinc oxide (a-IGZO), the a-IGZO TFTs [2]–

[15] have attracted lots of attention for potential

applica-tion in high drive current and large-area display with a

low cost. This high transistor current is particularly required

to drive high-resolution active-matrix organic

light-emitting-diode displays [3], [4]. Compared to the Si-based counterpart,

a-IGZO TFTs can provide the merits of both

amorphous-Si and polycrystalline-amorphous-Si TFTs, i.e., even in the amorphous

phase, a-IGZO TFTs still exhibit high mobility comparable

with polycrystalline-Si TFTs, and the amorphous property of

IGZO channel also helps to reduce the nonuniformity of

mo-bility and threshold voltage (V

). Moreover, a-IGZO TFTs

can be processed with a significantly low thermal budget, and

therefore, they can be used in emerging applications such as

flexible displays and low-cost flexible ICs [2]–[15].

To improve the device performance, low V

and small

sub-threshold swing (SS) are required. These can be achieved by

controlling the device process, such as oxygen partial pressure,

deposition pressure, IGZO composition, channel thickness, and

anneal temperature [5]. Incorporating high-κ gate dielectric into

TFT provides alternative solution to reach these goals [16]–

[18]. In this letter, we report the high-performance a-IGZO

TFT using high-κ HfLaO gate dielectric. The HfLaO also

Manuscript received September 7, 2009. First published November 6, 2009; current version published November 20, 2009. This work was supported in part by the National Science Council of Taiwan and helped by the National Nano Device Laboratory. The review of this letter was arranged by Editor A. Nathan. N. C. Su and S. J. Wang are with the Institute of Microelectronics, Depart-ment of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: [email protected]; [email protected]).

A. Chin is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the Nano-Electronics Consortium of Taiwan, Hsinchu 300, Taiwan (e-mal: albert_achin@ hotmail.com).

Digital Object Identifier 10.1109/LED.2009.2033392

Fig. 1. Schematic diagram of the a-IGZO TFT with HfLaO gate dielectric.

shows less Fermi-level pining than HfO

[19]–[21], owing to

unique negative flatband voltage of La

O

[22] for low V

n-MOS devices. Our HfLaO IGZO TFT also permits

low-voltage operation with low power consumption for portable

display application.

II. E

The devices were fabricated on the insulated SiO

/Si

sub-strate. A 50-nm TaN was first deposited by reactive

sputter-ing. After gate patterning, the TaN surface was treated by

NH

plasma that is important to reduce gate leakage

cur-rent [17], [18], [23]. Then, a 300-nm HfLaO gate dielectric

was deposited by PVD at room temperature, followed by a

400

C O

annealing for 5 min. The gate dielectric is preferred

to form by PVD for its low process temperature,

particu-larly when a plastic substrate is used [2], [18], [24]. Next,

40-nm IGZO channel layer was deposited by sputtering from

a ceramic IGZO target (Ga

O

: In

O

: ZnO = 1 : 1 : 1) in

a gas mixture with a 5% O

in Ar. Then, Al source/drain

electrodes of 300 nm were deposited and annealed at 300

C

under N

ambient. Here, metal masks were used to pattern the

device. The metal–insulator–metal capacitors were also

fabri-cated side-by-side to characterize the gate capacitance and

leak-age current. The devices were characterized by current–voltleak-age

(I–V ) and capacitance–voltage (C–V ) measurements using

HP4156C semiconductor parameter analyzer and HP4284A

precision LCR meter, respectively.

III. R

D

Fig. 1 shows the schematic cross-sectional view of the

a-IGZO TFT, where bottom gate device structure is used. The

C–V and J –V characteristics of the TaN/HfLaO/Al gate

ca-pacitors are shown in Fig. 2(a) and (b), respectively. The

measured high capacitance density of 5.1 fF/μm

gives an

equivalent oxide thickness of 7 nm and a high-κ value of 25

1318 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 12, DECEMBER 2009

Fig. 2. (a) C–V and (b) J –V characteristics of TaN/HfLaO/Al capacitors.

Fig. 3. Output characteristics of an a-IGZO TFT with HfLaO gate dielectric. The device size is 50 μm× 500 μm.

in HfLaO dielectric. Such large gate capacitance density can

benefit the transistor drive current, lower down the operation

voltage, and improve the I

/I

. A low leakage current of

5.7

× 10

A/cm

at 2 V was also measured due to the large

30-nm thickness.

The output I

–V

characteristics of the high-κ HfLaO/

a-IGZO TFT is shown in Fig. 3. Well-behaved transistor

char-acteristics were observed even under a low operation voltage of

2 V, which is important for low-power application.

Fig. 4 shows the transfer I

–V

characteristics of the

high-κ HfLaO/a-IGZO TFT. The μ

and V

were determined

from the linear I

versus V

plot. Excellent low SS of

Fig. 4. Transfer characteristics of an a-IGZO TFT with HfLaO gate dielectric. The device size is 50 μm× 500 μm.

TABLE I

COMPARISON OFIGZO TFTs WITHVARIOUSGATEDIELECTRICS

76 mV/dec is reached, which is even comparable with

submi-crometer single-crystalline Si MOSFET.

Such small SS is essential to turn on the transistor fast at

low voltage. This small SS is attributed to both good

high-κ–a-IGZO interface charge density (D

) and the high gate

capacitance density [17]

SS =

KT

q

× ln 10 ×



1 +

C

+ C

C



(1)

where C

is the depletion capacitance density of a-IGZO, C

is the capacitance density from charged interface traps, and C

is the gate capacitance density. The very high C

of 5.1 fF/μm

using HfLaO results in the good SS. Aside from a large 5

× 10

for I

/I

ratio, a low V

of 0.22 V and high μ

mobility of

25 cm

/V

· s are obtained simultaneously. The good mobility

is also related to the amorphous structure of HfLaO after

400

C anneal [19] with small surface roughness of only

0.57 nm.

In Table I, we compare important device parameters of

a-IGZO TFTs with various gate dielectrics of SiO

, AlTiO,

SU et al.: HIGH-PERFORMANCE InGaZnO THIN-FILM TRANSISTORS 1319

Si

N

/TiO

, Si

N

, Ba

Sr

TiO

, and Y

O

. The

perfor-mance of our HfLaO IGZO TFTs is comparable with other

devices, with additional merit of the best normalized drive

current (μC

) [17], [18] under a low voltage of 2 V. Therefore,

the high gate capacitance density C

is as important as mobility

for the needed high transistor drive current.

IV. C

A high-κ HfLaO dielectric was successfully integrated into

a-IGZO TFTs. The HfLaO/a-IGZO TFTs showed a low V

of 0.22 V, small SS of 0.76 mV/dec, large μ

mobility of

25 cm

/V

· s under a low operation voltage, and a high I

/I

of 5

× 10

. This device is suitable for high-speed low-power

ICs on glass panel.

R

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