68 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 3, MARCH 1998
Evaluation of Plasma Charging
Damage in Ultrathin Gate Oxides
Horng-Chih Lin,
Member, IEEE, Chi-Chun Chen, Chao-Hsing Chien, Szu-Kang Hsein, Meng-Fan Wang,
Tien-Sheng Chao,
Member, IEEE, Tiao-Yuan Huang,
Fellow, IEEE, and Chun-Yen Chang,
Fellow, IEEEAbstract—Monitoring of plasma charging damage in ultrathin
oxides (e.g.,<4 nm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides.
Index Terms— Dielectric breakdown, plasma materials-processing applications, semiconductor device reliability.
T
HE plasma charging damage has attracted much attention in recent years [1]–[9]. As gate oxide thickness is scaled down, the plasma charging damage can potentially degrade oxide integrity significantly. Therefore, how to monitor and minimize the damage becomes important. To this date, most reported studies characterized the charging damage induced in gate oxide which is thicker than 4 nm. In these oxides, Fowler–Nordheim (F–N) tunneling current is the conduction mechanism during high field stressing. Under such situations, electron current injected into the oxide may deposit energy in the oxide and lead to trap creation and interface state generation. These events may shift the device parameters such as threshold voltage , subthreshold swing , transconductance , etc. Consequently, those device pa-rameters can be used as indicators in monitoring the charging damage. As gate oxide is scaled below 4 nm, however, the situation may change since direct tunneling process replaces the F–N tunneling if oxide voltage is smaller than the barrier height of electron at the Si/SiO interface ( 3.2 V). Therefore, the effectiveness of using those device parameters in characterizing the damage should be carefully examined.In this letter, we investigate this issue by performing measure-ments on devices with 2.6-nm gate oxide. MOS capacitors and n-channel transistors were fabricated on 6-in wafers. Gate oxides were grown after LOCOS isolation, followed by nManuscript received July 25, 1997; revised September 18, 1997. This work was supported by National Science Council of Republic of China under Contract NSC-86-2721-2317-001.
H.-C. Lin, and T.-S. Chao are with National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C.
C.-C. Chen, C.-H. Chien, S.-K. Hsein, M.-F. Wang, and C.-Y. Chang are with the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan R.O.C.
T.-Y. Huang is with National Nano Device Laboratories, Hsinchu 300, Tai-wan, R.O.C. and the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
Publisher Item Identifier S 0741-3106(98)01962-4.
Fig. 1. Threshold voltage, subthreshold swing, and transconductance as a function of cell position. Antenna area ratio of the devices is 15 000.
poly-Si deposition which was employed as the gate electrode. Oxide thickness was determined by fitting the current–voltage characteristics with theory [10] and verified by high resolution TEM [11]. Metal antenna structures attached to the gates were used to monitor the damage. After definition of metal patterns, the photoresist is stripped off in a down-stream type asher. Detailed description of the asher can be found in our previous reports [4]–[6]. Finally, wafers received a 400 C anneal in forming gas for 20 min. Electrical characterization was then performed with an HP 4145 parameter analyzer.
Fig. 1 shows the , , and of transistors as a function of cell location. The measurements were performed on nine cells along a line that lies across the wafer. The measured devices have a channel length and width of 1.7 and 10 m, respectively; and antenna area ratio (AAR) value of 15 000. It is seen that, even with a large AAR value, these parameters vary only slightly across the wafer. In addition, no significant difference is found among transistors with various AAR values. Based on these results, one would tend to conclude that the plasma damage is negligible. However, significant damage is actually identified by the charge-to-breakdown measurements, as illustrated in Fig. 2. Tran-sistors with AAR of 500 and 15 000 were measured and compared. Distinctive difference between the two types of devices is found at the wafer center, in which the of devices with AAR of 15 000 drops to 0, indicating that severe damage has been induced. The damage region is similar to that found in previous reports [3]–[6], and has been identified to be induced during ashing treatment. Comparing the results 0741–3106/98$10.00 1998 IEEE
LIN et al.: EVALUATION OF PLASMA CHARGING DAMAGE IN ULTRATHIN GATE OXIDES 69
Fig. 2. Charge-to-breakdown values as a function of cell position.
(a)
(b)
Fig. 3. (a) Threshold voltage, subthreshold swing, and transconductance, and (b) charge-to-breakdown values as a function of antenna area ratio. The test cell is located at the wafer center.
shown in Figs. 1 and 2, it becomes obvious that the parameters used in Fig. 1 are not appropriate to serve as the indicators for monitoring charging damage in ultrathin oxides.
In order to make this point even more clear, we also measured the aforementioned parameters of transistors with various AAR values from a cell located in the wafer center. The results are shown in Fig. 3, in which the channel length and width of the measured devices are 1.2 and 10 m,
(a)
(b)
Fig. 4. Drain and gate current as a function of gate voltage measured (a) before and (b) after charge-to-breakdown test. Channel length and width of the measured transistor are 1.2 and 10m, respectively.
respectively. From Fig. 3(a), it is observed that the , , and are independent of the AAR values. Nevertheless, distinctive antenna effect can be seen from the measure-ment [Fig. 3(b)], consistent with the results shown in Fig. 2. Therefore, it can be concluded that is more reliable and sensitive than those device parameters in evaluating charging damage.
Such a finding is reasonable, since the rates of trap creation and interface state generation under high-field stressing de-crease significantly as oxides are scaled down [12]. In fact, we also found that the subthreshold characteristics of a transistor with such thin oxide depict little changes even after the charge-to-breakdown test. An example is shown in Fig. 4, in which the only shifts 1 mV after oxide breakdown, while and remain almost unchanged. The only parameter that depicts significant changes shown in the figures is the gate leakage , which increases significantly after oxide breakdown. The resultant excessive could prevent the device from practical applications. However, without actually monitoring the , the failed device may possibly be regarded as “good”. This point has been raised previously [9], and becomes significant as oxide thickness is scaled.
In summary, we have shown that traditional method of monitoring the transistor parameters, including , , and
70 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 3, MARCH 1998 , may not be appropriate for detecting the charging damage
in gate oxides as thin as 2.6 nm. In order to access the real damage situation, some destructive measurements, such as charge-to-breakdown, time-dependent dielectric breakdown (TDDB), or breakdown field measurement, maybe indispens-able. It is noted that, long-channel devices (e.g., 1.7 and 1.2 m) have been commonly used for characterizing the charging damage to eliminate uncertainties due to channel length variations. However, as devices’ dimensions enter the deep submicron regime, the situation may probably become more complicated due to the presence of short-channel and short-width effects, which could make the shift of device’s parameters significant.
ACKNOWLEDGMENT
The authors would like to acknowledge the staffs of NDL for technical assistance.
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