Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process

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(1)IEICE. TRANS.. ELECTRON.,. VOL.E91-C,. NO.3. MARCH. 2008. 378. PAPER. Circuit with. Performance. Bootstrapped. 130-nm. CMOS. Degradation Technique. of Switched-Capacitor due to Gate-Oxide. SUMMARY The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switchedcapacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device degrades the circuit performance of bootstrapped switch technique. key words: gate-oxide reliability, sample-and-hold amplifier, dielectric breakdown, bootstrapped switch, switched-capacitor circuit Introduction. The switched-capacitor circuit is an important building block in analog integrated circuits, such as analog-to-digital data converter (ADC). The high-speed and high-resolution analog-to-digital data converter needs a high performance switched-capacitor circuit. The low-supply voltage will degrade the performance of the switched-capacitor circuit due to the nonlinear effects of the MOSFET switch such as body effect, turn-on resistance variation, charge injection, and clock feedthrough [1]-[9]. The bootstrapped switch [1]-[4] and switched-opamp (switched operational amplifier) techniques [5]-[9] have been widely used in low-voltage switched-capacitor circuit. The switched-opamp technique is not suitable for highspeed switched-capacitor circuit, because it needs much more time to turn an opamp on/off than to turn a switch on/off [6]. The bootstrapped technique provided a constant voltage between the gate and drain nodes of the MOS switch is used to improve the performances of low-voltage and high-speed switched-capacitor circuit. However, the bootstrapped technique causes the gate-oxide overstress on the MOS switch to degrade the lifetime of switch device [1]. The gate-oxide reliability of MOS switch in the lowManuscript Manuscript. Overstress. in a. Process* Jung-Sheng. 1.. Circuit. CHEN†,. Nonmember. and. Ming-Dou. KER†a),. Member. voltage and high-speed switched-capacitor circuit with the bootstrapped technique is a very important reliability issue. The suitable device size design for the bootstrapped switch circuit [1], the thick-oxide MOSFET device [2], and the drain extended MOSFET device [3] can be used to avoid the gate-oxide overstress on the switch devices. Some design techniques of limit gate voltage in bootstrapped switch circuit had been proposed [4]. The impact of gate-oxide reliability on circuit performance of switched-capacitor circuit with bootstrapped technique wasn't investigated in the previous works [1]-[4]. In this work, the impact of gate-oxide reliability on MOS switch in the switched-capacitor circuit with the bootstrapped technique is investigated with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process [10]. The timedomain and frequency-domain circuit performances of the SHA with the unity-gain buffer are measured after the gateoxide overstress on the MOS switch. 2.. Bootstrapped ity. Technique. with. Gate-Oxide. Reliabil-. The conceptual schematic of the bootstrapped technique for switched-capacitor circuit is shown in Fig. 1(a). The basic schematic includes the signal MOS switch Ms, five ideal switches S1-S5, and a capacitor Cb. The CLK1 and CLK2 clock signals are the out-of-phase signals. When CLK1 is low and CLK2 is high (under sampling mode), the S3 and S4 switches charge the capacitor Cb to the supply voltage VDD, and the S5 switch is used to turn off the switch device Ms. When CLK1 is high and CLK2 is low (under hold. received June 19, 2007. revised October 2, 2007.. The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.. * This work was supported in part by the National Science Council (NSC), Taiwan, R.O.C., under Contract NSC 96-2221-E009-182. a) E-mail: [email protected] DOI: 10.1093/ietele/e91-c.3.378 Copyright (c). 2008 The Institute. of Electronics,. (b). (a). Fig. 1 (a) Conceptual schematic and (b) detail circuit implementation bootstrapped technique for switched-capacitor circuit.. Information. and Communication. Engineers. of.

(2) CHEN and KER: CIRCUIT. PERFORMANCE. DEGRADATION. OF SWITCHED-CAPACITOR. CIRCUIT. WITH BOOTSTRAPPED. TECHNIQUE 379. Fig. 2. Simulated. the switched-capacitor. waveforms circuit. of gate-oxide with. bootstrapped. transient. overstress. event. in. technique.. Fig. 3 voltage. The dependence of the different waveform in the switched-capacitor. sampling circuit. capacitors on output with the bootstrapped. technique.. mode), the S1 and S2 switches change the capacitor Cb in series with the input signal VIN and connect to the gate of the switch device Ms, such that the gate-to-source voltage across the switch device Ms is equal to the supply voltage VDD.The gate voltage of switch device Ms will be charged to VIN+VDD,which is larger than the supply voltage. The detailed circuit implementation is shown in Fig. 1(b) [11]. The M1, M2, M3, M4 and M5 correspond to the five ideal switches S1-S5 of Fig. 1(a). The M6 transistor is added to reduce the maximum drain-to-source voltage (VDS) of M5 transistor to avoid the gate-oxide overstress. The capacitor Cb must be large enough to supply charge to the gate of switch device in addition to all parasitic capacitors in the charge path. Moreover, charge sharing will significantly reduce the boosted voltage [1]. The sampling capacitor Cs in the switched-capacitor circuit with the bootstrapped technique is usually designed with several pF to improve the circuit performance. If the rise time of the voltage at gate node of the switch device is too fast, a large voltage could exist across the gate oxide of the switch device to degrade the lifetime of the switch device, before a channel is formed to equalize the potential between the source and drain. In order to explain the gateoxide transient overstress event in switched-capacitor circuit with bootstrapped technique, the simulated waveforms of the bootstrapped switch circuit are shown in Fig. 2. The drain node of the switch device is driven by an input signal VIN, and the source node of the switch device is connected to a large sampling capacitor. As the switch device turns on, an approximate voltage of VIN+VDD will be generated on the gate node to keep the constant voltage VDD between the gate and drain nodes of the switch device. Before a channel is formed and before the sampling capacitor is charged to supply voltage VDD, an excessive voltage greater than VDD may exist across the gate-to-source side of the switch device. This effect could create an oxide reliability problem. In Fig. 2, the simulated result is a worse case of switched capacitor circuit with bootstrapped oxide transient overstress.. technique. under the gate-. The input signal frequency, sampling frequency, and delay times of bootstrapped and sampling networks are the major design factors in the switched-capacitor circuit with the bootstrapped technique. Figure 3 shows the dependence of the different sampling capacitors on output voltage waveform in the switched-capacitor circuit with the bootstrapped technique. The VG is the gate voltage of the switch device Ms. The input signal VIN is set to 2-MHz sinusoidal signal with peak-to-peak amplitude of 1.2V, and sampling frequency is set to 10MHz. The different sampling capacitors in the switched-capacitor circuit with bootstrapped technique can be used to simulate the different delay times of the sampling network. The difference RC delay time between the sampling network (Ms and Cs) and the bootstrapped network (M1-M8 and Cb) will induce the gate-oxide transient overstress across the gate-to-source side of the switch Ms to cause the long-term reliability issue in the switchedcapacitor circuit with the bootstrapped technique. The dependences of the input/sampling frequency (fI/fS) ratio on maximum transient voltage in the switchedcapacitor circuit with the bootstrapped technique are shown in Fig. 4. The maximum transient voltage is defined as the maximum voltage difference between the source node and the gate node of the switch Ms during the sampling mode. The sampling capacitor of the switched-capacitor circuit with bootstrapped technique is set to 8pF. The high input/sampling frequency ratio has a larger transient voltage than the low input/sampling frequency ratio in the switchedcapacitor circuit with the bootstrapped technique. The overstress time is related to the RC time constant ratio of the sampling and bootstrapping networks in the bootstrapped switch technique. Based on Figs. 3 and 4, the RC delay time of the bootstrapped network should be designed slower than that of the sampling network in the switched-capacitor circuit with the bootstrapped technique to avoid the transient gate-oxide reliability. The best solution is that the bootstrapped and sampling networks have the same RC delay times to avoid the transient gate-oxide over-.

(3) IEICE. TRANS.. ELECTRON.,. VOL.E91-C. 380. , NO.3. MARCH. 2008. Fig. 5 The complete circuit of sample-and-hold amplifier with the gateoxide reliability test circuit, where the control device Mc is used to control the source. Fig. 4 The dependence of the input/sampling frequency ratio on maximum transient voltage in the switched-capacitor circuit with the bootstrapped technique.. stress. 3.. and to achieve. the best. Switched-Capacitor bility Test Circuit. performance.. Circuit. with Gate-Oxide. Relia-. The switched-capacitor circuit with the bootstrapped technique has a long-term reliability problem which causes circuit performance degradation. The overstress voltage on the gate oxide of the switch device depends on the voltages of input and clock signals. The obvious degradation of circuit performance in the switched-capacitor circuit with the bootstrapped technique needs a long-term operation, which may need many years, to observe the change due to the gate-oxide degradation of the switch device. The gate-oxide degradation of the switch Ms in the switched-capacitor circuit with bootstrapped technique is more likely to occur as the conventional time-dependent dielectric breakdown (TDDB). The TDDB accelerated lifetime-model for the nMOSFET can be expressed as [12].. equation. (1) where. A=W×L. is the. device. gate-oxide. area,. β is the. weibull slope parameter, F is the cumulative failure percentage at use condition, Vgs is the gate-to-source voltage, T is the temperature, and a, b, c, and d are the model-fitting parameters determined from the experimental work, ATDDB is the model factor. Note that a+bT is always negative. The model of TDDB breakdown related with frequency is still a challenge. Equation (1) is not suitable to calculate the lifetime of the switch device in the switched-capacitor circuit with bootstrapped technique. Therefore, to investigate the impact of gate-oxide reliability on circuit performance of the switched-capacitor circuit with bootstrapped technique is very important in advanced CMOS technology. In order to accelerate the degradation of circuit performance and to understand the impact of gate-oxide transient overstress event on switched-capacitor circuit with bootstrapped technique, the SHA with the gate-oxide reliability. voltage. of the switch. device. Ms for reliability. test.. test circuit is proposed in Fig. 5. The SHA with unity-gain buffer is used to verify the gate-oxide reliability of the bootstrapped switch. The two-stage operational amplifier is used to realize the output buffer. The folded-cascode operational amplifier and common-source amplifier are used to form the two-stage operational amplifier to achieve high output swing and high small-signal gain. Simulated by HSPICE, the twostage operational amplifier has the open-loop gain of 75dB, the unity-gain frequency of 160MHz, and the phase margin of 87.3 degrees, respectively, under output capacitive load of 2.5pF. The normal operating voltage and the gate-oxide thickness (tox) of all MOSFET devices in the SHA with the gate-oxide reliability test circuit are 1.2V and 2.63nm, respectively, in a 130-nm CMOS process. The control device Mc is used to control the source voltage of the switch device Ms. Therefore, the device dimension of the control device Mc should be designed larger than that of the switch device. The device dimensions of switch device (Ms) and control device (Mc) are selected as 40μm/0.12μm. and. 500μm/0.12μm,. respectively,. in a 130-. nm CMOS process. If the device dimension of the control device is smaller than that of the switch device, the source voltage of switch device Ms will not be kept at near ground. In normal operation, the control voltage Vc is biased to ground, such that the control device Mc will be turned off. The SHA with the unity-gain buffer can be successfully operated. In the gate-oxide overstress test, the control voltage Vc is biased to supply voltage VDD, and input signal VIN is biased to the supply voltage VDD. The voltage at VCLKnode can be applied with any higher voltage level than the supply voltage to overstress the gate oxide of switch device. The voltage across the gate-to-source nodes of switch device Ms can be controlled by the VCLKvoltage.. However, the switch device suffers from the dynamic (AC) stress in the real operation. The dynamic stress is less harmful than DC stress on switch device, but the dynamic stress on switch device still causes damage on gate oxide of switch device after long-term operation. The DC stress on switch device can be used to accurately estimate the damage occurring on the switch device to investigate the impact of gate-oxide reliability on MOS switch with bootstrapped technique. The difference between the AC stress in real case and DC stress in this test has the different degraded times of.

(4) CHEN and KER: CIRCUIT. PERFORMANCE. DEGRADATION. OF SWITCHED-CAPACITOR. CIRCUIT WITH BOOTSTRAPPED. TECHNIQUE 381. circuit performance, but they will have the same degradation trend on circuit performance after long-term operation [13]. Therefore, the proposed test circuit can be used to verify the impact of gate-oxide breakdown on circuit performance of the bootstrapped switch technique. The test chip has been fabricated in a 130-nm CMOS process, and the normal operating voltage of all MOSFET devices is 1.2V. The chip micrograph and layout view of the SHA with the gate-oxide reliability test circuit are shown in Figs. 6 (a) and 6 (b), respectively. The occupied silicon area including two testing circuits and ESD (electrostatic discharge). protection. devices. is 390μm×390μm.. The. top. layer of test chip is covered and protected by polyimide layer. Figure 7 shows the simulated frequency-domain (10MHz sampling frequency at VCLKnode and 2-MHz sinusoidal signal at VINnode) and time-domain (10-MHz sampling frequency at VCLKnode and 1-MHz sinusoidal signal at VIN node) waveforms of the sample-and-hold amplifier with the gate-oxide reliability test circuit under normal operation. The signal at VCLKnode is applied with clock signal between 0V to 1.2V. Simulated by HSPICE, the spurious. (a). free dynamic range (SFDR) of the SHA with the gate-oxide reliability test circuit is 38.6dB. 4.. Experimental. Results. When the SHA with the gate-oxide reliability test circuit is operating in the overstress mode, the input signal VINis biased to supply voltage, and the control voltage Vc is set to supply voltage. In order to observe the circuit performance degradation of the SHA due to the gate-oxide degradation of the switch device, the voltage at VCLKnode is kept to 2.4V for accelerating the gate-oxide degradation of the switch device. Only the gate-to-source nodes of the switch Ms is overstressed to simulate the switched-capacitor circuit with the bootstrapped technique. The measured results of test circuit are measured with die under test on the printed circuit board (PCB). When the time-domain and frequency-domain waveforms are re-evaluated after the gate-oxide overstress on the MOS switch, the signal at VCLKnode is applied with clock signal between 0V to 1.2V. After overstress time of 5.2 hours, the gate-oxide breakdown occurred on the switch device. The gate-leakage current (IG-leakage)of the switch. (b). Fig. 6 (a) Chip micrograph and (b) layout view of the sample-and-hold amplifier with the gate-oxide reliability test circuit realized in a 130-nm CMOS process. Two sets of test circuit in Fig. 5 are fabricated on the chip.. (a). (b) Fig. 7. The simulated. the sample-and-hold der normal. operation.. frequency-domain. amplifier. and time-domain. with the gate-oxide. reliability. waveforms. of. test circuit. un-. Fig. 8 The measured frequency-domain and time-domain waveforms of the sample-and-hold amplifier with the gate-oxide reliability test circuit. (a) Overstress time=0. hour, and (b) overstress time=5.2. hours..

(5) IEICE. 382. device. is jumped. from. 330nA. 2.4V due to the gate-oxide. to. 80.6μA. under. VCLK. TRANS.. ELECTRON.,. VOL.E91-C,. NO.3. MARCH. 2008. of. breakdown.. Figures 8 (a) and 8 (b) show the frequency-domain (10MHz sampling frequency at VCLKnode and 2-MHz sinusoidal signal at VINnode) and time-domain (10-MHz sampling frequency at VcLK node and 1-MHz sinusoidal signal at VIN node) waveforms at VOUTnode under the different stress times. Though date is shown till 8MHz, only the date below 5MHz is valid because of aliasing by Nyquist criterion. The SFDR of the test circuit is degraded by the gate-oxide breakdown on the switch device from 35.62dB to 30.86dB, because the gate-oxide breakdown causes extra gate-leakage current across gate oxide of the switch device to degrade the circuit performances of the SHA with the. (a). gate-oxide reliability test circuit. However, the amount of gate-leakage current depends on the gate-oxide breakdown location of the switch device. The gate-oxide breakdown location near channel region of the switch device (soft breakdown) has a smaller gate-leakage current than that near the drain or source side of the switch device (hard breakdown) [14]. 5.. Discussion. In order to investigate the impact of gate-oxide breakdown location (switch device) on performances of the switchedcapacitor circuit with bootstrapped technique, the prior pro-. (b). posed method [14] can be used to simulate this impact with HSPICE. The gate-oxide breakdown of a MOSFET device can be modeled as resistor. Only the gate-to-diffusion (source or drain) breakdown was considered, since it represents the worst-case situation [12], [14]. Breakdown to the channel can be modeled as a superposition of two gateto-diffusion events. Typical hard breakdown leakage has a close-to-linear I-V curve and an equivalent resistance of ∼103-104Ω high. . However,. non-linear,. sistance. above. resistance. typical. power. law. 105-106Ω. [14].. (VCLK/IG-leakage). stress. is approximate. under. VCLK. 30kΩ. soft breakdown. I-V. of. curve The. the (hard. and. paths. equivalent. switch. re-. breakdown. device. gate-oxide. have. equivalent. after. over-. breakdown). of 2.4V.. The SHA including equivalent breakdown resistors RGD and RGS is shown in Fig. 9 (a). The simulated frequency-domain (10-MHz sampling frequency at VCLK node and 2-MHz sinusoidal signal at VIN node) and timedomain (10-MHz sampling frequency at VCLKnode and 1MHz sinusoidal signal at VINnode) waveforms of the SHA with. equivalent. breakdown. resistor. (RGS. and. RGD). (c) Fig. 9 (a) The sample-and-hold amplifier with the gate-oxide reliability test circuit including equivalent breakdown resistors RGD and RGS. The simulated frequency-domain and time-domain waveforms of the test circuit. with. equivalent. breakdown. resistors. (b) RGD. and. (c) RGS. of. 30kΩ,. respectively.. of 30kΩ. are shown in Figs. 9 (b) and 9 (c), respectively. Comparing the simulated (Fig. 9 (c)) and measured (Fig. 8 (b)) results, the gate-oxide breakdown on the switch device in the SHA with the gate-oxide reliability test circuit is near the source side of the switch device. The differences between Fig. 8 (b) and Fig. 9 (c) are due to the gate-to-channel and gate-todrain breakdowns on the switch device caused the extra gate leakage current in the SHA. Only the gate-to-source oxide breakdown on the switch device will degrade the per-. formances of the SHA. In the sampling mode of the SHA, the gate leakage current of switch device is smaller than the charge current (ID) of switch device current. In hold mode of the SHA, the extra gate leakage current of will discharge the stored charge in sampling capacitor to degrade the circuit performance of the SHA. The relationship between extra gate leakage current and stored charge of sampling ca-.

(6) CHEN and KER: CIRCUIT PERFORMANCE DEGRADATION OF SWITCHED-CAPACITORCIRCUIT WITH BOOTSTRAPPED TECHNIQUE 383. on. switch. device. strapped. 6.. switch. The. sample-and-hold. amplifier. with. the. gate-oxide. reliability. test circuit including equivalenn breakdown resistors RGS. The simulated frequency-domain and time-domain waveforms of the test circuit with equivalent. breakdown. resistors. RGS. of 500kΩ.. pacitor under the SHA operated expressed as ΔV=. Qhold/ CS. in hold mode can be simple. oxide. order. to. breakdown. (2). / Cs,. circuit. cuit. equivalent. with. investigate on circuit. capacitor. with. the. performances. bootstrapped breakdown. impact. of of the. technique, resistor. soft. RGS. test. RGS. of gate-oxide transient overstress on the MOS bootstrapped technique has been investigated with the sample-and-hold amplifier. The timefrequency-domain waveforms of the SHA afstress times have been measured. After the. pling networks have the same RC delay times to avoid the transient gate-oxide overstress and to achieve the best performance. The hard gate-oxide breakdown has more serious impact on switched-capacitor circuit with bootstrapped technique.. of 500kΩ. is shown. in Fig.. References. [1]. 500kΩ. can. 10.. The. pact on circuit performances than soft gate-oxide breakdown. Abo. and. P.R.. pp. 599-606,. J.-B.. Park,. 10-b. 150-Msample/s. Aksin,. Circuits, [4]. S. Yao,. X.. strapped IEEE. Kim,. and. Cho,. and. CMOS. CMOS Circuits,. S.-H.. A/D. Lee,. “A. converter. J. Solid-State. F. Maloberti,. beyond. supply. pp. 1938-1943,. Wu,. Y.-J.. IEEE. Shyoukh,. and. switches. 14.3-MS/s. J. Solid-State. with. Circuits,. vol.39,. 2004.. sampling. vol.41,. 10bits, IEEE. 123-mW. bandwidth,”. M.A.. for precise. S.-W. 1.8V. Aug.. 1.5V,. 1999.. Yoo,. input. pp. 1335-1337, D.. “A. converter,”. May. S.-M.. 400-MHz. [3]. Gray,. analog-to-digital. vol.34, [2]. X.. Int. Electron. Aug.. Yan,. in low. “Switch. voltage,”. Devices. J. Solid-State. 2006.. “Modifications. voltage. bootstrapping. IEEE. for reliability. switched-capacitor. and. Solid-State. of boot-. circuits,” Proc.. Circuits,. pp. 449-452,. 2005. [5]. S.-M.. Yoo,. Park,. S.-H.. CMOS. [6]. J.-B.. L.. Papers,. Wang. A.. Chang. ADC. using. Circuits, L. Dai hold. U.-K.. H.-J. 0.18μm. Conf.. high-speed. bootstrapper,” Aug.. Dig.. Moon,. Trans.. 10-bit. technique,”. Syst.. 25-MS/spiplined. IEEE. J. Solid-State. 2003.. switched-op-amp-based. J. Solid-State. in standard. Circuits. 2001.. Aug.. “CMOS. circuit. IEEE. “A 1.4-V. pp. 1401-1404,. J. Solid-State. 2003.. at 40Ms/s,” April. switched-. IEEE. sample-and-hold. switching. R. Harjani,. Moon,. 123mW Circuits. “Low-voltage. voltage. opamp-rest. circuit,” IEEE. K.-H.. Int. Solid-State. Embabi,. pp. 394-399,. and. Bae, 150MS/s. 2003.. operating. vol.38,. and. IEEE. pp. 1411-1415,. no.4,. H.-H.. “A 10b. “A low-voltage. technology. D.-Y.. Yang,. Kim,. without. vol.38,. II, vol.48,. [9]. S.H.K.. Baschirotto,. CMOS. H.-S.. J.-H.. ADC,”. circuits. Circuits,. [8]. and. pp. 326-497,. and. capacitor. [7]. Park,. Lee,. pipelined. Tech.. soft. gate-oxide breakdown on the switch device also degrades the circuit performance of SHA. The soft and hard gateoxide breakdown on a CMOS transistor will cause different extra gate leakage currents. The soft gat-oxide breakdown on a transistor causes a smaller extra gate leakage current than that of the hard gate-oxide breakdown in CMOS process [14]. Therefore, the soft and hard gate-oxide breakdown will have different impact on circuit performances of SHA. The hard gate-oxide breakdown has more serious im-. A.M. pipeline. cir-. pling frequency at VCLKnode and 1-MHz sinusoidal signal at VINnode) waveforms of the SHA with equivalent breakresistor. boot-. gate-oxide overstress, only the gate-to-source oxide breakdown on the switch device will degrade the performances of the SHA. The overstress time is related to the RC time constant ratio of the sampling and bootstrapping networks in the bootstrapped switch technique. The best solution of bootstrapped switch design is that the bootstrapped and sam-. switched-. the of. gate-. be used to model the soft gate-oxide breakdowns on the switch device [14]. The simulated frequency-domain (10MHz sampling frequency at VCLKnode and 2-MHz sinusoidal signal at VIN node) and time-domain (10-MHz sam-. down. with. = CSVhold-IG_leakageThold. where Tholdis the hold time (2/fs, fs sampling frequency), CS is the sampling capacitor, Qholdis a stored charge in sampling capacitor, Vholdis the ideal potential stored in sampling capacitor without oxide breakdown on the switch device under hold mode, and IG_leakage is the extra gate leakage current of switch device due to gate-oxide breakdown. When the SHA operated in high sampling frequency, the gate-oxide breakdown on switch device has small impact on circuit performance. Therefore, the proposed SHA with the gateoxide reliability test circuit can be used to verify the impact of gate-oxide breakdown on switched-capacitor circuit with bootstrapped switch technique. In. circuit. Conclusion. The impact switch with and analyzed domain and ter different. Fig. 10. of switched-capacitor technique.. Circuits,. sample-and-. vol.35,. pp. 109-113,. Jan.. 2000. [10]. J.-S.. M.-D.. Ker,. CMOS. Proc.. process,”. M.. X.. “Circuit. due. IEEE. performance. to gate-oxide. degradation. overstress. Int. Reliability. Physics. of. in a 130-nm. Symp.,. pp. 705-. 2006. Dessouky. rail-to-rail [12]. and. amplifier. 706, [11]. Chen. sample-and-hold. and. Li, J. Qin,. reliability. A.. Kaiser,. operation,” B.. Huang,. simulation. circuits,” IEEE. Trans.. “Input switch. Electron. X.. configuration. Lett., vol.35,. Zhang,. and. J.B.. suitable. pp. 8-9,. Jan.. Bernstein,. method. for deep. submicrometer. Device. Materials. Reliabil.,. vol.6,. for. 1999. “A SPICE. CMOS. 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(7) IEICE TRANS. ELECTRON.,. 384. June [13]. C.. 2006. Yu. age. and. vol.52, [14]. J.S. Yuan,. “MOS. stress-modeling no.8,. pp. 1751-1758. R. Degraeve, B. “Relation between short. channel. tions,” IEEE Sept.. and. RF. , Aug.. Kaczer, A.D. breakdo wn. NMOSFETs Trans.. reliability. and. Device. subject. analysis,” IEEE. Trans. to dynamic . Electron. volt-. Devices,. 2005. Keersgieter, mode. and. its impact. Materials. and. G.. Groeseneken,. breakdown on. Reliabil. location. reliability ., vol.1,. in. specifica-. pp. 163-169,. 2001.. Jung-Sheng. Chen. received the B.S. de-. gree from electronics engineering from National Taiwan University of Science and Technology, Taipei, Taiwan, in 2000, the M.S. degree in engineering and system science from National Tsing-Hua University, Hsinchu, Taiwan, in 2002, and Ph. D. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2007. His current research interests include analog circuit design, mixed-signal circuit design, and circuit reliability.. Ming-Dou. Ker. received. the B.S. de-. gree from the Department of Electronics Engineering and the M.S. and Ph. D. degrees from the Institute of Electronics, National ChiaoTung University, Hsinchu, Taiwan, R.O.C., in 1986, 1988, and 1993, respectively. In 1994, he joined the VLSI Design Department of the Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, as a Circuit Design Engineer. In 1998, he was the Department Man-. ager in the VLSI Design Division of CCL/ITRI. Now, he has been a Full Professor in the Department of Electronics Engineering, National ChiaoTung University. In the field of reliability and quality design for CMOS integrated circuits, he has published over 300 technical papers in international journals and conferences. He has proposed many inventions to improve reliability and quality of integrated circuits, which have granted with 125 U.S. patents and 135 R.O.C. (Taiwan) patents. His current research topics include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel applications in TFT LCD display. He has been invited to teach or to consult reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC industry. Dr. Ker has served as member of the Technical Program Committee and Session Chair of numerous international conferences He was selected as a Distinguished Lecturer in IEEE Circuits and Systems Society for 2006-2007. He has also served as Associate Editor of IEEE TRANSACTIONS ON VLSI SYSTEMS. He was elected as the President of Taiwan ESD Association in 2001. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by Junior Chamber International (JCI). In 2005, one of his patents on ESD protection design has been awarded with the National Invention Award in Taiwan. In 2008, Prof.. Ker. tributions optimization. has to. been. elevated. electrostatic of. VLSI. as. IEEE. protection micro-systems.”. Fellow in. integrated. with. the. citation. circuits,. and. of. “for. performance. con-. VOL.E91-C,. NO .3 MARCH. 2008.

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