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Study Trapped Charge Distribution in P-Channel Silicon–Oxide–Nitride–Oxide–Silicon Memory
Device Using Dynamic Programming Scheme
View the table of contents for this issue, or go to the journal homepage for more 2013 Jpn. J. Appl. Phys. 52 04CD01
(http://iopscience.iop.org/1347-4065/52/4S/04CD01)
Study Trapped Charge Distribution in P-Channel Silicon–Oxide–Nitride–Oxide–Silicon
Memory Device Using Dynamic Programming Scheme
Fu-Hai Li1, Yung-Yueh Chiu1, Yen-Hui Lee1, Ru-Wei Chang1, Bo-Jun Yang1, Wein-Town Sun3,
Eric Lee3, Chao-Wei Kuo3, and Riichiro Shirota1;2
1Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
2Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu 300, Taiwan 3SONOS Technology Research Program, eMemory Technology Inc., Jhube, Hsinchu 302, Taiwan E-mail: [email protected]
Received September 23, 2012; revised October 23, 2012; accepted October 26, 2012; published online February 20, 2013
In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon–oxide–nitride–oxide–silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking. # 2013 The Japan Society of Applied Physics
1. Introduction
Conventionally, many studies have been done for the charge distribution in SiN layer during programming in n-channel
silicon–oxide–nitride–oxide–silicon (SONOS) devices,1–4)
using several methods,5–12) such as comparison between
sub-threshold and gate induced drain leakage (GIDL)
characteristics,1,6,7) studying Vt difference between forward
and reverse read.4,11,12) These studies have revealed that
injected charges were locally concentrated near to drain side until SiN trapped states are fully occupied by trapped charge. After that the trapped charges are extended to the source
side,4) gradually. On the other hands, recently, in order to
achieve high performance and highly reliable embedded Flash memory, lots of interests have been focused on
p-channel SONOS memory devices.13–15) Especially, three
superior characteristics of p-channel Flash memory (low voltage operation, high speed programming, and low power
consumption) have been emphasized.16,17) In order to
achieve hot electron injection in SiN layer, low gate voltage setting is required and makes it possible to attain low voltage operation at the gate. Next, hot electron injection efficiency in p-channel devices can be higher than that in n-channel
devices,18,19) which results in high speed programming and
low power consumption. Furthermore, channel electron tunneling erase operation in p-channel device does not produce hot hole injection because of the larger hole barrier
height,19) as long as applied erasing voltage is lower so
as not to generate hole injection from substrate. Therefore, hot-hole-free operation scheme in p-channel device further
reinforces the reliability.19)Additionally, dynamic
program-ming scheme with gate voltage staircase pulses has been
proposed15) to achieve higher programming efficiency and
low bit-line bias operation. By adopting dynamic program-ming scheme, memory cell can perform better writing efficiency and suffer less oxide degradation than the constant
programming scheme15)(i.e., apply a fixed voltage on gate),
due to the suppression of hot hole injection. However, the trapped charge distribution induced by channel hot hole induced hot electron injection (CHHIHE) in p-channel SONOS device has not been explored yet. In this paper,
trapped charge distribution as a function of programming time is studied. At first, experimental forward and reverse
current–voltage (I–V) characteristics are calibrated to fit the
parameters of numerical three-dimensional device simula-tions. Next, we investigate the dependence on the program-ming time of trapped charge distribution with various pulse width and number of pulses for p-channel SONOS device by comparing experimental programming characteristics and
simulated I–V characteristics. Following the introduction,
Sect. 2 introduces the device structure, bias setting and methodology for studying the electrical characteristic induced by localized charge in p-channel SONOS device. In Sect. 3, the spatial charge distribution of the localized trapped charge is shown.
2. Device Structure, Bias Setting, and Methodology
Schematic p-channel SONOS device structure under analy-sis is presented in Fig. 1. The channel length, channel width and equivalent oxide thickness (EOT) of the ONO layer
are 0.18m, 10 m, and 10.8 nm, respectively. Figure 2(a)
shows the programming window ofVtR[i.e., the difference
betweenVtin reverse read (RR) and the initial stateVt] and
VtRF (i.e., the reverse to forward Vt difference). In order
to simplify the simulation methodology, we consider an idealized non-uniform distribution, represented by a step
function, so that the trapped charge density (TD) is assumed
to have only two possible values in two different regions.
P+Poly SiO2 Si3N4 SiO2 W/L=10/0.18 μm Control Gate Blocking oxide Trapping layer Tunnel oxide EOT = 10.8 nm D S
Fig. 1. (Color online) Schematic SONOS device structure used for experiments. The channel length, channel width and EOT of the ONO layer are 0.18m, 10 m, and 10.8 nm, respectively.
Then, TD and the effective trapped charge length (TL) are
extracted, as shown in Fig. 2(b). Figures 3(a) and 3(b) show the bias setting of constant and dynamic programming scheme. Figures 3(c) and 3(d) show the programming waveforms of two schemes with various pulse widths. The increment gate voltage step up pulse is used with seven steps as shown in Figs. 3(c) and 3(d), where three kinds of pulse
widths (1, 7, and 14s) are examined. Figure 3(e) shows the
total programming time with various pulse widths per step.
3. Simulation and Experimental Results
Initial state before programming is prepared by electron tunnel erasing and electrons are uniformly distributed
(9:5 1018cm3) in SiN layer, as shown in Fig. 4. Next,
simulated n-channel contour plot of VtR and VtRF as a
function of TL and TDare exhibited in Figs. 5(a) and 5(b).
On the other hands, the simulated p-channel plots are shown in Figs. 5(c) and 5(d). In the case of n-channel device, charges in SiN layer locally concentrate near to drain side
to getVtRFmore than 1 V, as shown in Fig. 5(b). However,
in the case of p-channel device, charges in SiN layer need
to be extended into source side to getVtRFmore than 1 V,
as shown in Fig. 5(d). This difference comes from the formation of local inversion layer in the p-channel device when electrons are injected in SiN layer. Figures 6(a) and 6(b) are simulated channel surface potential associated with
the cases 1–4 as marked in Fig. 5(c), where differentTLand
TD are placed. The equivalent value of VtR is observed
between case 1 and case 2 or between case 3 and case 4. In comparison of case 1 and case 2, the maximum potential barrier heights are the same even though they have the
differentTD. On the other hand, in comparison of case 3 and
case 4, the potential barrier heights also are the same in spite
of the different TL. Figure 7 shows the comparison of
program transients of the constant and dynamic program-ming schemes with various pulse width (a) 1, (b) 7, and
VG (V) 0 1 2 3 4 5 ID (A) 10-10 10-9 10-8 10-7 10-6 10-5 10-4 (a) ΔVtR ΔVtF ΔVtRF VD= -1.5V, Forward Read VS= -1.5V, Reverse Read
Trapped Charge Length (TL)
TO
BO N
VG
Trapped Charge Density (TD)
VS VD
(b)
Fig. 2. (Color online) (a)VtRandVtFis the programming window in reverse and forward read condition.VtRFis the reverse to forwardVt difference. (b) The trapped charge density (TD) and the effective trapped charged length (TL) are extracted.
G D S Sub. 0V 0V 0V Dynamic PGM Scheme G D S Sub. 0V 0V 0V Constant PGM Scheme G D S 0V 0V -5V Vstep= 0~3V G D S 0V 0V -5V 0V
Pulse Width : 1μs, 7μs and 14μs
Vstep 1μs 7μs 7μs 49μs 14μs 98μs Total PGM Time Pulse Width per step
Constant Scheme Dynamic Scheme
(a) (b)
(c)
(d)
(e)
Pulse Width : 1μs, 7μs and 14μs
Fig. 3. (Color online) (a, b) Bias setting of constant and dynamic programming scheme. (c, d) Programming waveforms of constant and dynamic programming scheme with various pulses width used in this work. (e) The total programming time with various pulse widths per step.
VG (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 I (A)D 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 Forward Read, VD = -1.5V Reverse Read, VS = -1.5V Simulation
Fig. 4. (Color online) Comparison of the measured and simulatedI–V curves in forward and reverse read to verify the initial state condition.
case2 case1 case3 case4 (c) (d) (a) (b) (Δ Vt R – Δ Vt F )Δ Vt RF (V ) (Δ Vt R – Δ Vt F )Δ Vt RF (V ) Re v erse Thr eshold V o ltage Shift Δ Vt R (V) Re v erse Thr eshold V o ltage Shift Δ Vt R (V)
Drain N-Channel Source Drain P-Channel Source
Fig. 5. (Color online) N- and P-channel contour plots of (a) and (c)VtR and (b) and (d)VtRFas a function of the effective trapped charge region and the density of charge.
F.-H. Li et al. Jpn. J. Appl. Phys. 52 (2013) 04CD01
(c) 14s, respectively. Dynamic programming scheme has higher programming efficiency than constant programming
scheme, where programming efficiency is defined byVtshift
divided by program time, as shown in Fig. 7. Figures 8(a)
and 8(b) show the measuredVtRandVtRFas a function of
gate voltage step up pulse. As shown in Fig. 8(a), pulse
width 7 and 14s exhibit different Vth shift at the same
programming time. It indicates that pulse width 7s have the
best programming efficiency. Figures 9(a) and 9(b) show
VtR versus VtF (the difference between Vt in forward
read and the initial stateVt) andVtF=VtRas a function of
programming time for the analysis of charge uniformity.
After programming time longer, VtR vs VtF curves
approach the line (VtR¼ VtF) in both of pulses width 7
and 14s. It means that the charges are getting uniformly
distributed in SiN layer as program step number increased.
Cross point of the contour plots between VtR andVtRF
show the value ofTDandTL, as shown in Figs. 10(a)–10(d),
where 1s pulse width is used. Programming time
de-pendence of TD and TL from first (Vstep¼ 0 V) to fourth
(Vstep¼ 1:5 V) pulses are represented in series from
Figs. 10(a) to 10(d). The saturation of the value of VtR
andVtRFappears atVstepequal to 1.5 V (see Fig. 8), which
result in the saturation of the extension of TD and TL.
Figure 11 shows the simulated trapped charge evolution curve dependent on program step number, coupled to the
measured results. In the case of 1s pulse width, TL will
extend to SiN layer by applying seven program steps even
though it exhibits lower TD and programming speed (see
Fig. 7). Between two pulses width (7 and 14s),TL andTD
have the same trajectory, even though they have the different programming speed. Consequently, it is shown that the trapped charge smoothly extends into the SiN layer in seven program steps. The Electric field associated with different
TL during programming period is shown in Fig. 12. The
PGM Time (μμs) 1 2 3 4 5 6 7 Δ Vt R (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Constant PGM Scheme Dynamic PGM Scheme PGM Time (μs) 7 14 21 28 35 42 49 Δ Vt R (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Constant PGM Scheme Dynamic PGM Scheme PGM Time (μs) 14 28 42 56 70 84 98 Δ Vt R (V) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Constant PGM Scheme Dynamic PGM Scheme Pulse Width = 1μs Pulse Width = 7μs Pulse Width = 14μs
(c) (b)
(a)
Fig. 7. (Color online) Comparison of program transients of the constant and dynamic programming schemes at various pulse width (a) 1, (b) 7, and (c) 14s respectively.
Gate Voltage Step Up Pluse Vstep(V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 Δ Vt R (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Pulse Width = 1μs Pulse Width = 7μs Pulse Width = 14μs (a) PGM Time = 7μs PGM Time = 49μs PGM Time = 98μs PGM Time = 28μs
Gate Voltage Step Up Pulse Vstep(V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 Δ Vt RF = Δ Vt R - Δ Vt F (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Pulse Width = 1μs Pulse Width = 7μs Pulse Width = 14μs (b)
Fig. 8. (Color online) Measured dynamic programming characteristics. (a) Reverse threshold voltage shift and (b) reverse-forward threshold voltage shift versus gate voltage step.
ΔΔVtF(V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Δ Vt R (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Pulse Width = 1μs Pulse Width = 7μs Pulse Width = 14μs (a) Dot line : ΔVtF= ΔVtR PGM Time (μμs) 1 10 100 Δ Vt R /Δ Vt F 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 Pulse Width = 1μs Pulse Width = 7μs Pulse Width = 14μs Dot line : ΔVtF= ΔVtR (b)
Fig. 9. (Color online) (a)VtFversusVtRand (b)VtF=VtRas a function of programming time for the analysis of charge uniformity resulting from various pulse widths, such as 1, 7, and 14s respectively. Channel Position (0.05 0.00 -0.05μμm) -0.10 0.10 Surface Potential (V) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Erased State, VS = 0 V Erased State, VS = -1.5 V PGM State (case1), VS = -1.5 V PGM State (case2), VS = -1.5 V case1 case2 Charged length
Trapped Charge Nitride Layer
Source n i a r D (a) ΔVtRof case1 ΔVtRof case2 0.7V Channel Position (0.05 0.00 -0.05μμm) -0.10 0.10 Surface Potential (V) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Erased State, VS = 0 V Erased State, VS = -1.5 V PGM State (case3), VS = -1.5 V PGM State (case4), VS = -1.5 V
Trapped Charge Nitride Layer Charged length Source Drain case3 case4 ΔVtRof case3 ΔVtRof case4 1V (b)
Fig. 6. (Color online) Simulated channel surface potential correspond with [cases 1–4 as marked in Fig. 5(c)].
PGM Time = 1μμs μs PGM Time = 2μs PGM Time = 3μs PGM Time = 4μs~7μs (b) (a) (d) (c) ΔVtR(V) ΔVtR− ΔVtF(V) Vstep= 0 V Vstep= 0.5 V Vstep= 1 V Vstep= 1.5V Pulse Width = 1
Fig. 10. (Color online) ExtractTLandTDusing contour plot (see Fig. 5) of the cross point betweenVtRandVtRFwith variousV condition: (a) 0, (b) 0.5, (c) 1, and (d) 1.5 V.
accumulated trapped charges in SiN layer and the pinches-off point below the channel will move from drain side toward source side. Figure 13 shows the measured and simulated programming window in forward and reverse read with various pulse widths. The measured and simulated I–V curves show good agreements. In n-channel device, the
Vt is sensitive to TL. However, in p-channel device, the
charge almost uniformly distributed into SiN and the Vt
is insensitive to TL. Consequently, by using FN erase plus
CHHIHE programming, uniform charge transfer between the substrate and trapping layer is executed, which will ensure the robust program and erase operation.
4. Conclusions
In this paper, we have quantitatively traced the evolutionary trapped charge distribution induced by various dynamic pulse times in p-channel SONOS device. During a short dynamic programming period, the trapped charges quickly extend into the SiN layer of the whole p-channel based on our result. On the other hand, the channel length self-modulation can reduce the programming stress of gate oxide. This study provides a comprehensive understanding and design guidelines for p-channel SONOS devices.
Acknowledgments
The authors would like to thank Chun-Yuan Lo, Chia-Jung Hsu, and all members of SONOS Technology Research Team of eMemory Technology Inc., Taiwan for the preparation of the samples and supports of characterization.
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Charged Length (nm) 110 115 120 125 130 135 140 145 150 Density of Charge (x10 19 cm -3) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Pulse Width =1μs Pulse Width =7μs Pulse Width =14μs 1stVstep 1stVstep 1stVstep 7thVstep 7thVstep 7thVstep
Fig. 11. (Color online) Simulated trapped charge evolution curve depends on program step number using dynamic programming scheme.
Trapped Charge Length (TL)
TL=54nm
TL=108nm
TL=144nm
Fig. 12. (Color online) Electric field associated with differentTLduring programming period. FR Exp. 1 RR Exp. 1 s/step FR Exp. 7 s/step RR Exp. 7 s/step FR Exp. 14 s/step RR Exp. 14 s/step FR Sim. 1 s/step RR Sim. 1 s/step FR Sim. 7 s/step FR Sim. 14 s/step RR Sim. 14 s/step RR Sim. 7 s/step μs/step μ μ μ μ μ μ μ μ μ μ μ VG (V) 0.00.51.01.52.02.53.03.54.04.55.0 ID (A) 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
PGM window with various pulse width
Fig. 13. (Color online) Measured and simulated programming window in forward and reverse read with various pulse widths.
F.-H. Li et al. Jpn. J. Appl. Phys. 52 (2013) 04CD01
