Abstract—A new electrostatic discharge (ESD) implantation
method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 m/0.5 m has been suc-cessfully improved from the original 450 V to become 675 V in a 0.25- m CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 m/0.5 m for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation method with the n-type impurity can be fully merged into the general subquarter-micron CMOS processes.
Index Terms—Electrostatic discharge (ESD), ESD implantation,
ESD protection, machine model.
I. INTRODUCTION
C
OMPONENT-LEVEL ESD stresses on integrated circuit (IC) products had been classified as three models [1]: the human body model (HBM) [2]–[4], the machine model (MM) [5], [6], and the charged device model (CDM) [7], [8]. The ESD voltage ratio between HBM and MM ESD robustness of CMOSIC products was around in the submicron m
CMOS processes [9], [10]. In the past, most of ESD design efforts were focused to improve HBM ESD robustness of IC products. With a high HBM ESD robustness, the IC products also had a high enough MM ESD level. Typically, a CMOS IC product, which has a HBM ESD robustness of 2 kV, can sus-tain a MM ESD stress of 200 V. However, the MM ESD ro-bustness of IC products has been found to degrade much worse than its HBM ESD robustness in the subquarter-micron CMOS processes. This ratio has approached about 15–20 in the sub-quarter-micron CMOS processes. The CMOS IC fabricated by the subquarter-micron CMOS processes can still be designed to have a high HBM ESD robustness, but it becomes more chal-lenging to have a high enough MM ESD level. When the IC Manuscript received June 2, 2003; revised June 30, 2003. This work was supported by the National Science Council, Taiwan, R.O.C., under Grant NSC 92-2215-E-009-036. The review of this paper was arranged by Editor C.-Y. Lu. M.-D. Ker and H.-C. Hsu are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung Univer-sity, Hsinchu, Taiwan 300, R.O.C. (e-mail: [email protected], m8911550@ alab.ee.nctu.edu.tw).
J.-J. Peng is with the ESD Protection Technology Department, SoC Technology Center, Industrial Technology Research Institute (ITRI), Chutung, Hsinchu, Taiwan 300, R.O.C. (e-mail: [email protected]).
Digital Object Identifier 10.1109/TED.2003.817273
products enter into the phase of mass production, the IC prod-ucts are processed by a lot of automatic machines, such as the assembly and test machines, to have a throughput as fast as pos-sible. So, the MM ESD robustness of such mass-production IC product is often more important then its HBM ESD robustness. How to effectively improve MM ESD robustness of IC prod-ucts has become a challenge in the subquarter-micron CMOS processes. But, from the past literature, it is seldom to see the design or method for improving MM ESD robustness.
In order to enhance ESD robustness, some ESD implan-tations had been reported for including into process flow to modify the device structures for ESD protection [11]–[13]. The N-type ESD implantation was used to cover the lightly-doped drain (LDD) peak structure and to make a deeper junction in nMOS device for ESD protection [11]. The P-type ESD implantation with a higher doping concentration located under the drain junction of nMOS was used to reduce the junction breakdown voltage, and to earlier turn on the parasitic lateral n-p-n bipolar junction transistor (BJT) of the nMOS [12]. Moreover, both of the N-type and P-type ESD implantations were used in nMOS devices to create a higher ESD robustness [13]. The experimental results to compare the effectiveness among those ESD implantation methods had been investigated in a 0.18- m CMOS process [14].
In the mixed-voltage circuit application, the stacked nMOS structure had been widely used in the mixed-voltage input/output (I/O) buffer [15] to solve the gate-oxide reliability issue without using the additional thick-gate-oxide process (also known as dual gate oxide in some CMOS processes) [16], or the power-rail ESD clamp circuit [17]. Unfortunately, in such mixed-voltage I/O circuits, the stacked nMOS often have a much lower ESD level, as compared to the buffer with single nMOS [18], [19].
In this paper, a new ESD implantation method to improve ESD robustness of both single and stacked nMOS is proposed and verified in a 0.25- m CMOS processes. The MM ESD level has been an especially significant improvement [20]. The HBM/MM ESD level ratio in the single nMOS can be success-fully kept at . On the other hand, the ratio between HBM and MM ESD levels in the stacked nMOS can be pulled down from 18.4 to 13.3 by this new ESD implantation method.
II. HBMANDMM ESD CURRENTWAVEFORMS In order to identify the underlying physical mechanisms of the HBM and MM, it is instructive to compare the ESD current discharging waveforms between HBM and MM ESD zapping. The real ESD current discharging waveforms of HBM and MM 0018-9383/03$17.00 © 2003 IEEE
ESD stresses through the gate-grounded nMOS (ggnMOS) are measured and compared to find the difference. The experimental setup to measure the current waveforms during ESD zapping is illustrated in Fig. 1, where the KeyTek Zapmaster is used to gen-erate the HBM and MM ESD sources. The digital oscilloscope with a current probe of Tektronix CT-1 is used to measure the ESD transient currents in time domain.
The actual ESD current waveforms flowing through the ggnMOS with a device dimension width/length (W/L) of
300 m/0.5 m under 4-kV HBM and 400-V MM ESD
stresses are measured and shown in Fig. 2(a) and (b), respec-tively. The current peak of 4-kV HBM ESD stress in Fig. 2(a) is 3.54 A, and the rise time is 35 ns. The current peak of 400-V MM ESD stress on the ggnMOS in Fig. 2(b) is as high as 4.94 A, and the rise time of the current is 15 ns. When comparing these two ESD current waveforms, the MM ESD stress has a much higher ESD current peak within a shorter current pulse width. This implies that the MM ESD event generates more heat in a shorter time period to burn out the device, and therefore to cause a much lower ESD robustness. So, ESD protection design against an MM ESD event has become more difficult than that against an HBM ESD event in subquarter-micron CMOS processes.
III. ESD IMPLANTATIONMETHODS
A. Device Structure
Since ESD robustness is strongly correlated with current distribution in the second breakdown region, observation of ESD current discharging paths of different device structures provides new insight to understand their different ESD per-formance. Generally, the ESD current flowing in a nMOS device has two discharging paths. One is the channel current of the MOSFET, and the other is the parasitic lateral n-p-n BJT current path through the bulk of MOSFET device. In subquarter-micron CMOS technology, the MOSFET fabricated with a high doped arsenic drain, the lightly doped drain (LDD) structure, and a salicided process to improve circuit perfor-mance. However, several problems may occur when these technologies are involved in ESD protection devices [21]. The high doped arsenic drain might reduce the breakdown voltage and snapback holding voltage of nMOS, which may improve ESD robustness. Unfortunately, the high doped arsenic drain increases the electric field in MOSFET to cause severe hot-car-rier reliability issue. To solve this issue, the LDD structure is
Fig. 2. Measured ESD current discharging waveform through the ggnMOS with the device dimension W/L of 300m/0.5 m , which is zapped by (a) 4-kV HBM ESD voltage, and (b) 400-V MM ESD voltage.
commonly implemented in nMOS device to overcome the im-pact of hot-carrier reliability, as the n-type lightly doped drain (NLDD) region shown in Fig. 3(a). Such an LDD structure, however, will encounter severe degradation on ESD robustness [21]. So, the hot-carrier reliability issue and ESD performance should be traded off, and the ESD protection device could be more difficultly designed in subquarter-micron CMOS processes. Moreover, the ESD protection device with salicided process is known to seriously degrade ESD robustness owing to insufficient ballast resistance [22], [23]. Several experimental results have been proven and then suggested to enlarge the clearance from drain contact to poly-gate edge (S ) for better ESD robustness [23], [24].
To improve ESD robustness, some CMOS processes provide one extra ESD-implantation mask to modify the nMOS devices of I/O circuits without the LDD peak structure [14]. One of the traditional ESD implantation methods, with n-type impurity for improving ESD robustness of nMOS, is shown in Fig. 3(b)
Fig. 3. nMOS devices with (a) lightly doped drain (LDD) structure to overcome the hot-carrier issue, and (b) traditional n-type ESD implantation to improve its ESD robustness.
with the extra N_ESD region. The n-type (N_ESD) impurity in subquarter-micron CMOS process often has a lower concentra-tion than that of drain/source source diffusion to overcome the hot-carrier reliability issue. However, the N_ESD impurity with a lower concentration increases the junction breakdown voltage and snapback holding voltage of nMOS, which reduces the turn-on efficiency of the parasitic lateral n-p-n BJT in the MOSFET. A comparison on the effectiveness of improving ESD robustness among the traditional ESD implantation methods had been experimentally investigated in [14].
To significantly improve ESD robustness of nMOS in I/O cir-cuits, the new ESD implantation method is proposed in Fig. 4(a), where the blocking layout spacing “S” is the important layout parameter to be investigated. In Fig. 4(a), the ESD implantation region covers the whole drain region of nMOS device, except for the region around the drain contact. The corresponding layout top view of the nMOS with the new proposed ESD implantation method is drawn in Fig. 4(b), where the blocking layout spacing “S” is also indicated.
This new N_ESD implantation method is used on the stacked nMOS in the mixed-voltage I/O circuits. The cross-sectional view of the stacked nMOS with the proposed N_ESD implanta-tion is shown in Fig. 5(a), where the spacing “S” is the impor-tant layout parameter to be investigated. In Fig. 5(a), the ESD implantation region covers the whole drain region of stacked nMOS device, but except the region around the drain contact. The corresponding layout top view of the stacked nMOS with the proposed ESD implantation method is drawn in Fig. 5(b), where the layout parameter “S,” the clearance from drain con-tact to poly-gate edge (S ), and the spacing (C) between poly gate1 and poly gate2 of the stacked nMOS are also indicated.
This ESD implantation region has a doping concentration (N_ESD) lighter than that of the original drain diffu-sion. The junction covered by the proposed ESD implantation method has a little increased junction breakdown voltage. But, the region not covered by this ESD implantation has the orig-inal junction breakdown voltage. When a positive ESD voltage is zapped to the pad in Figs. 4(a) and 5(a) with the VSS rela-tively grounded, the drain of the nMOS device is stressed by
Fig. 4. (a) Cross-sectional view, and (b) layout top view, of the nMOS fabricated with the new proposed ESD implantation method to significantly improve its ESD robustness. The layout parameter “S” is also indicated in this figure.
Fig. 5. (a) Cross-sectional view, and (b) layout top view, of the stacked nMOS fabricated with the new proposed ESD implantation method to significantly improve its ESD robustness. The layout parameter “S” is also indicated in this figure.
Fig. 6. Fabrication process flow to realize the proposed N_ESD implantation.
the ESD voltage, and therefore breaks down to clamp the over-stress voltage on the pad. However, the region, which is not cov-ered by the N_ESD implantation, has a lower junction break-down voltage. So, the ESD current is first discharged through this region to generate the substrate current [Itrig, indicated in Figs. 4(a) and 5(a)] to quickly trigger on the parasitic lateral n-p-n BJT in the nMOS structure. With the self-generated sub-strate triggering current, the parasitic lateral n-p-n BJT in the nMOS structure can be fully turned on more quickly [25]. So, the fast transient current of ESD events, especially in the MM ESD zapping, can be quickly discharged through the parasitic lateral n-p-n BJT in the nMOS structure. Therefore, the ESD level of nMOS devices can be effectively improved.
B. Process Flow
The fabrication flow for forming the proposed ESD pro-tection device with the new N_ESD implantation is shown in Fig. 6. The fabrication steps use the general fabrication methods for example, photolithography, ion-implantation, oxidation, and etching to implement the proposed ESD device. The detailed fabrication steps are described as follows:
1) Form gate electrodes of the ESD protection device, as that shown in Fig. 7(a)
2) Form LDD structure on the ESD protection device, as that shown in Fig. 7(b).
3) Use the ESD mask layer to define the ESD implanta-tion region, and the light N-type dopant form the N_ESD region in the ESD protection device, as that shown in Fig. 7(c).
4) Form spacers by CVD interlayer dielectric (ILD) on the sidewall of the gate electrodes, as that shown in Fig. 7(d). 5) Apply the diffusion mask to define the source and
drain regions, and then form the source and drain region in the ESD protection device, as that shown in Fig. 7(e).
fusion has a doping dosage of 5 and a junction depth of m. The nMOS fabricated by this new process flow has the junction depth of ESD implantation slightly deeper than the junction depth of drain diffusion. This N_ESD implan-tation envelops the original LDD region of drain side, except the region around the drain contact in the ESD protection device.
IV. EXPERIMENTALRESULTS
To investigate the effectiveness of the new proposed ESD im-plantation method, test chips had been fabricated by a 0.25- m CMOS technology with shallow trend isolation (STI) and sali-cided diffusion. Two types of devices, single nMOS and stacked nMOS, with different blocking layout spacing “S” in the ESD implantation region are investigated. This new proposed ESD implantation method (shown in Figs. 4(a) and 5(a)) on the test devices are directly realized by using the traditional ESD im-plantation mask with light n-type impurity, which had been an optional process step in general CMOS technologies provided by the most foundries. To simply investigate the dependence of the ESD-implanted region (adjusted by the spacing “S” in layout) on ESD robustness of both single and stacked nMOS structures, the layout spacing of the drain diffusion between the gates is fixed at 5.7 m for all devices in the experimental test chips. The clearance (S ) from drain contact to poly gate edge is 2.4 m, and the spacing (C) between poly gate1 and poly gate2 of stacked nMOS is 0.4 m. The devices fabricated with different spacing “S” are measured by the curve tracer to investigate DC – characteristics, by the transmission line pulsing (TLP) system [26]–[28] to investigate secondary break-down current (It2), and by the ZapMaster ESD simulator to in-vestigate HBM and MM ESD robustness. The experimental re-sults are shown in Sections IV-A and B.
A. Experimental Results of ggnMOS With New N_ESD Implantation
1) DC Current–Voltage (I–V) Characteristics: The
mea-sured dc current–voltage (I–V) curves of the ggnMOS devices with different blocking layout spacing “S” in the ESD implan-tation region are compared in Fig. 8. The trigger (switching) voltages of the ggnMOS devices with or 2.3 m are 9.8 V, but that of the ggnMOS device with m is 9.72 V. The holding points of the ggnMOS devices with the layout spacing “S” of 0, 2.3, and 4.9 m have no obvious varia-tion. The dc behaviors of those devices are almost the same, as those shown in Fig. 8. This implies that the new proposed ESD
Fig. 7. Fabrication steps (a) form the gate electrode structure, (b) form the LDD structures, (c) use the light n-type ESD dopant to form the N_ESD region, (d) form spacers by chemical vapor deposition (CVD) interlayer dielectric (ILD) on the sidewall of the gate electrode, and (e) form source and drainN+ regions to realize the proposed ESD protection device.
implantation method does not modify the channel region of the nMOS devices. The trigger voltages of the nMOS devices with fixed channel length and unchanged channel region but different spacing S are the same, since the drain-to-source punch-through voltage dominates the dc characteristics of nMOS devices [29]. When such nMOS devices are used in the output buffer as the pull-down devices, their curves are similar to that of the normal nMOS device in the same CMOS process. This result provides the same device I–V behavior on the ESD-implanted nMOS, as that of normal nMOS, for working as the functional output devices in CMOS IC’s.
Fig. 8. Measured I–V curves of ggnMOS fabricated with the new proposed ESD implantation under different blocking layout spacing “S”.
2) TLP I–V Characteristics: The TLP system has been
widely used to measure the second breakdown characteristics of ESD protection devices to investigate the turn-on behavior of the device during ESD stress. The TLP system used in this measurement has been set up with a pulse width of 100 ns and a rise time of 10 ns to find the It2 of ESD protection devices [27]. When the ESD stress generated by the TLP system zapping on the ESD protection device is greater than its It2, the devices will be permanently damaged by the overstress current. The TLP-measured I–V curves of a ggnMOS with W/L = 300 m/0.5 m are shown in Fig. 9(a) under the different blocking layout spacing “S” in the ESD implantation region. The dependence of the It2 on the blocking layout spacing “S” of the ggnMOS fabricated with the new proposed ESD implantation method is shown in Fig. 9(b). The It2 of the ggnMOS with m is only 2.9 A, when it has a device dimension W/L of 300 m/0.5 m. But, its It2 can be significantly improved up to 3.64 A, when the spacing S is increased to 4.9 m. Under the same layout area of the ggnMOS with W/L = 300 m/0.5 m (the drain diffusion between two poly gates is fixed at 5.7 m), the It2 can be improved 25.5% by using the new proposed ESD implantation method. This implies that the blocking layout spacing “S” in the ESD implantation region is an important design parameter determining ESD robustness for the ggnMOS.
3) ESD Test Results: The ZapMaster ESD tester is used
to investigate the HBM and MM ESD level of the fabricated test chips. The failure criterion is generally defined as the minimum ESD stress to cause the leakage current of the tested device greater than 1 under the voltage bias of 1.1 VDD. To compare with the traditional design, the ggnMOS drawn with layout spacing S of 0 m, where the ESD implantation is cover the whole drain diffusion, is also tested as a reference. The dependences of the HBM and MM ESD robustness on the layout spacing “S” of ESD-implanted ggnMOS, under a fixed device dimension W/L of 300 m/0.5 m, are shown in Fig. 10(a). With the same layout area and device dimension in the ESD-implanted ggnMOS, the wider spacing “S” can lead to higher HBM and MM ESD levels. The HBM ESD level of this ESD-implanted ggnMOS with a fixed device dimension W/L of 300 m/0.5 m is improved from the original 5.75 kV
Fig. 9. (a) TLP-measured I–V curves, and (b) the second breakdown current (It2), under different blocking layout spacing “S” in the ESD implantation region of the ggnMOS.
(with ) to become 6.75 kV (with m). The
MM ESD level of this ESD-implanted ggnMOS, with W/L= 300 m/0.5 m, is also improved from the original 450 V (with ) to become 675 V (with m). This tendency is well consistent with that verified by the TLP-measured It2 in Fig. 9(b).
The ratio between the HBM and MM ESD levels on the layout spacing “S” of the ESD-implanted ggnMOS with W/L = 300 m/0.5 m are further compared in Fig. 10(b). Surprisingly, the HBM/MM ESD level ratio of the ESD-implanted ggnMOS with W/L = 300 m/0.5 m has a value of 12.7 when the spacing
m. As seen in Fig. 10(b), this HBM/MM ESD level ratio can be decreased to 9.9, when the spacing “S” is enlarged to 4.9 m in the ESD-implanted ggnMOS. From the experimental results, the new proposed ESD implantation method can significantly increase ESD level of the nMOS devices in subquarter-micron CMOS processes, especially MM ESD robustness. Moreover, the HBM/MM ESD level ratio can be successfully kept at by this new ESD implantation method.
B. Experimental Results of Stacked nMOS With New N_ESD Implantation
1) DC I–V and TLP I–V Characteristics: The
TLP-mea-sured I–V curves of stacked nMOS with W/L = 300 m/0.5 m,
Fig. 10. Dependence of (a) HBM and MM ESD robustness, and (b) HBM/MM ratio, on different blocking layout spacing “S” in the ESD implantation region of the ggnMOS.
fabricated in a 0.25- m CMOS process with the new proposed ESD implantation method, are shown in Fig. 11(a) under the different layout spacing “S.” The measured dc I–V curves of the stacked nMOS with different layout spacing “S” are also inserted in Fig. 11(a). The dc behaviors of those test devices are almost the same, which imply that the new proposed ESD implantation method does not modify the channel region of nMOS devices [29]. The dependence of the It2 on the layout spacing “S” of the stacked nMOS, fabricated with the new proposed ESD implantation method, is shown in Fig. 11(b). The It2 of the stacked nMOS with m is only 3.25 A, when it has a device dimension W/L of 300 m/0.5 m. But, its It2 can be significantly improved up to 4.03 A, when the spacing S is increased to 3.9 m. Under the same layout area of the stacked nMOS with W/L= 300 m/0.5 m, the It2 can be improved 24% by using the new proposed ESD implantation method.
2) ESD Test Results: The ESD-implanted stacked nMOS
devices are also verified by the ZapMaster ESD simulator under both HBM and MM ESD stresses. The ESD failure criterion of the stacked nMOS under ESD stresses is the same as measuring the single ggnMOS. The dependences of HBM and MM ESD levels on the channel width of stacked nMOS with or 1.5 m are shown in Fig. 12. The HBM and
Fig. 11. (a) TLP-measured I–V curves with the inset of dc I–V curves, and (b) the second breakdown current (It2), under different blocking layout spacing “S” in the ESD implantation region of stacked nMOS.
MM ESD levels are linearly increased, when the channel width of the stacked nMOS is increased. This implies that the ESD implantation method leads to uniformly turn on, and the ESD level is improving when the total channel width increasing. However, as comparing the lines between the HBM and MM ESD levels under different layout spacing S, the MM ESD level has an obvious improvement if the stacked nMOS is drawn with a wider S.
The dependences of the HBM and MM ESD robustness on the layout spacing “S” of ESD-implanted stacked nMOS, under a fixed device dimension of W/L = 300 m/0.5 m, are shown in Fig. 13(a) and (b), respectively. With the same layout area and device dimension in the ESD-implanted stacked nMOS, the wider spacing “S” can lead to higher HBM and MM ESD levels. The average HBM ESD level of this ESD-implanted stacked nMOS with a fixed device dimension of W/L = 300 m/0.5 m is slightly improved from the original 6.45 kV (with m) to become 6.65 kV (with m), as shown in Fig. 13(a). However, the averaged MM ESD level of this ESD-implanted stacked nMOS, with W/L = 300 m/0.5 m, is significantly improved from the original 350 V (with m) to become 500 V (with m), as that shown in Fig. 13(b). The MM ESD level can be greatly improved 43% by using the new proposed N_ESD implantation method.
Fig. 12. Dependence of HBM and MM ESD robustness on the channel width of ESD-implanted stacked nMOS withS = 0 or 1.5 m.
Fig. 13. Dependence of (a) HBM, and (b) MM, ESD robustness on the blocking layout spacing “S” in the ESD implantation region of the stacked nMOS.
The ratio between the HBM and MM ESD levels on the layout spacing “S” of the ESD-implanted stacked nMOS with W/L = 300 m/0.5 m are further compared in Fig. 14. The HBM/MM ESD level ratio of the ESD-implanted stacked
nMOS has a value of 18.4 when the spacing m.
As seen in Fig. 14, this HBM/MM ESD level ratio can be decreased to 13.3, when the spacing “S” is enlarged to 3.9 m
Fig. 14. Dependence of the HBM/MM ratio on the blocking layout spacing “S” in the ESD implantation region of stacked nMOS.
in the ESD-implanted stacked nMOS. From the experimental results, the new proposed N_ESD implantation method can significantly increase the MM ESD level of the stacked nMOS devices in subquarter-micron CMOS processes. The HBM/MM ESD level ratio can be successfully decreased 28% by using the new proposed N_ESD implantation method. This tendency is also consistent with that of ggnMOS. However, the HBM ESD levels of the stacked nMOS drawn with a wider “S” have a little improvement. Future work on this point, including device simulation and failure analysis, will be performed to optimize the new proposed ESD implantation method for application on the IC products.
V. CONCLUSION
On-chip ESD protection design with a new N_ESD implan-tation method to significantly improve ESD robustness of both ggnMOS and stacked-nMOS devices, especially MM ESD robustness, has been practically verified in a 0.25- m CMOS process. Moreover, the HBM/MM ESD level ratio of both single and stacked nMOS is also decreased. The proposed ESD implantation method, which is process compatible to general CMOS processes with an additional noncritical mask layer of light-doping ESD implantation, is very suitable for using in IC products to improve MM ESD robustness without adding any extra silicon area.
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Design Division of CCL/ITRI. In 2000, he was an Associate Professor in the Department of Electronics Engineering, National Chiao-Tung University. In the field of reliability and quality design for CMOS integrated circuits, he has published over 150 technical papers in international journals and conferences. He holds 140 patents on the reliability and quality design for integrated circuits, of which 55 are U.S.-held patents. His inventions regarding ESD protection design and latchup prevention methods have been widely used in modern IC products. He has been invited to teach or aid in ESD protection design and latchup prevention by more than 150 IC design houses and semiconductor companies in the Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. or in the Silicon Valley, San Jose, CA. His research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed or mixed-voltage I/O interface circuits, sensor circuits, and semiconductors.
Dr. Ker has also received many research awards from ITRI, the Dragon Thesis Award (by Acer Foundation), National Science Council, and National Chiao-Tung University. He has been a Member of the Technical Program Committee and as Session Chair of some International Conferences. He was elected as the first President of the Taiwan ESD Association in 2001.
Jeng-Jie Peng (M’00) received the B.S. degree from the Electrical Engineering Department, Ta-Tung Institute of Technology, Taipei, Taiwan, R.O.C. in 1994, and the M.S. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 2002.
Currently, he is a member of the ESD team in the SOC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, R.O.C. He has over six years of experience in IC physical design and layout. His research interests include on-chip ESD/latchup protection design, semiconductor device physics, IC product engineering, IC physical design, and semiconductor process.
