Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

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Gate-to-drain capacitance verifying the continuous-wave green laser crystallization

n-TFT trapped charges distribution under dc voltage stress

Zhen-Ying Hsieh, Mu-Chun Wang, Shuang-Yuan Chen, Chih Chen, and Heng-Sheng Huang

Citation: Applied Physics Letters 95, 253503 (2009); doi: 10.1063/1.3275728 View online: http://dx.doi.org/10.1063/1.3275728

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Gate-to-drain capacitance verifying the continuous-wave green laser

crystallization n-TFT trapped charges distribution under dc voltage stress

Zhen-Ying Hsieh,1Mu-Chun Wang,1,2,a兲 Shuang-Yuan Chen,1Chih Chen,3and

Heng-Sheng Huang1

1

Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei 10601, Taiwan

2

Department of Electronic Engineering, Ming-Hsin University of Science and Technology, Hsinchu 304, Taiwan

3

Department of Material Science and Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan

共Received 22 July 2009; accepted 27 November 2009; published online 23 December 2009兲 In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The共continuous-wave green laser crystallization兲 n-channel thin-film transistors 共TFTs兲 were forced by dc voltage stress, VG= VD. The gate-to-drain capacitance, CGD

− VG, with varying frequency of applied small signal was developed. To probe the distribution of

these defects, the difference共initial capacitance values minus stressed capacitance values兲 of CGD

关doi:10.1063/1.3275728兴

The continuous-wave green laser crystallization共CGLC兲 n-TFT had been manufactured successfully with its excellent output characteristic and high mobility.1,2 The high carrier mobility of LTPS-TFTs is one of candidate for fabricating driver integrated circuit in TFT process. However, most of TFTs were made on quartz or glass substrate with no sub-strate共or bulk兲 terminal, and hence, there is seldom measure-ment techniques, such as charge-pumping or gated-diode methods, can be used to realize the shift in threshold voltage. In this study, as CGLC n-TFT was forced by the dc voltage stress, VG= VD, electrons injected into gate insulator and

break the Si–H bond on the interface between channel and gate insulator. Moreover, there are a large number of Si–H bonds at the grain boundary of channel layer, and hence, after stressed, traps will be produced. The CGD− VG curve,

which was reported in several literatures,3–5was adopted in-stead of I-V curves to analyze the characteristic of CGLC n-TFT after dc voltage stressed. The stress voltage was gate voltage was equal to drain voltage and can be referred to some lectures.6–8 The stretched and shifted C_GD− V_Gcurve was attributed to the increased of oxide trapped charges, in-terface states, and deep trap states as TFT devices were stressed by the dc voltage. The TCADtool was performed to simulate the vertical and lateral electrical field while stress-ing, and the result of TCAD assisted in verifying the location of oxide trapped charges and deep trap states.

A transparent quartz glass was employed as a substrate. Nitride layer共SiN_x兲, buffer silicon dioxide 共SiO₂兲, and amor-phous silicon共a-Si兲 films were sequentially deposited on this substrate. The nitride layer is used to form a barrier layer between substrate and buffer oxide and gather the mobile ions, not to influence the electrical characteristics of TFTs. The buffer SiO2 may reduce the stress effect between a-Si

and SiN_x. Then, the continuous-wave green laser, diode pumped solid state CW laser共l=532 nm 关second harmonics 共2␻兲 of Nd:YVO4兴, irradiated on a-Si film to produce a

numbers of grain in channel as a gate channel. Next, the gate dielectric TEOS-SiO2共tetraethoxysilane兲 was deposited with

100 nm thickness by plasma-enhanced chemical vapor depo-sition technology at 300 ° C. Furthermore, the active region of a TFT transistor on the CGLC poly-Si was fabricated.

The dc voltage stress condition was VG= VD= 16 V. The

stress and measurement instruments are Keithley 4200 semi-conductor parameter analyzer and Agilent 4284A LCR meter. A simple illustration of the CGLC n-TFT is presented in Fig. 1. High lateral voltage共VD兲 will accelerate the

flow-ing electrons in the channel and cause impact ionization, and hence damage which is near drain side have been raised from these hot electrons. In addition, high vertical voltage 共VG兲

will attract the flowing electrons and move toward the inter-face of silicon channel and gate oxide insulator. Therefore, the interface and insulator may be damaged during stressing. The impact ionization in Fig. 1 was led by hot carrier effect 共HCE兲 which causes a formation of electron-hole-pairs, EHPs.9,10 The generation electrons injected into gate oxide layer, which can be referred to lucky current model, to form oxide trapped charges and interface states.11Otherwise, the generation holes reflowed to source terminal causing grain boundary states. The path of hole reflowing is de-scribed in Fig. 1.12 Therefore, a shift of threshold voltage

a兲_{Electronic mail: [email protected].}

10 100 1000 10000 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Stress voltage = 16 V VTH s hif t (V)

Stress time (sec.)

W / L=25µm/ 15 µm Stress temperature = 25o C Poly-Si Oxide Poly-gate n+ n+ VG=16 V VD=16 V D S VS Hole drift

FIG. 1. 共Color online兲 An illustration of cross-section view of CGLC n-TFT, hot carrier effect on CGLC n-TFT, and shift in threshold voltage on CGLC n-TFT under dc voltage stress.

APPLIED PHYSICS LETTERS 95, 253503共2009兲

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was observed in Fig. 1. The threshold voltage shift in this work was attributed to the dangling bonds and fixed oxide trapped charges. The flowing electrons in the channel were attracted by gate voltage, at this moment in time; silicon-hydrogen共Si–H兲 bonds were easily broken due to the colli-sion from flowing electrons. The broken bonds became dan-gling bonds then degrading the drain current of device. In a word, as CGLC n-TFT was forced by dc voltage stress, it may induce oxide trapped charges, deep trapped states, and few of interface states since HCE.

An abbreviated graph in Fig. 2 presented the gate-to-drain capacitance共CGD兲 versus gate voltage. CGD− VGcurve

was reported to analyze device characteristic after stressed.7 In order to verify grain boundary trapped states or fixed gate trapped charges effect on device, the frequency modulation of applied small signal, which were from 1 MHz to 50 kHz, was given. From the experimental data, a horizontal shift on

CGD− VGcurve was observed before and after stressed and a

distortion at the tail of 50 kHz had been discovered. How-ever, the difference of before and after stressed CGD− VG

curve 共initial capacitance curve minus stressed capacitance curve兲 in Fig.2 clearly represented the feature trend which can be divided into three region, including VG⬍−3 V,

−3 V⬍V_G⬍1.25 V, and V_G⬎1.25 V.

For VG⬍−3 V, the TFT device was accumulation mode that CGD can be consider as 共COL 储CSpa兲.13 The capacitor

model was illustrated in Fig. 3共a兲. Supposing the overlap capacitor was damaged, the CGD− VGcurve should be shifted

or depends on the applied frequency. However, the difference of capacitance approached to zero showed that the TFT de-vice exhibited no damage except channel region after stressed.

The region of −3 V⬍VG⬍1.25 V showed frequency

independence, but gate bias dependence. Gate bias deter-mined the inversion charges共electrons兲 which below the gate oxide. The inversion charges came from the drain terminal due to this terminal was connected to ground. The inversion layer was initially formed near the drain site at the channel region. As gate voltage increased, the inversion layer ex-tended into the channel which can be seen in Fig. 3共b兲. The extended inversion layer was considered as a conductor which was modulated by gate voltage. Therefore, as gate voltage induced the inversion charges, the gate oxide trapped charges had been revealed in CGD− VG curve. Most of the

gate oxide trapped charges were resulted from the generation electrons of EHPs. Typically, EHPs was strongly relative to electrical field while stressing, and hence, Fig.3共d兲displayed the electrical field simulation of device with the stress con-dition. The peak of vertical electrical field in Fig. 3共d兲 had led the peak value of oxide trapped charges which described in Fig. 2.

The gate-to-drain capacitance started to be frequency-dependent while gate voltage was much than 1.25 V which was around threshold voltage. The frequency-dependent CGD

in Fig. 2 was attributed to the interface trapped states and grain boundary trapped states which were enhanced revealed by vertical and lateral electrical field, respectively. However, the amount of interface trapped charge was not greater than grain boundary trapped state,14 and hence, the frequency-dependent C_GD was dominated by boundary trapped states. The frequency-dependent CGD was appeared at large gate

voltage. As gate voltage was above threshold voltage, elec-trons 共for n-TFT兲 were accumulated under gate oxide layer. In the meantime, the interface trapped states and grain boundary trapped states easily caught the electrons, and then, decreased source-to-drain current. The peak A in Fig. 2 is resulted from the horizontal shift which can be observed in abbreviated graph of Fig. 2. For the peak B, this phenom-enon speculated induces from the distribution of deep trapped states.6

For CGD− VG measurement, the source terminal was

floated so that most of electrons were provided from drain terminal. An illustration of the gradient of electron concen-tration was shown in Figs.3共a兲–3共c兲. Electrons filled in ver-tical were rapider than in lateral. Therefore, the C_GDrevealed frequency- and gate voltage-dependent in this work. More-over, the grain boundary trapped states depended on impact ionization which was determined by lateral electrical field. Consequently, from the TCAD simulation result, the most damaged region occurred in deep region labeled on Fig.3共d兲. In this study, gate-to-drain capacitance had been investi-gated to analyze the CGLC n-TFT under dc voltage stress,

VG= VD= 16 V. From the experimental data, the CGD− VG

curve can be divided into three regions. The first region 共VG⬍−3 V兲 showed no damage while stressing. The second

-10 -5 0 5 10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 Capacitance in it ia l -Capacitance stre sse d (fF) V_G(V) C_Diff._1MHz C_Diff._900kHz C_Diff._500kHz C_Diff._100kHz C_Diff._50kHz Two peaks Peak A Peak B -10 -5 0 5 10 520 530 540 550 560 570 500 550 600 650 700 750 800 C apacitance (fF) VG(V) C_Fresh_1MHz C_3000-s_1MHz C apacitance (fF) C_Fresh_50kHz C_3000-s_50kHz

FIG. 2. 共Color online兲 The difference of before and after stressed CGD

− VG curve 共initial capacitance curve minus stressed capacitance curve兲

clearly represented the feature trend. The abbreviated graph presented the gate-to-drain capacitance共CGD兲 vs gate voltage. CGD− VGcurve.

Drain VG< -3 V COL CC COX CSi Contact CSpa. REff. (a) Drain CINV CC Contact CSpa. VGD> 1.25 V (c) Drain CINV CC Contact CSpa 1.25 V >VGD> -3 V (b)

Grain boundary trapped states 200 nm

The concentration of deep trapped states

(d) Interface trapped states

Fixed charges Drain Gate Electrostatic Potential 3.4 x 10-1 1.0 x 101 1.7 x 101 The concentration of fixed trapped charges

FIG. 3. 共Color online兲 The capacitor model as 共a兲 gate voltage is less than ⫺3 V 共VG⬍−3 V兲, 共b兲 gate voltage is between ⫺3 and 1.25 V 共−3 V

⬍VG⬍1.25 V兲, and 共c兲 gate voltage is greater than 1.25 V 共VG

⬎1.25 V兲. 共d兲 The simulation of vertical and lateral electrical field from

TCADtool.

253503-2 Hsieh et al. Appl. Phys. Lett. 95, 253503共2009兲

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region 共−3 V⬍V_G⬍1.25 V兲 revealed the oxide trapped charge influencing CGD. The third region共VG⬎1.25 V兲

de-scribed a frequency-dependent CGD. As gate voltage

in-creased, the inversion layer which was considered by inver-sion charges determined the CGD component. Therefore,

combining the TCADelectrical field simulation, the distribu-tion of oxide trapped charge and grain boundary trapped charge can be realized.

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